JP4457648B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a plurality of LSI chips are incorporated in one package.

FIG. 6 is a conceptual diagram of a conventional semiconductor device.
In recent years, in order to obtain a high density, a high degree of integration, and a high function, a semiconductor device in which a plurality of LSI chips (LSI chip A51 and LSI chip B52) are placed in one package 91 as shown in the figure has been developed. . This type of semiconductor device 90 has been tested in a state where a plurality of LSI chips A51 and LSI chips B52 are connected (see, for example, Patent Document 1).
Therefore, when the LSI chip B52 is tested (for example, an operation test), some of the terminals in1 (62) do not exist as external terminals of the package 91. Therefore, the signal input to the terminal in1 (62) is the LSI chip. It is necessary to operate and give A51.

Further, as a test pattern used for the test, it is necessary to consider the operations of both the LSI chip A51 and the LSI chip B52. For example, when it is desired to change the input signal terminal in1 (62) of the LSI chip B52 from Hi (hereinafter referred to as “H”) to Low (hereinafter referred to as “L”), it is the output terminal of the LSI chip A51. It is necessary to change the terminal out2 (55) from H to L, and the terminal out1 (61), which is the output terminal of the LSI chip B52, is connected only to in2 (56) of the LSI chip A51. Since it is not connected to a terminal, the operation of the LSI chip A51 must also be considered.
This leads to a possibility that the number of test patterns increases as compared with the case where the LSI chip B52 is tested alone, and it may be possible that a sufficient test cannot be performed in some cases. The increase in the number of test patterns also leads to an increase in the inspection cost of the semiconductor device, and the fact that a sufficient test cannot be performed means that selection for detecting defective products cannot be performed.

FIG. 7 is a conceptual diagram of another conventional semiconductor device.
As shown in the figure, all the terminals of the LSI chip A51 and the LSI chip B52 are exposed to the outside of the package 101, and the connection of the LSI chip A51 and the LSI chip B52 is connected to the terminal 16 outside the package 101 as indicated by a broken line. 17 and terminals 20 and 21 are connected, there is a concern that the increase in the number of external terminals may lead to an increase in the size of the package 101.
For this reason, there has been proposed a semiconductor integrated circuit capable of reducing the number of test patterns and reducing the product cost by shortening the test time (see, for example, Patent Document 2).
Japanese Patent Laid-Open No. 2003-4808 JP-A-1-196158

However, since the conventional technique shown in FIG. 7 performs a test on a plurality of functional blocks of the LSI chip A51 and the LSI chip B52 incorporated in one semiconductor device 100 for each functional block. The test is not performed by electrically separating the LSI chip A51 and the LSI chip B52 one by one.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of simultaneously performing individual tests of a plurality of LSI chips built in one package.

In order to solve the above-mentioned problem, the invention according to claim 1 is a semiconductor device in which a plurality of LSI chips are electrically connected to each other and incorporated in one package. The selector circuit that switches the output signal of each LSI chip from the other connected LSI chip to the outside of the package is sometimes different from the terminal for normal operation of the package. A plurality of test terminals which are arranged at positions and which exchange signals with the outside of the package at the time of testing; terminals for inputting signals from outside of the test terminals; and inputs for the LSI chips Other selectors that cut between the test terminal and the input terminal of each LSI chip during normal operation. Has a circuit, by reducing the distributed capacitance between the terminal for the test of the respective LSI chips, characterized in that the send transmission signals between the respective LSI chips at a high speed.

According to a second aspect of the invention, in the invention according to the first SL placement, the selector circuit includes an output terminal connected to an output terminal of said test terminal signal to output a high impedance is inputted to the normal It is characterized by that.

According to a third aspect of the present invention, in the mounting according to claim 1 or 2 SL, the package together with a package for the BGA or PGA, the plurality of test terminals in a plane surrounded by a ball grid or pins It is characterized by being arranged in.

The invention according to claim 4 is the invention according to any one of claims 1 to 3 , wherein the package is a full-grid array BGA package or a PGA package, and the plurality of test terminals are normally used. It is set to a ball or pin grid that is not used.

  Since the output signal of the LSI chip can be freely output from the connected LSI chip to the outside of the package by the selector circuit, it is possible to provide a semiconductor device capable of simultaneously performing individual tests of a plurality of LSI chips incorporated in one package. Can be realized.

FIG. 1 is a conceptual diagram showing an embodiment of a semiconductor device of the present invention.
As shown in FIG. 1, the semiconductor device 10 includes a plurality of (two, but not limited) LSI chips A12 and LSI chips B13 in one package 11, and each LSI chip A12 and LSI chip is incorporated. This is a semiconductor device in which the connection between B13 is performed inside the package 11. In order that the semiconductor device 10 can be executed at the same time even in a state where a test similar to a test in which each LSI chip A12 and LSI chip B13 are individually packaged is packaged. The LSI chip A, B has a built-in selector circuit (hereinafter referred to as “selector”), a test switching terminal for switching from normal use to a test state, LSI chip A12, LSI It is characterized in that a test terminal used only for testing the chip B13 is provided at a terminal portion which is not normally used in the package.

  As shown in FIG. 1, an LSI chip A12 containing a selector A14 and an LSI chip B13 containing a selector B15 are built in one package 11. The LSI chip A12 is connected to two terminals in1 (30) and in2 (27), a control terminal TESTA28, output terminals out1 (29) and out2 (37), and an output terminal of the selector A14. Two terminals 25 and 26 are provided. The LSI chip B13 has two terminals in1 (36) and in2 (32), a terminal TESTB33, terminals out1 (38) and out2 (31), and two terminals 34 and 35 connected to the output terminal of the selector B15. .

The package 11 has a plurality of test terminals (nine but not limited to 9 in the figure) in addition to terminals (not shown) for performing a normal operation. As test terminals, a selector A14, a terminal TEST22 for inputting a control signal to the selector B15, terminals INA24, INB19, TinA21, TinB17 which are test signal input terminals, and terminals OUTA23, OUTB18, ToutA16 which are output terminals. , ToutB20.
The selector A14 has one signal input terminal connected to the terminal out2 (37) of the LSI chip A12, one control signal input terminal connected to the terminal TESTA of the LSI chip A12, an output terminal 25 of the LSI chip A12, 26 and two data output terminals connected to each other. The selector A14 includes, for example, two tristate (registered trademark) buffers having input terminals connected in common.
In the selector A14, when the control signal is not input to the control signal input terminal, the output terminal on the terminal ToutA side is in a high impedance state (for example, the output terminal is opened), and the control signal is input to the control signal input terminal. When the signal is input, the output terminal on the connection side LSI chip B13 side is in a high impedance state.

  Similarly to the selector A14, the selector B15 includes two tristate (registered trademark) buffers having input terminals connected in common. When no control signal is input to the control signal input terminal, the output terminal on the output terminal ToutB side is When the control signal is input to the control signal input terminal, the output terminal on the connection side LSI chip A12 side is in the high impedance state.

That is, in the semiconductor device 10 of the present invention, as shown in FIG. 1, one test-dedicated terminal (TESTA 28, TESTB 33) is provided on each of the LSI chip A12 and LSI chip B13, and these test-dedicated terminals 28, 33 are provided. Is controlled (ON / OFF of voltage for turning ON / OFF the selector A14 and the selector B15), so that a test signal is input to a designated terminal of the LSI chip A12 and further connected to another LSI chip B13. It is possible to set the output terminal to be in a high impedance state, and a test terminal used only when testing the LSI chip A12 and LSI chip B13 is provided at a terminal portion that is not normally used in the package 11. To do.

The first embodiment of the present invention will be further described with reference to FIG .
The device shown in FIG. 1 is a semiconductor device in which two LSI chips, LSI chip A12 and LSI chip B13, are built in one package 11, and is dedicated to testing provided in each LSI chip A12 and LSI chip B13. By controlling the terminals (TESTA28 and TESTB33), the LSI chip A12 and the LSI chip B13 can be tested in parallel so that the selector A14, the selector B15, and the terminal (TinA21) used only when testing the LSI chip A12 and the LSI chip B13. , ToutA16, TinB17, ToutB20).

  Here, “test can be performed in parallel” means that the two selectors A14 and B15 are operated simultaneously, and the two LSI chips A12 and B13 are simultaneously connected to the test terminals TinA21, ToutA16, TinB17, and ToutB20. The test signals (for example, signals of “1” logic level, that is, H) are input to the test terminals TinA21 and TinB17, respectively, and the voltage at the output terminals ToutA16, ToutB20, OUTA23, and OUTB18 This refers to measuring a waveform or the like.

FIG. 2 is a bottom view of the package of the semiconductor device shown in FIG.
In FIG. 2, as an example of the package 11 in which the LSI chip A <b> 12 and the LSI chip B <b> 13 are incorporated, a bottom surface showing a terminal arrangement of a BGA (Ball Grid Array) is shown. Are used as terminals (TinA21, ToutA16, TinB17, ToutB20) used only when testing the LSI chip A12 and LSI chip B13. This is because the terminal 40 that is normally used is provided on the outer periphery of the package 11, so that the semiconductor device 10 of the present invention is mounted and connected to another component or another LSI package on a printed circuit board or the like. This is advantageous because it facilitates connection and improves inspection efficiency.
2 shows a case where the total number of terminals (the number of balls) is 200, the present invention is not limited to this, and even if the number of balls is 200 or more, the semiconductor device is 200. It may be less than one. In this embodiment, the terminal 40 is provided on the outer peripheral portion of the package 11 and the test terminal 42 is provided on the central portion of the package 11. However, the present invention is limited to this. Instead, it may be a full grid array type. Further, although the case of the BGA type semiconductor device has been described in the present embodiment, the present invention is not limited to this, and may be a PGA (Pin Grid Array) type semiconductor device.

When testing the LSI chip A12 and the LSI chip B13, the selector A14 is connected to the terminal out2 (37) by designating that the logic level of the terminal TEST22 is opposite to that when the semiconductor device 10 functions as a product. The signal is output to the terminal ToutA16, and the output terminal of the selector A14 connected to the terminal in1 (36) of the LSI chip B13 outputs a high impedance.
Similarly, the selector B15 outputs a signal from the terminal out1 (29) to the terminal ToutB20, and the output terminal of the selector B15 connected to the terminal in2 (27) of the LSI chip A12 outputs a high impedance.

  By realizing the connection as described above, when testing the LSI chip A12, a test signal can be input through the terminal INA24 and the terminal TinA21, and the test result can be determined at the terminal OUTA23 and the terminal ToutA16. When testing LSI chip B13, a test signal is input from INB19 and TinB17, and the test result is determined at terminal OUTB18 and terminal ToutB20.

Further, in the normal operation in which each LSI chip A12 and LSI chip B13 function as products other than during the test, the logic of the terminal TEST is specified to be opposite to that during the test, and the terminal out2 (37 of the LSI chip A12) ) Is connected to the terminal in1 (36) of the LSI chip B13 by switching the selector A14, and the output of the selector A14 connected to the terminal ToutA16 is set to a high impedance state.
Similarly, the signal from the terminal out1 (38) of the LSI chip B13 is connected to in2 (27) of the LSI chip A12 by switching the selector B15, and the output of the selector B15 connected to the terminal ToutB20 is in a high impedance state. To.
In this way, since the terminals used during the test are in a high impedance state during normal operation, the terminals can be handled as open.

(Explanation of effect)
Even in the state of a semiconductor device in which multiple LSI chips are built in one package, it is possible to perform the same test as when each LSI chip is tested as an individual component one by one, and a sufficient test can be performed By doing so, it is possible to obtain the effect of preventing an increase in the inspection cost and the effect of reducing the mixing of defective products into the final product.

(Second Embodiment)
A second embodiment will be described with reference to FIG.
FIG. 3 is a conceptual diagram showing another embodiment of the semiconductor device of the present invention. In addition, the same code | symbol was used for the member similar to embodiment shown in FIG.
In the second embodiment, the selector A14 incorporated in the LSI chip A12 in the first embodiment is brought out of the LSI chip A12, the test dedicated terminal TESTA28 (see FIG. 1) is deleted, and the like. The selector B15 built in the LSI chip B13 is taken out of the LSI chip B13, the test-dedicated terminal TESTB3 (see FIG. 1) is deleted, and the LSI chip A51, LSI chip B52, selector A53, and selector B54 are packaged. It is built in. The semiconductor device 50 shown in FIG. 3 is the same as that of the first embodiment in the operation when testing the LSI chip A51 and the LSI chip B52 and the normal operation other than the test.

(Third embodiment)
FIG. 4 is a conceptual diagram showing another embodiment of the semiconductor device of the present invention.
The semiconductor device 70 as the third embodiment can realize the functions of the selector A53 and the selector B54 as an LSI chip different from the LSI chip A51 and the LSI chip B52.

(Fourth embodiment)
FIG. 5 is a conceptual diagram showing another embodiment of the semiconductor device of the present invention.
In the semiconductor device 80 as the fourth embodiment, another selector 82 is newly provided between the terminal TinA21 and the terminal in2 (56) of the LSI chip A51, and the terminal TinA21 is in the normal operation under the control of the terminal TEST22. Is electrically disconnected to reduce the wiring capacity (distributed capacity) hanging from the terminal TinA21, thereby transmitting between the terminal out1 (61) of the LSI chip B52 and the terminal in2 (56) of the LSI chip A51. Signals can be sent at high speed. Similarly, another selector 81 is newly provided between the TinB terminal 17 and the terminal in1 (62) of the LSI chip B52, and the wiring capacity (distributed capacity) hanging from the terminal TinB17 is reduced during normal operation by the control of the terminal TEST22. In addition, a transmission signal between the terminal out2 (55) of the LSI chip A51 and the terminal in1 (62) of the LSI chip B52 can be sent at high speed.
In the present embodiment, the selectors 81 and 82 are provided outside the LSI chip A51 and the LSI chip B52. However, the present invention is not limited to this, and the first embodiment. As described above, each of the LSI chips A51 and B52 may be built in, or in the LSI chip 70 as in the third embodiment.

It is a conceptual diagram which shows one Embodiment of the semiconductor device of this invention. It is a bottom view of the package of the semiconductor device shown in FIG. It is a conceptual diagram which shows other embodiment of the semiconductor device of this invention. It is a conceptual diagram which shows other embodiment of the semiconductor device of this invention. It is a conceptual diagram which shows other embodiment of the semiconductor device of this invention. It is a conceptual diagram of the conventional semiconductor device. It is a conceptual diagram of another conventional semiconductor device.

Explanation of symbols

10 Semiconductor Device 11 Package 12 LSI Chip A
13 LSI chip B
14 Selector A (Selector circuit A)
15 Selector B (Selector circuit B)
16 ToutA (terminal)
17 TinB (terminal)
18 OUTB (terminal)
19 INB (terminal)
20 ToutB (terminal)
21 TinA (terminal)
22 TEST (terminal)
23 OUTA (terminal)
24 INA (terminal)

Claims (4)

In a semiconductor device in which a plurality of LSI chips are electrically connected to each other and incorporated in one package,
A selector circuit disposed between the LSI chips and configured to switch an output signal of each LSI chip from a connected other LSI chip to the outside of the package by a signal from the outside of the package at the time of testing;
A plurality of test terminals which are arranged at positions different from the terminals for normal operation of the package, and which are used to exchange signals with the outside of the package at the time of testing;
The test terminal is disposed between a terminal to which an external signal is input and an input terminal of each LSI chip, and is used for input of the test terminal and each LSI chip during normal operation. Another selector circuit that cuts the connection between the terminals is provided, and the transmission capacity between the LSI chips is transmitted at high speed by reducing the distributed capacitance between the test terminals and the LSI chips. A semiconductor device characterized by that. Said selector circuit according to claim 1 Symbol mounting semiconductor device, characterized in that the signal as an output terminal connected to the output terminal during normal outputs a high-impedance input of said test terminals. Together with the package is a package for the BGA or PGA, the semiconductor according to claim 1 or 2 SL placing the plurality of test terminals is characterized by being located in a plane surrounded by a ball grid or pins apparatus. Together with the package is a package for the BGA or PGA full grid array, any of claims 1 to 3, wherein the plurality of test terminals in a normal is set to the ball or pin grid not used A semiconductor device according to claim 1.

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