JP4457551B2 - Integrated circuit protection against electrostatic discharge and overvoltage - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to the protection of integrated circuits from electrostatic discharge and other overvoltages. The invention particularly relates to the integration of the circuits necessary for protection.
[0002]
[Prior art]
A protection circuit against electrostatic discharge (ESD) is intended to protect an electronic circuit against electrostatic discharge coming from its terminals.
[0003]
FIG. 1 shows an example of a conventional electronic protection circuit 1. The function of this circuit is to short-circuit the supply lines 2 and 3 of the integrated circuit when an overvoltage is generated by electrostatic discharge applied to the pad 4 of the circuit. The midpoint 5 of this series of connections is electrically connected to the pad 4. Diodes D1 and D2 are biased to turn off in normal operation. Thus, in the example of FIG. 1, line 2 forms a positive supply line and line 3 forms a negative supply line (generally ground). The circuit 1 also includes a MOS transistor MOSSWI between the supply lines 2 and 3, and its gate is connected to at least one ESD protection control circuit 6.
[0004]
The electrostatic type disturbance received by the pad 4 is formed by positive or negative charges. When this type of charge appears, one of the diodes D1 and D2 conducts. Next, the transistor MOSSWI is turned on to short-circuit the supply lines 2 and 3, thus conducting and dissipating excess charge. Damage to the core can be avoided by passing charge through the transistor MOSSWI. A resistor 7 is provided between the pad 4 and the integrated circuit core to ensure that the resistance of the electrical circuit due to the diode D1 or D2 is smaller than the resistance through the circuit core.
[0005]
Accordingly, the circuit 6 (CT) sets a time constant (τ) that triggers the transistor MOSSWI when electrostatic discharge occurs, that is, when a current flows through the diode D1 or D2. The circuit 6 is generally formed of a resistive and capacitive circuit (RC cell).
[0006]
Transistor MOSSWI, which shorts the supply conductor, is also used as protection against overvoltage for the maximum value allowed in integrated circuit technology. In this case, another control circuit 8 (OVT) has a function of detecting an overvoltage (for example, with respect to a predetermined voltage threshold Vref) and turning on a transistor MOSSWI associated with the circuit. Thus, integrated circuits are protected not only from electrostatic discharge, but also from overvoltage whatever the source.
[0007]
In the following description, an electronic protection circuit for protection against electrostatic discharge (ESD) will be exemplified. It also includes protection against overvoltage unless otherwise specified.
[0008]
Of particular note among the features of the electronic protection circuit 1 is that the on-state resistance (RdsON) of the transistor MOSSWI is made as small as possible to achieve its protective action and prevent overvoltages from propagating elsewhere in the circuit. Is to do. As a result, the transistor MOSSWI (generally an N channel MOS transistor) has a large size in order to conduct excess charge rapidly.
[0009]
The control circuit 6 for detecting an overvoltage generally has to have a low time constant (in many cases 200 ns or less).
[0010]
As a result, it is generally desirable to place the transistor MOSSWI of the protection circuit as close as possible to the pad 4 to be protected. This is to reduce the resistance provided by the actual supply line and the interval between the pad and the transistor terminal.
[0011]
Further, conventionally, the control circuit itself is arranged as close as possible to the transistor MOSSWI to reduce the resistance caused by the conductive path between the control circuit forming the capacitive element of the control circuit 6 and the gate of the transistor MOSSWI.
[0012]
FIG. 2 is a top view of a conventional integrated circuit 10 having pads 4 associated with an ESD protection circuit. In the example of FIG. 2, three pads 4 (PAD) and two ESD protection circuits 1 are shown. For the reasons of proximity mentioned above, the protection circuit 1 is placed in the so-called crown position of the integrated circuit. The crown encloses a circuit core that integrates different functions associated with a particular application of the integrated circuit.
[0013]
The crown of circuit 10 generally includes a feed rail 11 (BUS) that includes at least two conductors 12 and 13 that carry a positive power supply voltage VP and a negative power supply voltage VN of the integrated circuit. If necessary, the feed rail 11 can include other conductors, such as ground and negative supply voltage if the integrated circuit has a positive supply voltage.
[0014]
The power supply bus can be arranged partially in the periphery of the integrated circuit or differently (eg in the center). The notation of the core, regardless of its location, relates to an application specific to the integrated circuit and surrounds the integrated element that is powered by any form of bus.
[0015]
Each transistor MOSSWI of circuit 1 is connected to conductors 12 and 13 of the feed bus by conductors 14 and 15, respectively. Similarly, each pad 4 is connected to the conductors 12 and 13 via diodes (D1, D2 in FIG. 1 and not shown in FIG. 2).
[0016]
From the connection pad perspective, two large integrated circuit families are distinguished.
[0017]
The first family is called a pad limiting circuit. Here, a large number of connection pads from the integrated circuit core to the outside condition the actual integrated circuit size due to the perimeter required for the pad arrangement.
[0018]
The second family is called the core limiting circuit and its size is limited by the surface area of the core, not the perimeter for the arrangement of pads.
[0019]
In the first family of circuits, sufficient space can be reserved in the integrated circuit core to form a sufficient number of MOSSWI transistors and their control circuitry to properly protect the integrated circuit from electrostatic discharge. .
[0020]
However, in circuits that are already sized by the integrated circuit core, increasing the size of the core to form the MOSSWI transistor of the ESD protection circuit is detrimental to the circuit. Typically, the protection circuit occupies up to 10% of the chip core size and adversely affects the desired miniaturization.
[0021]
[Problems to be solved by the invention]
An object of the present invention is to provide an integrated circuit having a small-sized electronic protection element.
[0022]
An object of the present invention is to reduce the volume of a core-limited integrated circuit having an electronic protection element.
[0023]
The invention further aims to provide a solution that does not adversely affect the quality of ESD protection or rather improves it.
[0024]
The present invention further aims to provide a solution for protecting an integrated circuit from any type of overvoltage.
[0025]
The present invention further aims to provide a solution that is compatible with current integrated circuit fabrication techniques.
[0026]
[Means for Solving the Problems]
To achieve the above and other objects, the present invention provides:
In an integrated circuit having at least one switch for short-circuiting a supply conductor formed on the rail and having at least one element for electronic protection,
The switch is integrated into the rail under the conductor;
The switch (MOSSWI) is composed of MOS transistors, and their drain and source are each connected to one of the two supply conductors (12, 13) of the integrated circuit,
Before crisp Lumpur (11), another conductor (23) is provided for the control of the gate of the MOS transistor,
The gate of the MOS transistor is placed perpendicular to the supply conductors (12, 13) of the rail, which gate is connected to the other conductor (23) for gate control by a via (27). An integrated circuit is provided.
[0027]
According to an embodiment of the present invention, several switches are controlled by at least one first common circuit.
[0028]
According to an embodiment of the present invention, the first common circuit detects the generation of electrostatic charges.
[0029]
According to an embodiment of the present invention, at least one second control circuit for detecting occurrence of an overvoltage between the supply conductors is included.
[0030]
According to an embodiment of the invention, the control circuit for the short-circuit switch is provided in the core of the integrated circuit.
[0034]
DETAILED DESCRIPTION OF THE INVENTION
In different drawings, the same elements are denoted by the same reference numerals. For clarity, only those elements necessary for understanding the present invention are shown and described. In particular, the application functions of the integrated circuit will not be described in detail. The present invention is applicable regardless of the application of the integrated circuit.
[0035]
A feature of the present invention is that it utilizes the silicon surface under the supply rail of the integrated circuit that integrates the MOSSWI transistor of the electronic protection element against electrostatic discharge or overvoltage.
[0036]
In order to save space, it is conceivable to integrate elements specific to the application of the integrated circuit under the supply rail. However, the above solution is insufficient because the connection of the core circuit of the application requires a metallization layer for interconnection. Currently, in the supply rail, all metallization layers are used to form the actual supply conductor (12, 13 in FIG. 2), reducing the width of the supply rail and increasing its thickness so that the circuit It was large.
[0037]
The present invention takes advantage of the fact that electronic protection element (especially ESD) switches (MOSSWI) and their connections require only positive and negative supply and control signals. Since the supply conductor is already in the rail, the present invention provides for the integration of the MOSSWI transistor on the silicon surface.
[0038]
FIG. 3 shows a top view of an embodiment of the integrated circuit 20 according to the invention in comparison with FIG.
[0039]
A pad for connection to the outside of the core of the integrated circuit 20, and a power supply rail (for example, a periphery) including a conductor 12 carrying a positive power supply voltage VP and a conductor 13 carrying a negative power supply voltage VN (generally ground) Included.
[0040]
According to the invention, the MOSSWI transistor of the electronic protection circuit (ESD and / or overvoltage) is arranged under the conductors 12 and 13 of the feed rail. The connection of the MOSSWI transistor to the conductors 12 and 13 is indicated in FIG. 3 by 21 and 22, which are compared to 14 and 15 in FIG. Control of the MOSSWI transistor of the circuit of the present invention is provided by a conductor 23 that carries a control signal CTRL provided by a control circuit 6 similar to that described above, which comprises an RC cell type delay circuit. The circuit 6 is connected to the feed conductor as usual (not shown in FIGS. 2 and 3).
[0041]
As a feature of the present invention, a single ESD protection control circuit 6 is sufficient for the entire integrated circuit. Although the control circuit is not an element occupying a lot of space in the prior art, the present invention is effective in reducing the volume of the circuit. However, for example, when it is desired to reduce the access resistance of the control signal, several control circuits can be provided. At that time, all the control circuits are connected to the control conductor 23 in parallel.
[0042]
Similarly, for the entire integrated circuit, a single control circuit 8 is sufficient for protection against overvoltage.
[0043]
In order to implement the present invention, a conductor carrying the control signal CTRL must be added to the rail. However, this conductor does not require a large cross section. Therefore, the space it occupies is small. Furthermore, since all metallization layers can be used in the rail, it is not a problem to allocate a small section of one metallization layer to construct this control signal. Conventionally, the two signals appearing on the rail require a large cross-section (supply conductor) for the implementation of the present invention.
[0044]
FIG. 4 is a perspective view of a cross section of the structure of the MOSSWI transistor according to the first embodiment of the present invention. As shown, the transistor is formed perpendicular to the conductors 12 and 13 of the supply rail. This facilitates connection of the drains and sources (not shown) of the transistors by the contacts (and vias) 25 and 26 from the conductors 12 and 13. Therefore, in the embodiment of FIG. 4, a large number of small MOS transistors are distributed under the supply rail 11. The smallness is compensated by connecting many in parallel, and the desired transistor surface area is obtained with a small series resistance.
[0045]
Another advantage of the present invention is that each pad 4 of the integrated circuit necessarily has a group of transistors in close proximity.
[0046]
In the embodiment of FIG. 4, the connection of the gate G of the transistor is contrary to the embodiment of FIG. 3 by a conductor 23 carrying a signal CTRL placed beside conductors 12 and 13, ie inside or outside the supply rail. Done. The connection of the conductor 23 to the gate G is made by one or more contacts and possibly vias 27. Only thick oxide regions 29 are shown on both sides of the gate G in FIG. The transistor can be realized in silicon by conventional techniques.
[0047]
FIG. 5 partially shows the top surface of a second embodiment of the present invention. This embodiment shows the case where the control conductor 23 of the MOSSWI transistor is in the center of the supply rail 11. In the embodiment of FIG. 5, only the rail 11 is shown, and the rail 11 has a structure in which a positive supply conductor 12 is surrounded by two ground conductors 13.
[0048]
As in the embodiment of FIG. 4, the gate G of the MOSSWI transistor is perpendicular to the conductor of the supply rail 11. In the embodiment of FIG. 5, a plurality of vias 27 are shown for connecting the gate G to the conductor 23, while a single via for connecting the drain and source of each transistor to the supply conductor, 25 and 26, respectively. Is shown. However, the number of vias is adapted from case to case according to current and application. In the embodiment of FIG. 5, another series of vias 28 for biasing the integrated circuit board to ground is illustrated.
[0049]
An advantage of the present invention is that the surface occupied by the electronic protection element (especially ESD) is very small compared to the core surface area for application.
[0050]
Another advantage of the present invention is that the distribution of MOSSWI transistors in the protective element is more uniform than in the prior art where the number of protective elements is reduced to minimize the surface area.
[0051]
Of course, variations, modifications and improvements of the present invention are easy to those skilled in the art. In particular, the actual realization of an electronic protection element (ESD or overvoltage), in particular a MOSSWI transistor, is easy for those skilled in the art based on the application and the functional description above. The gate capacitance of the MOSSWI transistor of the present invention is larger than that of the conventional MOSSWI transistor in comparison with the surface area of the transistor. Further, although the formation of the diodes D1 and D2 of the protection circuit will not be described in detail, the diode can be placed as close as possible to the pad 4 outside the rail as in the prior art.
[0052]
The above changes, modifications and improvements are part of this description and are within the spirit of the invention. Accordingly, the foregoing description is by way of example only and does not limit the invention. The invention is limited only by the claims and the equivalents thereof.
[Brief description of the drawings]
FIG. 1 shows a conventional protection circuit against electrostatic discharge and overvoltage.
FIG. 2 is an example of a conventional circuit against an overvoltage of an integrated circuit.
FIG. 3 shows an electronic protection circuit according to the invention.
FIG. 4 is a perspective view of a first embodiment of a MOSSWI transistor relating to a supply rail of an integrated circuit according to the invention.
FIG. 5 shows a second embodiment of a MOSSWI transistor for the supply rail of an integrated circuit according to the invention.
[Explanation of symbols]
4 Pad 6 Control circuit 11 Feed rail 12, 13 Conductor 20 Integrated circuit 21, 22 Conductor 23 Conductor MOSSWI MOS transistor CORE Core

Claims (5)

In an integrated circuit having at least one switch (MOSSWI) for short-circuiting supply conductors (12, 13) formed on the rail and having at least one element (1) for electronic protection,
The switch is integrated into the rail under the conductor;
The switch (MOSSWI) is composed of MOS transistors, and their drain and source are each connected to one of the two supply conductors (12, 13) of the integrated circuit,
Before crisp Lumpur (11), another conductor (23) is provided for the control of the gate of the MOS transistor,
The gate of the MOS transistor is placed perpendicular to the supply conductor (12, 13) of the rail, which gate is connected to the other conductor (23) for gate control by a via (27). An integrated circuit characterized by that.   2. The circuit according to claim 1, wherein several switches (MOSSWI) are controlled by at least one first common circuit (6). The circuit of claim 2, wherein the first common circuit detects the occurrence of electrostatic charges.   3. A circuit according to claim 2, including at least one second control circuit (8) for detecting the occurrence of an overvoltage between the supply conductors. The circuit according to claim 2 or 4, wherein the first common circuit (6) for a short-circuit switch is provided in the core (CORE) of the integrated circuit.

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