JP4445024B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device including a TFT having a small grain crystal grown in a lateral direction as a channel region and a TFT having a large grain crystal grown in a lateral direction as a channel region.

As a display method of the current liquid crystal display, there is an active matrix method in which individual pixels are switched. In the pixel switch, an amorphous silicon thin film transistor (a-Si TFT) which is a kind of field effect transistor is mainly used.
In the technological development of liquid crystal displays, it aims at high definition, high aperture ratio, light weight and low cost. In order to realize these performances, a technique using a polycrystalline silicon thin film transistor (poly-Si TFT) which is a kind of field effect transistor has attracted attention. Poly-SiTFT has a mobility that is two orders of magnitude higher than a-SiTFT, so the device size can be reduced and an integrated circuit can be formed. Is possible.

A method for manufacturing a polycrystalline semiconductor thin film transistor by an excimer laser crystallization method according to the prior art will be described below.
As shown in FIG. 5 (a), a base protective film (for example, a SiO 2 film, a SiN film, a SiN / SiO 2 laminated film, etc.) 102 and an amorphous silicon thin film 103 are deposited on a glass substrate 101. Next, as shown in FIG. 5 (b), when the surface of the amorphous silicon thin film is irradiated with an excimer laser (XeCl, KrF, etc.) 104 that has been shaped into a square shape or a long shape by an optical system, The amorphous silicon thin film 103 is converted from an amorphous structure to a polycrystalline structure through a melting and solidifying process in an extremely short time of 50 to 100 ns by irradiation and heating of the excimer laser 104. When the entire surface of the amorphous silicon film 103 is scanned and heated by the excimer laser 104 in the direction of the arrow 105, a polycrystalline silicon thin film 106 as shown in FIG. 5 (c) is formed. The above process is called an excimer laser crystallization technique. It is used when manufacturing a high-quality polycrystalline silicon thin film on a substrate of a low melting point material such as glass. These are detailed in, for example, “Nikkei Microdevices separate volume flat panel display 1999 (Nikkei BP, 1998, pp. 132-139)”.

  FIG. 5 (d) shows a transistor formed using the polycrystalline silicon thin film 106 of FIG. 5 (c). A gate insulating film 107 such as a SiO2 film is formed on the polycrystalline silicon thin film 106 by film formation. Further, a source impurity implantation region 109 and a drain impurity implantation region 108 are provided. A gate electrode 110 is provided over the source and drain regions and the gate insulating film, a protective film 111 is formed, and a source electrode 112 and a drain electrode 113 are formed. Thus, a TFT capable of controlling the current between the source and the drain by the voltage of the gate electrode is completed.

In general, a TFT used in a pixel portion is intended to hold charges in active matrix control, and does not require extremely high mobility, but rather requires low off-state current.
In order to reduce the off-state current, it is necessary to increase the TFT channel length to such an extent that the aperture ratio is not lowered in order to reduce the electric field strength at the drain end.
On the other hand, TFTs used for driver circuits and arithmetic circuits are required to have high mobility for high-speed operation, and off-state current is not a problem.
For this reason, it is necessary to reduce the size of the TFT because miniaturization of the channel length is particularly effective for speeding up.
Thus, required characteristics and sizes are different between the TFT used in the pixel portion and the TFT used in the drive circuit and the arithmetic circuit.
If these TFTs are not formed on the same substrate all at the same time, the economic effect of integration will be reduced.

However, in the conventional crystallization method, only a poly-Si thin film having a certain crystallinity can be formed. When TFTs having different sizes are formed on the same substrate, the following problems occur.
A large-size TFT has a small variation in characteristics but low performance due to an increase in crystal grain boundaries in the TFT channel region.
A small-size TFT has high performance but large variations in characteristics because it has fewer crystal grain boundaries in the TFT channel region.

  Therefore, in the present invention, a semiconductor layer having two or more kinds of average crystal grain sizes can be formed directly or indirectly on the same substrate, and as a result, it becomes a TFT active layer for TFTs having different sizes. The object of the present invention is to propose a semiconductor device in which the crystal grain size is controlled so that the average number of grain boundaries Na across the current direction in the channel region is constant.

  In order to achieve this object, the present invention is configured as follows.

That is, the invention according to claim 1 is a semiconductor layer provided with a small grain crystal region and a large grain crystal region grown in a lateral direction directly or indirectly provided on the same substrate,
A TFT having a small grain crystal grown in the lateral direction as a channel region;
A TFT having a large grain crystal grown in the lateral direction as a channel region;
Comprising
The average value of the number of grain boundaries across the current direction is the same in the channel region of the small grain crystal grown in the lateral direction and the channel region of the large grain crystal grown in the lateral direction. to.

According to the present invention, when TFTs of different sizes are manufactured on the same substrate, the current in both regions in the channel region of the small grain crystal of the small TFT and the channel region of the large crystal grain of the large TFT. Since the average number of crystal grain boundaries across the direction is the same, there is little variation in characteristics between a large size TFT and a small size TFT, and a high performance semiconductor device can be obtained .

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 shows a schematic diagram of a laser crystallization apparatus used in the present invention.
In the laser crystallization apparatus, an attenuator (attenuator) 2 and a beam profile modulation unit 3 are disposed at the start end of the optical axis a of the laser light source 1, and a semiconductor substrate 5 is disposed at the end via a mirror 4.
In addition, the beam profile measuring unit 6 is arranged in parallel on the semiconductor substrate 5, and the semiconductor substrate 5 and the beam profile measuring unit 6 are fixed to the moving stage 7.
Further, a control personal computer 8 is installed, the beam profile measuring unit 6 is connected to the input side, and the control system of the attenuator 2, the beam profile modulating unit 3, and the moving stage 7 is connected to the output side.

  The attenuator 2 optically modulates the intensity (amplitude) of laser light by adjusting the angle of the dielectric multilayer coating filter, and includes a sensor, a motor, and a control system (not shown).

The beam profile modulation unit 3 modulates the spatial intensity distribution of the laser light, and includes a phase shift mask 31 and an imaging optical system 32.
The phase shift mask 31 generates a reverse peak pattern in which the light intensity is minimized in the phase shift portion by alternately shifting the phase of light passing through the mask pattern to 0 and π, and the semiconductor substrate 5 is generated by this reverse peak pattern. By controlling the position of the first solidified region (crystal nucleus) above, the crystal is laterally grown from there (lateral growth), thereby providing a crystal grain having a large grain size at a designated position.
At this time, a desired beam profile is set according to the shape of the phase shift mask, the distance from the semiconductor substrate 5, the angular distribution of the laser light, and the like.
The phase shift mask 31 also includes sensors, actuators, and a control system (not shown) for exchanging mask patterns and aligning in the optical axis direction.

The imaging optical system 32 is composed of an optical component such as a lens, and irradiates the laser beam while holding the semiconductor substrate 5 at a position defocused from the focal position of the imaging optical system 32.
The shape and width of the reverse peak pattern are controlled by the mask pattern and the defocus amount at this time.
The width of the reverse peak pattern increases in proportion to the defocus amount to the half power.

The beam profile measuring unit 6 receives an ultraviolet excimer laser with a fluorescent plate 61 and converts it into visible light, receives the visible light reflected by the mirror 62 with a CCD 63, and simultaneously measures the intensity and beam profile of the laser light.
The intensity of the laser beam may be measured separately using a semiconductor power meter or the like.
Further, an ultraviolet excimer laser may be directly received by the CCD 63.

The fluorescent plate 61 is installed on the same plane as the semiconductor substrate 5 or on a parallel plane.
When the fluorescent plate 61 is installed on a parallel plane having a step, the movable stage 7 is moved up and down to position the fluorescent plate 61 at the same height as the semiconductor substrate 5 and perform measurement.
Thereby, the beam profile of the laser beam on the substrate surface can be measured under the same conditions as in actual irradiation.

The image received by the CCD 63 is input to the personal computer 8 and sliced by an arbitrary scanning line, and the intensity of the laser beam and the beam profile are measured from the intensity distribution of the image signal.
Then, the manipulated variable is calculated by comparing the measured intensity with a preset target intensity, and the angle of the attenuator 2 is adjusted while feeding back the measured intensity to the target intensity by outputting an operation signal to the attenuator 2. Adjust.
Further, an operation amount is calculated by comparing the measured beam profile with a preset target beam profile, and an operation signal is output to the beam profile modulation unit 3 and the moving stage 7 so that the measured beam profile becomes the target beam profile. The position of the phase shift mask 31 and the height of the moving stage 7 are adjusted while feedback is performed.

  The moving stage 7 can move in the front and rear, left and right, and up and down three-dimensional directions, and includes a sensor, an actuator, and a control system (not shown) for alignment in the in-plane direction and the optical axis direction.

The laser crystallization apparatus used in the present invention is configured as described above. In the laser crystallization process, first, the moving stage 7 is moved in the in-plane direction, and the tip of the optical axis a of the laser light source 1 is set as a beam profile measuring unit. 6 is positioned on the fluorescent plate 61 and irradiated with laser light to measure its intensity and beam profile.
Next, the angle of the attenuator 2, the position of the phase shift mask 31, and the height of the moving stage 7 are aligned so that the measured intensity and the beam profile match a preset target.
Next, the moving stage 7 is moved in the in-plane direction, this time the tip of the optical axis a is positioned in a predetermined crystal region of the semiconductor substrate 5, and laser light having a preset intensity and beam profile is irradiated.
By repeating the above measurement, alignment and irradiation, crystal regions having different TFT sizes in the same substrate but having a constant average value Na of crystal grain boundaries across the current direction in the channel region are formed simultaneously.
Measurement, alignment, and irradiation are not performed alternately in this way. First, all measurements are performed to determine the amount of operation necessary for alignment, and then alignment and irradiation are performed in parallel for each crystal region. You may do it.

As an example of the present invention, an example of creating TFT-A (small size TFT) and TFT-B (large size TFT) having the same characteristics but different sizes is shown below.
First, as shown in FIG. 3A, as a substrate preparation, a first thin film 302 (eg, tetraethylorthosilicate (TEOS) is formed on the surface of an insulator substrate 301 (eg, Corning 1737 glass, fused silica, sapphire, plastic, polyimide, etc.). ) And O2 plasma chemical vapor deposition 300 nm thick SiO2 film, SiN / SiO2 laminated film, alumina, mica, etc.), second thin film amorphous semiconductor on the surface of the first thin film 302 A thin film 303 (for example, amorphous Si or amorphous SiGe having a thickness of 100 nm is formed by plasma chemical vapor deposition). A SiO2 film 305 is formed by plasma chemical vapor deposition (for example, 100 nm thickness) of tetraethylorthosilicate (TEOS) and O2 using SiO2 as a gate insulating film. Next, dehydrogenation of the thin film is performed (for example, heat treatment at 600 ° C. for 1 hour in a nitrogen atmosphere).

Next, laser crystallization is performed using the laser crystallization apparatus of FIG. The laser light source 1 uses a pulsed high energy laser such as a KrF excimer laser.
The laser light emitted from the laser light source 1 passes through the attenuator 2 and the beam profile modulation unit 3 that can modulate the power and the beam profile. As a result, the power and beam profile are modulated. Thereafter, it reaches the moving stage 7 through an optical element such as the mirror 4. A semiconductor substrate 5 is disposed on the moving stage 7. Laser crystallization is performed by irradiating the semiconductor substrate 5 with modulated laser light. The moving stage 7 is provided with a beam profile measuring unit 6 that can measure a beam profile and can also be used as a power meter. This apparatus works in conjunction with a personal computer 8 for measurement, and parameters of the optical system (for example, the angle of the attenuator 2 and the phase shift mask 31) that can modulate the moving stage 7 height z, power, and beam profile so as to have a suitable beam profile. For example).
The beam profile A in FIG. 2 (a) is a small-grain crystal region, and the beam profile B in FIG. 2 (b) is a beam profile in which a large crystal grain crystal region can be formed. The beam profile is set by a system linked to the above-described measurement personal computer 8.
As a result of crystallization using the beam profile A or the beam profile B, poly-Si having a desired crystal grain size is formed. For example, when laser crystallization is performed with the beam profile A, a small crystal grain size region r1 is formed in a selected region as shown in FIG. Further, when laser crystallization is performed in the beam profile B, a large crystal grain region r2 is formed in a selected region as shown in FIG. 2 (b), and the crystal region can be divided depending on the beam profile. .

  Evaluation of the average value Na of the number of crystal grain boundaries crossing the current direction in the channel region of the TFT is performed as follows. As shown in FIG. 4, marking is performed at four locations with a laser marker b or the like so that the edge of the TFT active layer can be seen. After that, the source electrode 312, the drain electrode 313, the gate electrode 309, and the interlayer insulating film 314 shown in FIG. To expose. Thereafter, wet etching is performed for about 30 seconds with a secco etching solution or the like to make crystal grain boundaries stand out. After drying, image observation with a scanning electron microscope is performed. As the image observation apparatus, a surface roughness meter, an atomic force microscope, or the like may be used.

The number of crystal grain boundaries that cross the current direction in the channel region is determined by dividing the two markings in the source portion and the two markings in the drain portion, for example, into 10 equal parts, and the straight lines are parallel to each other. The number of crossings between the straight line and the grain boundary is averaged and calculated.
Since the grain size is controlled by the beam profile, there are crystal grain boundaries in the small grain crystal region more densely than in the large grain crystal region.

The gate length La of TFT-A was 2 μm, the gate length Lb of TFT-B was 4 μm, and the width W was 2 μm.
As shown in FIG. 2, a beam profile A and a beam profile B for obtaining a TFT characteristic capable of achieving the same performance were measured in advance. As shown in FIG. 6, in this case, a desired profile could be determined by the Z value based on the relational data between the stage height Z and the number of grain boundaries per 1 μm.
In this case, the phase shift mask height d = 0μm is constant.
The profile required for TFT-A is Z = 30μm, laser intensity is 500mJ / cm2,
The profile required for TFT-B is Z = 20μm and the laser intensity is 700mJ / cm2,
It was measured that.
Under these conditions, crystallization was performed on a plurality of regions on the substrate.

The produced crystal was crystallized by a beam profile as shown in FIGS. 2 (a) and 2 (b).
The crystal regions manufactured by these methods are patterned with the sizes of TFT-A and TFT-B, respectively, and the following processes are performed. As shown in FIG. 3B, a gate electrode 309 (for example, high-concentration phosphorus-doped polysilicon, W, TiW, WSi2, or MoSi2) is provided on the gate insulating film. Using the gate electrode 309 as a mask, ion implantation is performed to form a source region 311 and a drain region 310. For example, in the case of N-type TFT, ion implantation is performed by injecting P + in the order of 1015 cm −2, and in the P-type TFT, BF 2+ is injected in the order of 1015 cm −2. Thereafter, annealing is performed at 500 to 600 ° C. for about 1 hour using nitrogen as a carrier gas in an electric furnace to activate the impurities. Moreover, you may heat at 700 degreeC for 1 minute by rapid thermal annealing (RTA). Finally, an interlayer insulating film 314 is formed, contact holes are formed, and a source electrode 312 and a drain electrode 313 are formed. As the material of the source electrode 312 and the drain electrode 313, for example, Al, W, or Al / TiN is used.

The evaluation of TFT was performed on a 350 mm × 400 mm substrate at a total of five points including a central position where two diagonal lines were drawn and crossed, and a midpoint between the central position and the four corners of the substrate.
In the region, the TFT width W is 2 μm constant, the length La = 2 μm TFT-A, and the Lb = 4 μm TFT-B are formed in a constant pattern. When the TFT characteristics were measured at each of the five points, the same characteristics were obtained for both TFT-A and TFT-B. Furthermore, in order to investigate the ratio Na / L of the average number Na of crystal grain boundaries and the gate length L across the current direction in the channel region, the poly-Si layer should be clarified for the TFT whose characteristics were measured. The marking of the position and the removal of the upper layer portion were performed, and the range of 50 μm × 50 μm was evaluated by a scanning electron microscope. As a result, the ratio Na / L of the grain boundary average Na and the gate length L across the current direction in the channel region in each of the TFT-A and TFT-B measured multiple times is a frequency within ± 5%. It was a distribution.
As a result of measuring the characteristics of a plurality of TFTs manufactured according to the present invention, TFT-A and TFT-B have the same performance (electron mobility: 250 cm 2 / V · s) even though the transistor sizes are different. I was able to.

Furthermore, in the beam profile measurement, the above-mentioned conditions
The profile required for TFT-A is Z = 30μm, laser intensity is 500mJ / cm2,
The profile required for TFT-B is Z = 20μm and the laser intensity is 700mJ / cm2,
In addition to adjusting the height d of the phase shift mask and detecting the optimum d,
For TFT-A, d = 5μm
For TFT-B, d = 1μm
Was preferred.
Under the above conditions, the TFT described above was fabricated, and the ratio Na / L of the average number Na of grain boundaries and the gate length L crossing the current direction in the channel region in each of the TFT-A and TFT-B measured multiple times The frequency distribution was within ± 2%.
As a result of measuring the characteristics of the fabricated TFTs, TFT-A and TFT-B can obtain the same performance (electron mobility: 250 cm2 / V · s) even though the transistor sizes are different. It was.

It is the schematic of the laser crystallization apparatus used for this invention. It is a schematic diagram of the electronic device produced using the manufacturing apparatus and method used for this invention. It is process sectional drawing of the electronic device produced using the manufacturing apparatus and method used for this invention. It is a schematic diagram of the laser marker provided in the active layer of TFT. It is process sectional drawing of the conventional electronic device. 3 is a graph showing the relationship between stage height Z and the number of crystal grain boundaries per 1 μm.

1 Laser light source 2 Attenuator 3 Light intensity pattern adjustment unit
31 Phase shift mask
32 Imaging optics 4 Mirror 5 Semiconductor substrate 6 Light intensity pattern measurement unit
61 Fluorescent screen
62 Mirror
63 CCD
7 Moving stage 8 PC
101 glass substrate
102 Base protective film
103 Amorphous silicon thin film
104 excimer laser
105 Arrow indicating scanning heating direction
106 polycrystalline silicon thin film
107 Gate insulation film
108 Drain impurity implantation region
109 Source impurity implantation region
110 Gate electrode
111 Protective film
112 Source electrode
113 Drain electrode
301 Insulator substrate
302 First thin film
303 second thin film
305 SiO2 film
306 poly-Si layer
309 Gate electrode
310 Drain region
311 Source area
312 Source electrode

Claims (1)

A laterally grown small grain crystal region and a semiconductor layer provided with a large grain crystal region provided directly or indirectly on the same substrate;
A TFT having a small grain crystal grown in the lateral direction as a channel region;
A TFT having a large grain crystal grown in the lateral direction as a channel region;
Comprising
The average value of the number of grain boundaries across the current direction is the same in the channel region of the small grain crystal grown in the lateral direction and the channel region of the large grain crystal grown in the lateral direction. A semiconductor device .

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