JP4438940B2 - Wiring board, semiconductor device, electronic device and electronic equipment - Google Patents

Description

  The present invention relates to a wiring board and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, an electronic device, and an electronic apparatus.

  In a semiconductor device to which the form of COF (Chip On Film) is applied, wiring is formed on the surface of the flexible substrate on which the semiconductor chip is mounted, and after the semiconductor chip is mounted, between the semiconductor chip and the flexible substrate. Inject resin (underfill material). In this case, if the resin can be injected so that bubbles do not occur between the semiconductor chip and the flexible substrate, the reliability can be improved.

An object of the present invention is to improve reliability of a wiring board and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, an electronic device, and an electronic apparatus.
JP 2003-197673 A

(1) A wiring board according to the present invention comprises:
A flexible substrate having a chip component mounting area on which chip components are mounted;
A first wiring having a first electrical connection formed inside the chip component mounting area and extending with a width of the first electrical connection;
A second wiring having a second electrical connection formed inside the chip component mounting region and extending with a width of the second electrical connection;
A first through hole penetrating the flexible substrate and electrically connected to the first wiring;
A second through hole penetrating the flexible substrate and electrically connected to the second wiring;
Third wiring formed on the surface of the flexible substrate opposite to the chip component mounting area and electrically connecting the first and second wirings via the first and second through holes. When,
including. According to the present invention, the third wiring for electrically connecting the first and second wirings is formed avoiding between the chip component and the flexible substrate. Thereby, the flow of the resin injected between the chip component and the flexible substrate can be improved, and the generation of bubbles or unfilled portions due to resin sealing can be prevented. In addition, since the third wiring is formed on the surface opposite to the chip component mounting area of the flexible substrate, it can be freely routed without being restricted by other wiring. Therefore, it is possible to prevent the occurrence of electrical defects such as a short circuit between the wirings. Therefore, the reliability of the wiring board can be improved.
(2) In this wiring board,
At least one of the first and second through holes may be formed inside the chip component mounting region.
(3) In this wiring board,
The first through hole is formed avoiding the first electrical connection portion,
The second through hole may be formed so as to avoid the second electrical connection portion. According to this, when the chip component is bonded, the bonding weight applied to the first and second electrical connection portions can be made substantially the same as the bonding weight applied to the other electrical connection portions, The bonding weight can be made uniform.
(4) In this wiring board,
At least one of the first and second through holes may be formed outside the chip component mounting region.
(5) In this wiring board,
The third wiring may be formed avoiding the chip component mounting area. According to this, since the chip component mounting area of the flexible substrate can be supported flat, it is possible to reduce the occurrence of bonding defects such as the chip component being tilted and mounted.
(6) In this wiring board,
The third wiring may be formed so as to overlap the chip component mounting region. According to this, the light-shielding property with respect to a chip component can be improved.
(7) In this wiring board,
The third wiring may have an outer shape having a size including the outer shape of the chip component mounting region. By so doing, light perpendicularly incident on the surface of the chip component can be blocked almost completely, so that the light shielding property to the chip component can be improved more effectively.
(8) In this wiring board,
The outer shape of the chip component mounting area is rectangular,
The third wiring may extend in a direction parallel to the long side of the chip component mounting area.
(9) In this wiring board,
An insulating layer provided on a surface opposite to the chip component mounting region of the flexible substrate;
The insulating layer may cover the third wiring.
(10) A semiconductor device according to the present invention includes:
The wiring board;
A semiconductor chip having a plurality of bumps as the chip component;
Including
The semiconductor chip is face-down bonded to the chip component mounting area,
The first electrical connection portion overlaps a part of the first bump among the plurality of bumps, and enters the first bump.
The second electrical connection portion overlaps and enters a part of the second bump among the plurality of bumps.
(11) An electronic device according to the present invention includes:
The semiconductor device;
An electro-optical panel to which the semiconductor device is electrically connected;
including.
(12) An electronic apparatus according to the present invention includes the semiconductor device.
(13) A method for manufacturing a wiring board according to the present invention includes:
The first wiring is provided on the flexible substrate having the chip component mounting area on which the chip component is mounted, and the first electrical connection portion is provided on the inner side of the chip component mounting area. Forming to extend with the width of the connection part,
Forming the second wiring so as to have a second electrical connection formed inside the chip component mounting region and to extend with a width of the second electrical connection portion;
Forming a first through hole for electrically connecting to the first wiring by providing a conductive material in a through hole formed in the flexible substrate;
Forming a second through hole for electrically connecting to the second wiring by providing a conductive material in a through hole formed in the flexible substrate;
A third wiring for electrically connecting the first and second wirings is formed on the surface of the flexible substrate opposite to the chip component mounting through the first and second through holes. thing,
including. According to the present invention, the third wiring for electrically connecting the first and second wirings is formed while avoiding the space between the chip component and the flexible substrate. Thereby, the flow of the resin injected between the chip component and the flexible substrate can be improved, and the generation of bubbles or unfilled portions due to resin sealing can be prevented. In addition, since the third wiring is formed on the surface opposite to the chip component mounting area of the flexible substrate, it can be freely routed without being restricted by other wiring. Therefore, it is possible to prevent the occurrence of electrical defects such as a short circuit between wirings. Therefore, the reliability of the manufacturing method of the wiring board can be improved.
(14) A method for manufacturing a semiconductor device according to the present invention includes:
Manufacturing a wiring board by the above method, including face down bonding a semiconductor chip including a plurality of bumps to the chip component mounting region;
In the face down bonding process,
The first electrical connection portion is overlapped with a part of the first bump among the plurality of bumps, and enters the first bump,
The second electrical connection portion is overlapped with a part of the second bump among the plurality of bumps, and enters the second bump.
(15) In this method of manufacturing a semiconductor device,
The method may further include injecting a resin between the semiconductor chip and the flexible substrate after the semiconductor chip is face-down bonded.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  1 to 4 are diagrams showing a wiring board or a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1 is a plan view of a wiring board, FIG. 2 is a partially enlarged view of FIG. 1, FIG. 3 is a sectional view taken along line III-III in FIG. 2, and FIG. It is line sectional drawing. 3 and 4 show a semiconductor device including a semiconductor chip.

  The wiring board according to the present embodiment includes a flexible substrate 10 and a wiring pattern formed on the flexible substrate 10. The wiring pattern is formed in the wiring pattern formation region 3 of the wiring substrate 1. The wiring board 1 may be a long tape, and a plurality of wiring pattern formation regions 3 may be arranged in the length direction of the wiring board 1. Adjacent wiring pattern formation regions 3 may be spaced apart. The wiring board 1 is punched along the outer shape of the wiring pattern formation region 3 in a subsequent process. The wiring board according to the present embodiment includes a wiring pattern formation region 3 after punching.

  The flexible substrate 10 is a base substrate that can be bent. The flexible substrate 10 may be made of an organic material such as a resin substrate (for example, a polyimide substrate). The flexible substrate 10 may be a COF (Chip On Film) substrate, or may be a film or a tape. The flexible substrate 10 has a chip component mounting area 12 on which chip components are mounted. The chip component may be a semiconductor component such as a semiconductor chip 50 (see FIG. 3), an active component (such as an integrated circuit component), or a passive component (such as a resistor, capacitor, or inductor). . The chip component mounting area 12 is provided on one surface of the flexible substrate 10 and is provided within the range of the wiring pattern forming area 3. The outer shape of the chip component mounting area 12 is the same as the planar shape of the chip component, and may be, for example, a quadrilateral (for example, a square or a rectangle). In the example shown in FIGS. 1 and 2, the outer shape of the chip component mounting region 12 is a rectangle having first and second long sides 14 and 16 facing each other.

  The wiring pattern is formed of a conductive material (for example, a metal such as Cu). In the wiring pattern forming region 3, one or more electrically independent wiring patterns are formed. The wiring pattern can be formed by applying electroplating, electroless plating, sputtering, etching, or the like.

  As shown in FIGS. 2 to 4, the wiring pattern includes a plurality of wirings 20. The plurality of wirings 20 may be formed on the surface of the chip component mounting region 12 of the flexible substrate 10. The cross-sectional shape of the wiring 20 may be a shape in which the upper end portion is recessed from the lower end portion (for example, a trapezoid whose upper side is smaller than the lower side) (see FIG. 4). The wiring 20 is intended for electrical connection between at least two points.

  One electrical connection portion of the wiring 20 may be an electrical connection portion 22 for a chip component. The electrical connection portion 22 is formed inside the chip component mounting area 12. The electrical connection portion 22 is a portion that is electrically connected to the chip component (for example, the semiconductor chip 50), and more specifically, is a portion that overlaps with the electrical connection portion (for example, the bump 54) of the chip component. The electrical connection portion 22 may be an end portion of the wiring 20 or may be a portion avoiding the end portion of the wiring 20. The wiring 20 extends with the width of the electrical connection portion 22. The electrical connection portion 22 is not in a land shape. For example, the wiring 20 may have an extending portion that extends from the electrical connection portion 22 with the same width. The extending part may be a part protruding from the range of the electrical connection part of the chip part (for example, the bump 54 of the semiconductor chip 50). The other electrical connection portion of the wiring 20 may be for another electronic component (for example, an electro-optical panel) or may be for a circuit board (for example, a motherboard).

  In the example shown in FIG. 2, the plurality of wirings 20 are formed by arranging a plurality of wirings 20 along the first long side 14, and a plurality of wirings 20 arranged along the second long side 16. And a second group 42. The plurality of wirings 20 belonging to the first group 40 may be output terminals from chip components. The plurality of wirings 20 belonging to the first group 40 extend in a direction of the first long side 14 from the electrical connection portion 22 that is a part of the wiring 20 so as to intersect the first long side 14 (for example, orthogonally). Has been. The plurality of wirings 20 belonging to the second group 42 may be input terminals from chip components. The plurality of wirings 20 belonging to the second group 42 extend in the direction of the second long side 16 from the electrical connection portion 22 that is a part of the wiring 20 so as to intersect (for example, orthogonally intersect) the second long side 16. Has been. Among the plurality of wirings 20 belonging to the first group 40 (or the second group 42), the plurality of electrical connection portions 22 may be arranged in one row, or the adjacent ones are staggered. It may be arranged in a shifted manner. By arranging in a staggered manner, the pitch of the adjacent electrical connection portions 22 can be increased even within a limited plane region.

  The plurality of wirings 20 include first to third wirings 24, 30 and 36. The first to third wirings 24, 30, and 36 belong to one of the first and second groups 40 and 42 (second group 42 serving as an input terminal in FIG. 2), and each is electrically connected to each other. It is connected to the. The first to third wirings 24, 30, and 36 have a common potential (for example, a ground potential or a power supply potential). The plurality of wirings 20 include first and second through holes 28 and 34. In the present embodiment, the first to third wirings 24, 30 and 36 are electrically connected by the first and second through holes 28 and 34.

  The first wiring 24 has a first electrical connection portion 26, and extends with the width of the first electrical connection portion 26. The second wiring 30 has a second electrical connection portion 32, and extends with the width of the second electrical connection portion 32. The details thereof are as described for the wiring 20 described above. In the region between the first wiring 24 and the second wiring 30, at least one other wiring 20 may be arranged. Alternatively, the first and second wirings 24 and 30 may be adjacent to each other.

  The first through hole 28 is electrically connected to the first wiring 24. The first through hole 28 is formed through the flexible substrate 10. The first through hole 28 may be formed by forming a through hole in a direction perpendicular to the surface of the flexible substrate 10 and providing a conductive material in the through hole. The through hole can be formed by punching the flexible substrate 10. The entire through hole may be filled with a conductive material, or the conductive material may be provided only on the inner wall surface avoiding the central axis of the through hole. As a method for forming the conductive material, sputtering, plating (electroless plating), or application of a paste material may be applied. The planar shape (transverse cross-sectional shape) of the first through hole 28 may be circular. The width (for example, diameter) of the first through hole 28 may be larger than the width of the wiring 20, may be smaller, or may be the same. Further, the width (for example, the diameter) of the first through hole 28 may be larger, smaller, or the same as the width of the electrical connection portion (for example, the bump 54) of the chip component. Good. The boundary between the first through hole 28 and the first wiring 24 is not necessarily clear. The second through hole 34 is electrically connected to the second wiring 30. The details of the first through hole 28 can be applied to the details of the second through hole 34.

  The third wiring 36 is electrically connected to the first wiring 24 through the first through hole 28 and electrically connected to the second wiring 30 through the second through hole 34. ing. The boundary between the third wiring 36 and the first through hole 28 (or the second through hole 34) is not necessarily clear. The third wiring 36 is routed so as to connect two points of the first through hole 28 and the second through hole 34 in the plan view of the flexible substrate 10. The third wiring 36 is formed on the surface of the flexible substrate 10 opposite to the chip component mounting area 12.

  As shown in FIG. 2, the third wiring 36 may extend in a direction parallel to the long side (for example, the first or second long side 14, 16) of the chip component mounting region 12. The third wiring 36 may extend in a direction parallel to the direction intersecting with the plurality of other wirings 20. The third wiring 36 may extend in a straight line, or may have a bent portion. The third wiring 36 may be elongated in a so-called line shape. With the third wiring 36, one or more first wirings 24 (first electrical connection portions 26) and one or more second wirings 30 (second electrical connection portions 32) , Are electrically connected.

  At least one of the first and second through holes 28 and 34 (both in FIG. 2) may be formed inside the chip component mounting region 12. The first through hole 28 (or the second through hole 34) may be formed avoiding the first electrical connection portion 26 (or the second electrical connection portion 32). For example, the first through hole 28 (or the second through hole 34) is disposed inside the chip component mounting region 12 rather than the first electrical connection portion 26 (or the second electrical connection portion 32). May be. According to this, when the chip component is bonded, the bonding weight applied to the first and second electrical connection portions 26 and 32 is substantially the same as the bonding weight applied to the other electrical connection portions 22. Therefore, the bonding weight can be made uniform. Alternatively, the first through hole 28 (or the second through hole 34) may be formed so as to overlap the first electrical connection portion 26 (or the second electrical connection portion 32).

  The third wiring 36 may overlap the chip component mounting area 12. When both the first and second through holes 28 and 34 are formed inside the chip component mounting area 12, the entire third wiring 36 overlaps the chip component mounting area 12. Alternatively, when one of the first and second through holes 28 and 34 is formed inside the chip component mounting region 12 and the other is formed outside thereof, a part of the third wiring 36 is a chip. It overlaps with the component mounting area 12.

  According to the present embodiment, the third wiring 36 for electrically connecting the first and second wirings 24 and 30 while avoiding the space between the chip component (for example, the semiconductor chip 50) and the flexible substrate 10. Is formed. Thereby, the flow of the resin injected between the chip component and the flexible substrate 10 can be improved, and the generation of bubbles or unfilled portions due to resin sealing can be prevented. Further, since the third wiring 36 is formed on the surface opposite to the chip component mounting area 12 of the flexible substrate 10, it can be freely routed without being restricted by the other wiring 20. Therefore, it is possible to prevent the occurrence of electrical defects such as a short circuit between the wirings. Therefore, the reliability of the wiring board can be improved. Further, if the third wiring 36 overlaps the chip component mounting area 12, the wiring pattern forming area is not enlarged. In addition, the light shielding property to the chip component is improved.

  The wiring board according to the present embodiment may further include insulating layers 60 and 62 that cover a part of the wiring pattern, as shown in FIG. The insulating layers 60 and 62 are provided to avoid the chip component mounting region 12 of the flexible substrate 10. The insulating layer 60 is provided on the surface of the chip component mounting region 12 of the flexible substrate 10 and covers a part of the wiring 20. The insulating layer 60 is provided around the chip component mounting region 12 with a certain distance therebetween. The insulating layer 62 is provided on the surface of the flexible substrate 10 opposite to the chip component mounting area 12 and covers the third wiring 36. If the first through hole 28 (or the second through hole 34) is exposed, the insulating layer 62 also covers the exposed portion. When the insulating layer 62 overlaps the chip component mounting region 12, the light shielding property for the chip component may be enhanced by the insulating layer 62.

  The wiring board according to the present embodiment is configured as described above. Next, a method for manufacturing the wiring board will be described. In the method for manufacturing a wiring board according to the present embodiment, a wiring pattern (including first to third wirings 24, 30, 36, and first and second through holes 28, 34) is formed on the flexible substrate 10. Including doing. The first to third wirings 24, 30, and 36 can be patterned by etching a metal foil. For example, a metal foil may be formed on the surface of the chip component mounting region 12 of the flexible substrate 10, and the metal foil may be etched and patterned into the shapes of the first to third wirings 24, 30, and 36. Each surface of the flexible substrate 10 may be patterned in order, or both surfaces may be patterned simultaneously. The first and second through holes 28 and 34 may be performed after patterning both surfaces of the flexible substrate 10 or after patterning one of the surfaces and before patterning the other surface. Alternatively, it may be performed before patterning any surface. When the first through hole 28 (or the second through hole 34) is formed so as to overlap the first electrical connection portion 26 (or the second electrical connection portion 32), the first After the formation process of the through hole 28 (or the second through hole 34), the formation process of the first wiring 24 (or the second wiring 30) is performed. The other details about the manufacturing method of a wiring board can be derived from the contents described above.

  The semiconductor device according to the present embodiment includes the above-described wiring board and a semiconductor chip 50 as a chip component. An integrated circuit is formed on the semiconductor chip 50. The semiconductor chip 50 includes a pad (for example, an aluminum pad) 52 and a bump (for example, a gold bump) 54 on the pad 52. The arrangement of the plurality of pads 52 (or bumps 54) corresponds to the arrangement of the electrical connection portions (including the first and second electrical connection portions 26 and 32) 22 of the wiring board described above. The bump 54 is an electrical connection portion of the semiconductor chip 50. The semiconductor chip 50 is provided with a passivation film 56 so as to avoid the central portion of the pad 52 (a region where the bump 54 is formed).

  The semiconductor chip 50 is face-down bonded to the chip component mounting area 12 of the flexible substrate 10. The plurality of electrical connection portions 22 are electrically connected to the plurality of bumps 54 of the semiconductor chip 50. Specifically, the first electrical connection portion 26 overlaps a part of the first bumps of the plurality of bumps 54 (see FIG. 2) and enters the first bumps (FIG. 4). reference). The second electrical connection portion 32 overlaps a part of the second bumps of the plurality of bumps 54 (see FIG. 2) and enters the second bump (see FIG. 4). Only the upper end portion of the electrical connection portion 22 may enter the bump 54.

  A sealing material (underfill material) 58 such as a resin may be provided between the semiconductor chip 50 and the flexible substrate 10. In the present embodiment, since the third wiring 36 is formed so as to avoid the space between the semiconductor chip 50 and the flexible substrate 10, it is difficult for the resin flow to be blocked. That is, the flow of the resin injected between the semiconductor chip 50 and the flexible substrate 10 can be improved, and the generation of bubbles or unfilled portions due to resin sealing can be prevented.

  Since the semiconductor device according to the present embodiment includes the above-described wiring board, the reliability of the semiconductor device can be improved. The semiconductor device manufacturing method according to the present embodiment includes face-down bonding of the semiconductor chip 50 to the chip component mounting region 12. The sealing material 58 may be formed by injecting a resin between the semiconductor chip 50 and the flexible substrate 10. In the present embodiment, even when a method of injecting resin between the semiconductor chips 50 mounted on the flexible substrate 10 is applied, the generation of bubbles or unfilled portions due to resin sealing is prevented. Thus, the reliability of the sealing process can be improved. A plurality of semiconductor devices can be manufactured by mounting a plurality of semiconductor chips 50 on the wiring substrate 1 shown in FIG.

  FIG. 5 is a diagram showing a semiconductor device (including a wiring board) according to a modification of the present embodiment. The third wiring 70 has a shape that expands two-dimensionally, and has an outer shape that includes, for example, the outer shape of the chip component mounting region 12. That is, in the plan view of the flexible substrate 10, the outer shape of the third wiring 70 is larger than the outer shape of the chip component (for example, the semiconductor chip 50). In this way, light that is perpendicularly incident on the surface of the chip component (for example, the integrated circuit formation surface) can be blocked almost completely, so that the light shielding property to the chip component can be improved more effectively. it can. In addition, since the planar area of the third wiring 70 is large, the ground potential or the power supply potential is stable, and electrical reliability can be improved. Note that the third wiring 70 is covered with an insulating layer 72.

  FIG. 6 is a diagram showing a wiring board according to a modification of the present embodiment. At least one (both in FIG. 6) of the first and second through holes 80 and 82 may be formed outside the chip component mounting region 12. The third wiring 84 is formed so as to avoid the chip component mounting area 12. That is, the third wiring 84 is formed so as not to overlap the chip component mounting region 12. According to this, since the chip component mounting region 12 of the flexible substrate 10 can be supported flatly, it is possible to reduce the occurrence of bonding failure such as the chip component being tilted and mounted.

  FIG. 7 is a diagram showing an electronic device according to an embodiment of the present invention. This electronic device includes the above-described semiconductor device and an electro-optical panel 110 to which the semiconductor device is electrically connected. In the semiconductor device, a semiconductor chip (drive IC) 50 is mounted on a flexible substrate 10. The electronic device may be a display device that converts an electrical information signal into an optical information signal that can be visually recognized. The electro-optical panel 110 may be a display panel. Examples of the electro-optical panel 110 include a liquid crystal panel, a plasma display panel, and an electroluminescence display panel.

  As an electronic apparatus according to an embodiment of the present invention, a notebook personal computer 1000 is shown in FIG. 8, and a mobile phone 2000 is shown in FIG. These electronic devices include any of the above-described wiring boards, semiconductor devices, and electronic devices.

  The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

FIG. 1 is a plan view of a wiring board according to an embodiment of the present invention. FIG. 2 is a partially enlarged view of FIG. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. FIG. 5 is a diagram showing a modification of the embodiment of the present invention. FIG. 6 is a diagram showing a modification of the embodiment of the present invention. FIG. 7 is a diagram showing an electronic device according to an embodiment of the present invention. FIG. 8 is a diagram showing an electronic apparatus according to an embodiment of the present invention. FIG. 9 is a diagram showing an electronic apparatus according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Wiring board 3 ... Wiring pattern formation area 10 ... Flexible board 12 ... Chip component mounting area 14 ... 1st long side 16 ... 2nd long side 20 ... Wiring 22 ... Electrical connection part 24 ... 1st wiring 26 ... 1st electrical connection part 28 ... 1st through-hole 30 ... 2nd wiring 32 ... 2nd electrical connection part 34 ... 2nd through-hole 36 ... 3rd wiring 40 ... 1st group 42 ... second group 50 ... semiconductor chip 52 ... pad 54 ... bump 56 ... passivation film 58 ... sealing material 60 ... insulating layer 62 ... insulating layer 70 ... third wiring 72 ... insulating layer 84 ... third wiring 110 ... Electro-optic panel

Claims (11)

A flexible substrate having a chip component mounting area on which chip components are mounted;
A first wiring having a first electrical connection formed inside the chip component mounting area and extending with a width of the first electrical connection;
A second wiring having a second electrical connection formed inside the chip component mounting region and extending with a width of the second electrical connection;
A first through hole penetrating the flexible substrate and electrically connected to the first wiring;
A second through hole penetrating the flexible substrate and electrically connected to the second wiring;
Third wiring formed on the surface of the flexible substrate opposite to the chip component mounting area and electrically connecting the first and second wirings via the first and second through holes. When,
Only including,
At least one of the first and second through holes is a wiring board formed outside the chip component mounting region . A flexible substrate having a chip component mounting area on which chip components are mounted;
A first wiring having a first electrical connection formed inside the chip component mounting area and extending with a width of the first electrical connection;
A second wiring having a second electrical connection formed inside the chip component mounting region and extending with a width of the second electrical connection;
A first through hole penetrating the flexible substrate and electrically connected to the first wiring;
A second through hole penetrating the flexible substrate and electrically connected to the second wiring;
Third wiring formed on the surface of the flexible substrate opposite to the chip component mounting area and electrically connecting the first and second wirings via the first and second through holes. When,
Only including,
The outer shape of the chip component mounting area is rectangular,
The third wiring is a wiring board extending in a direction parallel to the long side of the chip component mounting area . The wiring board according to claim 2 ,
At least one of the first and second through holes is a wiring board formed inside the chip component mounting region. In the wiring board according to claim 2 or 3 ,
The first through hole is formed avoiding the first electrical connection portion,
The wiring board, wherein the second through hole is formed avoiding the second electrical connection portion. In the wiring board according to any one of claims 1 to 4 ,
The third wiring is a wiring board formed so as to avoid the chip component mounting area. The wiring board according to any one of claims 1 to 5 ,
The wiring board is formed by overlapping the third wiring with the chip component mounting region. The wiring board according to claim 6 ,
The third wiring is a wiring board having an outer shape having a size including an outer shape of the chip component mounting region. The wiring board according to any one of claims 1 to 7 ,
An insulating layer provided on a surface opposite to the chip component mounting region of the flexible substrate;
The insulating layer is a wiring board that covers the third wiring. A wiring board according to any one of claims 1 to 8 ,
A semiconductor chip having a plurality of bumps as the chip component;
Including
The semiconductor chip is face-down bonded to the chip component mounting area,
The first electrical connection portion overlaps a part of the first bump among the plurality of bumps, and enters the first bump.
The second electrical connection portion is a semiconductor device which overlaps with and enters a part of the second bump among the plurality of bumps. A semiconductor device according to claim 9 ;
An electro-optical panel to which the semiconductor device is electrically connected;
Including electronic devices. An electronic apparatus having the semiconductor device according to claim 9 .

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