JP2006245187A - Process for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for manufacturing a highly reliable semiconductor device efficiently. <P>SOLUTION: The process for manufacturing a semiconductor device comprises a step for preparing a semiconductor module 100 having a wiring board 10 including a wiring pattern 14 and a resist layer 20 provided with an opening 22 for exposing a part of the wiring pattern 14, and a semiconductor chip 40 mounted on the wiring board 10 such that an electrode 42 opposes the wiring pattern 14, and a step for forming a resin portion 52 between the wiring board 10 and the semiconductor chip 40 by filling the space between the wiring board 10 and the semiconductor chip 40 with resin paste 50 and hardening the resin paste 50. The resist layer 20 has at least one hole 30 arranged on the side of a region overlapping the semiconductor chip 40. In the step for filling the space with the resin paste 50, the resin paste 50 is fluidized to cover at least a part of the hole 30. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  A semiconductor device in which a semiconductor chip is mounted on a wiring board is known. It is known to form a resin portion between the wiring board and the semiconductor chip. The resin part serves to increase the mechanical strength of the semiconductor device by bonding the wiring substrate and the semiconductor chip, and also serves to seal the wiring and the chip electrode to prevent their deterioration. . In order to manufacture a highly reliable semiconductor device, it is important to form the resin portion so as not to have bubbles inside.

An object of the present invention is to provide a method for manufacturing a highly reliable semiconductor device.
JP-A-11-111894

(1) A method of manufacturing a semiconductor device according to the present invention includes a wiring substrate including a wiring pattern, a resist layer in which an opening exposing a part of the wiring pattern is formed, and an electrode. Preparing a semiconductor module having a semiconductor chip mounted on the wiring board so as to face the wiring pattern; and
Filling a resin paste between the wiring substrate and the semiconductor chip, curing the resin paste, and forming a resin portion between the wiring substrate and the semiconductor chip;
The resist layer has at least one hole disposed on a side of a region overlapping with the semiconductor chip,
In the step of filling the resin paste, the resin paste is caused to flow so as to cover at least a part of the hole. According to the present invention, the flow rate of the resin paste traveling along the outer periphery of the semiconductor chip can be reduced. Therefore, it is possible to prevent the resin paste from enclosing the outer periphery of the semiconductor chip before the resin paste is filled in the semiconductor chip central region. Therefore, the resin paste can be filled so that no voids remain between the wiring board and the semiconductor chip. Accordingly, since the resin portion can be formed so as not to have voids therein, a highly reliable semiconductor device can be manufactured.
(2) In this method of manufacturing a semiconductor device,
The hole may be arranged on each side of a pair of opposite sides of the semiconductor chip facing each other.
(3) In this method of manufacturing a semiconductor device,
The resin paste may be supplied from between a side other than the opposite side and the wiring board.
(4) In this method of manufacturing a semiconductor device,
The holes may be arranged on the sides of all sides of the semiconductor chip.
(5) In this method of manufacturing a semiconductor device,
The resin paste may be supplied from the hole toward the center of the semiconductor chip. According to this, the resin paste can be filled from the central region of the semiconductor chip. Therefore, the resin paste can be filled between the wiring board and the semiconductor chip so that no voids remain.
(6) In this method of manufacturing a semiconductor device,
You may supply the said paste so that it may not contact the part which overlaps with the said hole in the outer periphery of the said semiconductor chip.
(7) In this method of manufacturing a semiconductor device,
The hole may be formed so as to reach a region overlapping with the semiconductor chip.
(8) In this method of manufacturing a semiconductor device,
The hole may be formed only outside the region overlapping with the semiconductor chip.
(9) In this method of manufacturing a semiconductor device,
The hole may be communicated with the opening.
(10) In this method of manufacturing a semiconductor device,
The hole may not be communicated with the opening.
(11) In this method of manufacturing a semiconductor device,
The hole may be formed so as to penetrate the resist layer.
(12) In this method of manufacturing a semiconductor device,
The hole may be formed so as not to penetrate the resist layer.
(13) In this method of manufacturing a semiconductor device,
The wiring board may further include a second resist layer disposed in a central region of the opening of the resist layer. According to this, the flow rate of the resin paste traveling through the central region of the semiconductor chip can be increased. Therefore, the resin paste can be filled between the wiring board and the semiconductor chip so that no void remains inside.
(14) In this method of manufacturing a semiconductor device,
The surface of the second resist layer may be a flat surface.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. However, the present invention is not limited to the following embodiments. Further, the present invention may be freely combined with the embodiments and modifications described below.

(First embodiment)
FIG. 1A to FIG. 4B are diagrams for explaining a semiconductor device manufacturing method according to the first embodiment to which the present invention is applied.

  The method for manufacturing a semiconductor device according to the present embodiment includes preparing the semiconductor module 100. Although the method for forming the semiconductor module 100 is not particularly limited, a method for forming the semiconductor module 100 will be described below with reference to FIGS. 1 (A) to 2 (B).

  The method for forming the semiconductor module 100 may include preparing the wiring board 10 shown in FIGS. 1 (A) and 1 (B). FIG. 1A is a top view of the wiring board 10, but for the sake of explanation, a region 41 for mounting the semiconductor chip 40 is indicated by a one-dot chain line. FIG. 1B is a partially enlarged view of a cross section taken along line IB-IB in FIG. The wiring substrate 10 includes a base substrate 12 (see FIG. 1B). The material and structure of the base substrate 12 are not particularly limited, and any known substrate may be used. The base substrate 12 may be a flexible substrate or a rigid substrate. The base substrate 12 may be a laminated substrate or a single layer substrate. The base substrate 12 may be composed of any organic or inorganic material, or may be composed of a composite structure thereof. As the base substrate 12, for example, a substrate or a film made of polyethylene terephthalate (PET) may be used. Alternatively, a flexible substrate made of a polyimide resin may be used as the base substrate 12. As the flexible substrate, a tape used in FPC (Flexible Printed Circuit) or TAB (Tape Automated Bonding) technology may be used. Examples of the base substrate 12 formed from an inorganic material include a ceramic substrate and a glass substrate. An example of a composite structure of organic and inorganic materials is a glass epoxy substrate. The external shape of the base substrate 12 is not particularly limited.

  As shown in FIGS. 1A and 1B, the wiring board 10 has a wiring pattern 14. The wiring pattern 14 is provided on the base substrate 12. One wiring pattern 14 may be provided on one base substrate 12, or a plurality of wiring patterns 14 may be provided. The wiring pattern 14 may have an electrical connection portion 15. The electrical connection portion 15 is a portion used for electrical connection with an electrode of an electronic component (for example, an electrode 42 of a semiconductor chip 40 described later). The structure and material of the wiring pattern 14 are not particularly limited. For example, the wiring pattern 14 may have a configuration in which any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti-W) is laminated. The wiring pattern 14 may have a plurality of portions having different configurations. For example, in a region covered with a resist layer 20 described later, the wiring pattern 14 may be formed of copper. The wiring pattern 14 may have a structure in which a base wiring formed of copper is plated with gold in a region exposed from the resist layer 20 (for example, the electrical connection portion 15). The wiring pattern 14 may be provided only on the surface of the base substrate 12, or may be provided so as to pass through the inside of the base substrate 12 (not shown). In addition, the electrical connection portion 15 may be provided on both surfaces of the base substrate 12. The region where the wiring pattern 14 is formed is not particularly limited. For example, the wiring pattern 14 may be routed to a range including the central region of the region 41 for mounting the semiconductor chip 40 (the central region of the opening 22 of the resist layer 20) (not shown). At this time, an electrical connection portion (not shown) may be provided in the central region of the opening 22.

  The wiring substrate 10 includes a resist layer 20. The resist layer 20 may be formed so as to partially cover the wiring pattern 14. The resist layer 20 is formed with an opening 22 for exposing a part of the wiring pattern 14. The opening 22 may be formed so as to expose the electrical connection portion 15 of the wiring pattern 14. The opening 22 may be formed inside the region 41 for mounting the semiconductor chip 40. That is, the opening 22 may be formed so as not to be exposed from the semiconductor chip 40 described later. However, the positional relationship between the opening 22 and the semiconductor chip 40 (region 41) is not limited to this. For example, an opening larger than the semiconductor chip 40 (region 41) may be formed in the resist layer 20 (not shown). Further, the planar shape of the opening 22 is not particularly limited. The planar shape of the opening 22 may be a rectangle (a square or a rectangle). For example, the planar shape of the opening 22 may be (substantially) the same shape as the semiconductor chip 40. The material of the resist layer 20 is not particularly limited, and any known material may be applied.

  The wiring board 10 may have a second resist layer (not shown). The second resist layer may be disposed in the central region of the opening 22. The second resist layer may be formed so that the surface is a flat surface. The second resist layer may be formed of the same material as the resist layer 20. When the wiring pattern 14 has an electrical connection portion arranged in the central region of the opening 22, the second resist layer may have an opening that exposes the electrical connection portion. However, the wiring board 10 may not have the second resist layer. In this case, the wiring pattern 14 may be exposed in a region inside the opening 22.

  In the wiring substrate 10, the resist layer 20 has holes 30 as shown in FIGS. 1 (A) and 1 (B). The hole 30 is arranged on the side of the region 41 for mounting the semiconductor chip 40. The hole 30 may be a recess that does not penetrate the resist layer 20 (see FIG. 1B). Alternatively, the hole 30 may be a through hole penetrating the resist layer 20 (not shown). The hole 30 may be formed only in a region outside the region 41. In other words, the hole 30 may be formed so as not to overlap the region 41. At this time, the hole 30 may be formed so as not to communicate with the opening 22 (away from the opening 22). However, the arrangement of the holes 30 is not limited to this, and the holes 30 may be formed so as to reach the inside of the region 41. At this time, the hole 30 may be communicated with the opening 22. The hole 30 may be arranged on each side of the pair of opposite sides 43 facing each other in the region 41 (see FIG. 1A). At this time, the hole 30 may be arranged at the center of the side 43, but may be arranged at a position shifted from the center of the side 43. Or the hole 30 may be arrange | positioned at each side of all the sides of the area | region 41 (not shown). Only one hole 30 may be arranged on the side of one side of the region 41, or a plurality of holes 30 may be arranged (not shown). The planar shape of the hole 30 is not particularly limited. The hole 30 may extend in a groove shape. At this time, the width of the hole 30 may be wider than the wiring pitch of the wiring pattern 14. That is, the hole 30 may be arranged so as to extend over a plurality of wirings. Alternatively, the hole 30 may have the same width as the side of the opening 22.

  The method for manufacturing the semiconductor module 100 may include mounting the semiconductor chip 40 having the electrodes 42 on the wiring substrate 10 as shown in FIGS. 2 (A) and 2 (B). 2A is a top view of the semiconductor chip 40 mounted on the wiring board 10 (semiconductor module 100). FIG. 2B is an enlarged view of a section taken along the line IIB-IIB in FIG. As shown in FIG. 2B, the semiconductor chip 40 is mounted on the wiring board 10 so that the electrode 42 faces the wiring pattern 14. The electrode 42 and the electrical connection portion 15 may be brought into contact and electrically connected. At this time, the electrode 42 and the electrical connection portion 15 may be bonded to a eutectic alloy. When the electrical connection portions 15 of the wiring pattern 14 are formed on both surfaces of the base substrate 12, semiconductor chips may be mounted on both surfaces of the base substrate 12 (not shown). The semiconductor chip 40 may be a silicon chip, for example. The semiconductor chip 40 may include an integrated circuit 46 (see FIG. 2B). The configuration of the integrated circuit 46 is not particularly limited. For example, the integrated circuit 46 may include an active element such as a transistor and a passive element such as a resistor, a coil, and a capacitor. At this time, the electrode 42 may be electrically connected to the integrated circuit 46. The configuration of the electrode 42 is not particularly limited. For example, the pad and the bump provided on the pad may be collectively referred to as the electrode 42. The arrangement of the electrode 42 is not particularly limited. For example, the electrodes 42 may be arranged along each side of the semiconductor chip 40. Alternatively, the electrode 42 may be disposed along each of a pair of opposing sides of the semiconductor chip 40 that face each other. Alternatively, the electrodes 42 may be arranged in an area array. The electrode 42 may be disposed in a region overlapping with a region where the integrated circuit 46 is formed. The semiconductor chip 40 is mounted on the region 41. Therefore, the positional relationship between the outer shape of the semiconductor chip 40 and the hole 30 matches the positional relationship between the region 41 and the hole 30 described above. The planar shape of the semiconductor chip 40 is not particularly limited. For example, the semiconductor chip 40 may be square, but may be rectangular.

  The semiconductor module 100 may be formed by the above process. The semiconductor module 100 includes a wiring board 10 and a semiconductor chip 40 mounted on the wiring board 10. The wiring board 10 includes a wiring pattern 14 and a resist layer 20 in which an opening 22 exposing a part of the wiring pattern 14 is formed. The resist layer 20 has at least one hole 30 disposed on a side of a region overlapping with the semiconductor chip 40. As shown in FIG. 2A, the holes 30 may be arranged on the sides of a pair of opposite sides 43 of the semiconductor chip 40 facing each other.

  As shown in FIGS. 3A to 4B, the semiconductor device manufacturing method according to the present embodiment is filled with a resin paste 50 between the wiring substrate 10 and the semiconductor chip 40, and then the resin paste. 50 is cured to form a resin portion 52 between the wiring board 10 and the semiconductor chip 40. Thereby, the semiconductor device 1 may be manufactured (see FIG. 4B). 3A to 3D are views showing a state in which the resin paste 50 flows between the wiring board 10 and the semiconductor chip 40. FIG. However, for the sake of explanation, only the outer shape of the semiconductor chip 40 is shown as the region 41. FIG. 4A is a partially enlarged view of a cross section taken along line IVA-IVA of FIG. FIG. 4B is a diagram illustrating the semiconductor device 1 after the resin paste 50 is cured. In the semiconductor device manufacturing method according to the present embodiment, the resin paste 50 is caused to flow so as to cover at least a part of the hole 30.

  Normally, when the resin paste 50 is supplied between the wiring substrate 10 and the semiconductor chip 40, the resin paste 50 flows between the wiring substrate 10 and the semiconductor chip 40 by capillary action. Thereby, the resin paste 50 is filled between the wiring substrate 10 and the semiconductor chip 40. Thereafter, the resin portion 52 is formed by curing the resin paste 50. However, in order to manufacture a highly reliable semiconductor device, it is important to form the resin portion 52 so as not to have bubbles inside. It is. For that purpose, it is important to fill the resin paste 50 so as not to have bubbles inside.

  However, if the resin paste 50 is caused to flow between the wiring substrate 10 and the semiconductor chip 40, the resin paste 50 is removed from the outer periphery of the semiconductor chip 40 before the resin paste 50 is filled between the wiring substrate 10 and the semiconductor chip 40. Was sometimes surrounded. For example, in the central region of the semiconductor chip 40, the flow rate of the resin paste may be slow due to the unevenness of the electrodes of the semiconductor chip and the wiring pattern (see FIG. 3A). As a result, the flow rate of the resin paste traveling along the outer periphery of the semiconductor chip 40 becomes faster than the flow rate of the resin paste traveling through the central region of the semiconductor chip 40, and the resin paste 50 surrounds the outer periphery of the semiconductor chip 40. was there. If the resin paste 50 surrounds the outer periphery of the semiconductor chip 40, then the fluidity of the resin paste 50 that travels through the central portion of the semiconductor chip 40 decreases, and it may be difficult to fill the resin paste 50. Further, since the resin paste 50 surrounds the outer periphery of the semiconductor chip 40, it is difficult for air to escape from between the wiring substrate 10 and the semiconductor chip 40, and a void residue may occur. If the occurrence of these phenomena can be avoided, the resin paste 50 can be filled between the wiring substrate 10 and the semiconductor chip 40 so that no voids remain, and a highly reliable semiconductor device is manufactured. Can do.

  In the method of manufacturing a semiconductor device according to the present embodiment, the resist layer 20 has the holes 30 as described above. The hole 30 is disposed on the side of the semiconductor chip 40. Then, the resin paste 50 is caused to flow so as to cover at least a part of the hole 30. According to this, the flow rate of the resin paste traveling along the outer periphery of the semiconductor chip 40 can be reduced. Specifically, since the hole 30 is disposed on the side of the semiconductor chip 40, the resin paste 50 that travels along the outer periphery of the semiconductor chip 40 flows into the hole 30 (see FIG. 3B), and one of the holes 30. Cover the part. As a result, the flow direction of the resin paste 50 is changed, so that the flow rate of the resin paste traveling along the outer periphery of the semiconductor chip 40 is reduced. In other words, by causing the resin paste 50 to flow so as to cover part of the hole 30 (so as to flow into the hole 30), the flow of the resin paste traveling along the outer periphery (side 43) of the semiconductor chip 40 is inhibited. Can do. Therefore, the time required for the resin paste 50 to surround the outer periphery of the semiconductor chip 40 can be lengthened. Thereby, the resin paste 50 can be filled in the central region of the semiconductor chip 40 before enclosing the outer periphery of the semiconductor chip 40 (see FIGS. 3C and 3D). That is, the resin paste 50 can be filled from the inside of the semiconductor chip 40. Therefore, the resin paste 50 can be filled between the wiring substrate 10 and the semiconductor chip 40 so as not to have voids inside. Thereby, a highly reliable semiconductor device can be manufactured.

  In the semiconductor device manufacturing method according to the present embodiment, the resin paste 50 may be supplied from between the side 44 of the semiconductor chip 40 and the wiring substrate 10 (see FIG. 3A). Here, the side 44 is a side other than the opposite side 43 described above. In other words, the side 44 may be a side arranged next to the opposite side 43. Further, the side facing the side 44 may be referred to as a side 45. By supplying the resin paste 50 from the side 44, the flow rate of the resin paste 50 can be reduced at both sides (side 43) along the flow direction of the resin paste 50, so that the resin paste 50 reaches the side 45. The time required can be lengthened. Therefore, before the resin paste 50 that flows along the outer periphery of the semiconductor chip 40 blocks the space between the side 45 and the wiring substrate 10, the resin paste 50 that travels through the central region of the semiconductor chip 40 can flow to the side 45. (See FIG. 3C). Therefore, the resin paste 50 can be filled between the wiring substrate 10 and the semiconductor chip 40 so that no voids remain (see FIGS. 3C and 3D), and a highly reliable semiconductor device. Can be manufactured.

(Modification)
A method for manufacturing a semiconductor device according to a modification of the first embodiment to which the present invention is applied will be described below with reference to the drawings. It should be noted that the contents described above are applied as much as possible in the following modifications.

  In the example shown in FIG. 5, a hole 60 is formed in the resist layer 20. The hole 60 has substantially the same width as the side of the region 41 for mounting the semiconductor chip 40. According to this, the flow rate of the resin paste traveling along the side 43 can be slowed over a wide range. Therefore, the resin paste 50 can be filled between the wiring substrate 10 and the semiconductor chip 40 more reliably.

  The hole 60 may be a through hole that exposes the substrate 10 (wiring pattern 14) as shown in FIG. According to this, the surface property of the base substrate 12 and the unevenness of the wiring pattern 14 become resistance to the flow of the resin paste 50, and the flow rate of the resin paste 50 can be further reduced inside the hole 60. When the hole 60 is a through hole, the resin paste 50 may be flowed so as to completely cover the hole 60. Thereby, the malfunction by the wiring pattern 14 being exposed can be avoided. Note that such control may be performed by adjusting the amount and viscosity of the resin paste 50.

  Further, in the example shown in FIG. 5, the wiring board has a second resist layer 25 formed in the central region of the opening 22. According to this, since the flow rate of the resin paste 50 can be increased in the central region of the semiconductor chip 40, the resin paste 50 can be easily filled between the wiring substrate 10 and the semiconductor chip 40. At this time, the surface of the second resist layer 25 may be a flat surface. As a result, the flow rate of the resin paste 50 traveling through the central region of the semiconductor chip 40 can be further increased.

  In the example illustrated in FIG. 6, the hole 60 is disposed only on the side of one side 47 of the semiconductor chip 40 (region 41). Also by this, the flow rate of the resin paste 50 that travels around the semiconductor chip 40 can be slowed, so that the same effect as described above can be achieved. At this time, the resin paste 50 may be supplied from between the side adjacent to the side 47 and the wiring board 10. Alternatively, the resin paste 50 may be supplied from between the side facing the side 47 and the wiring board 10. Alternatively, the resin paste 50 may be supplied from between the side 47 and the wiring board 10.

  In the example shown in FIG. 7, the hole 62 is formed so as to reach a region overlapping with the semiconductor chip 40. That is, the hole 62 is formed so as to intersect the outer periphery of the semiconductor chip 40. In other words, the hole 62 has a first hole disposed on the side of the semiconductor chip 40 and a second hole disposed in a region overlapping with the semiconductor chip 40 and communicated with the first hole. You may do it. In the example shown in FIG. 7, the hole 62 is formed to communicate with the opening 22. Also by this, the same effect can be produced and a highly reliable semiconductor device can be manufactured.

(Second Embodiment)
A method for manufacturing a semiconductor device according to the second embodiment to which the present invention is applied will be described below. FIG. 8 to FIG. 9C are diagrams for explaining a method for manufacturing a semiconductor device according to the present embodiment.

  In the method of manufacturing a semiconductor device according to the present embodiment, the resist layer 20 has a hole 70 as shown in FIG. The hole 70 may be formed so as to reach a region inside the semiconductor chip 40. The hole 70 may be formed so as to communicate with the opening 22 of the resist layer 20. The hole 70 may be disposed on the side of the corner of the semiconductor chip 40 (the region 41 for mounting the semiconductor chip). Alternatively, the hole 70 may be arranged so as to intersect with any side of the semiconductor chip 40. The hole 70 may be a recess or a through hole.

  In the method for manufacturing a semiconductor device according to the present embodiment, resin paste 50 is supplied from hole 70 toward the center of semiconductor chip 40 (see FIG. 9A). At this time, the resin paste 50 may be supplied so as not to contact a portion overlapping the hole 70 on the outer periphery of the semiconductor chip 40. In other words, the resin paste 50 may be supplied so as not to come into contact with two sides constituting the corner. By supplying the resin paste 50 so as not to contact the outer periphery of the semiconductor chip 40, it is possible to prevent the resin paste 50 from proceeding along the outer periphery of the semiconductor chip 40. That is, as shown in FIGS. 9A and 9B, the resin paste 50 can be filled from the inside of the semiconductor chip 40. Therefore, it is possible to prevent the resin paste 50 from flowing so as to surround the outer periphery of the semiconductor chip 40. As a result, as shown in FIG. 9C, since the resin paste 50 can be filled so that no voids remain between the wiring board and the semiconductor chip 40, a highly reliable semiconductor device is manufactured. be able to. The resin paste 50 can be supplied so as not to contact the outer periphery of the semiconductor chip 40 by adjusting the amount, viscosity, and supply speed of the resin paste 50.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

1A and 1B are diagrams for explaining a method for manufacturing a semiconductor device according to a first embodiment to which the present invention is applied. 2A and 2B are views for explaining a method for manufacturing a semiconductor device according to the first embodiment to which the present invention is applied. FIG. 3A to FIG. 3D are views for explaining a method for manufacturing a semiconductor device according to the first embodiment to which the present invention is applied. FIG. 4A and FIG. 4B are diagrams for explaining the method of manufacturing the semiconductor device according to the first embodiment to which the present invention is applied. FIG. 5 is a diagram for explaining a method of manufacturing a semiconductor device according to a modification of the first embodiment to which the present invention is applied. FIG. 6 is a diagram for explaining a method of manufacturing a semiconductor device according to a modification of the first embodiment to which the present invention is applied. FIG. 7 is a diagram for explaining a method of manufacturing a semiconductor device according to a modification of the first embodiment to which the present invention is applied. FIG. 8 is a diagram for explaining a method of manufacturing a semiconductor device according to the second embodiment to which the present invention is applied. FIG. 9A to FIG. 9C are diagrams for explaining a method for manufacturing a semiconductor device according to the second embodiment to which the present invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Wiring board, 12 ... Base board, 14 ... Wiring pattern, 15 ... Electrical connection part, 20 ... Resist layer, 22 ... Opening, 25 ... 2nd resist layer, 30 ... Hole, 40 ... Semiconductor chip, 41 ... Area for mounting semiconductor chip, 42... Electrode, 43... Side, 44 .. Side, 45 .. Side, 46 .. Integrated circuit, 47 .. Side, 50 .. Resin paste, 52 ... Resin part, 60. Hole 70 ... Hole 100 ... Semiconductor module

Claims (14)

A wiring board including a wiring pattern and a resist layer in which an opening exposing a part of the wiring pattern is formed, and an electrode, and the electrode is mounted on the wiring board so as to face the wiring pattern Providing a semiconductor module having a semiconductor chip; and
Filling a resin paste between the wiring substrate and the semiconductor chip, curing the resin paste, and forming a resin portion between the wiring substrate and the semiconductor chip;
The resist layer has at least one hole disposed on a side of a region overlapping with the semiconductor chip,
A method of manufacturing a semiconductor device, wherein in the step of filling the resin paste, the resin paste is flowed so as to cover at least a part of the hole. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the hole is arranged on each side of a pair of opposite sides of the semiconductor chip facing each other. The method of manufacturing a semiconductor device according to claim 2.
A method for manufacturing a semiconductor device, wherein the resin paste is supplied from between a side other than the opposite side and the wiring board. In the manufacturing method of the semiconductor device according to claim 1,
The said hole is a manufacturing method of the semiconductor device formed by arrange | positioning to the side of all the sides of the said semiconductor chip. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the resin paste is supplied from the hole toward a central portion of the semiconductor chip. In the manufacturing method of the semiconductor device according to claim 5,
A method of manufacturing a semiconductor device, wherein the paste is supplied so as not to contact a portion overlapping the hole on the outer periphery of the semiconductor chip. In the manufacturing method of the semiconductor device in any one of Claims 1-6,
The method for manufacturing a semiconductor device, wherein the hole is formed so as to reach a region overlapping with the semiconductor chip. In the manufacturing method of the semiconductor device in any one of Claims 1-6,
The method of manufacturing a semiconductor device, wherein the hole is formed only outside a region overlapping with the semiconductor chip. In the manufacturing method of the semiconductor device in any one of Claims 1-8,
The method of manufacturing a semiconductor device, wherein the hole communicates with the opening. In the manufacturing method of the semiconductor device in any one of Claims 1-8,
The method of manufacturing a semiconductor device, wherein the hole is not communicated with the opening. In the manufacturing method of the semiconductor device in any one of Claims 1-10,
The method for manufacturing a semiconductor device, wherein the hole is formed so as to penetrate the resist layer. In the manufacturing method of the semiconductor device in any one of Claims 1-10,
The method for manufacturing a semiconductor device, wherein the hole is formed so as not to penetrate the resist layer. In the manufacturing method of the semiconductor device in any one of Claims 1-12,
The method for manufacturing a semiconductor device, wherein the wiring board further includes a second resist layer disposed in a central region of the opening of the resist layer. 14. The method of manufacturing a semiconductor device according to claim 13,
A method of manufacturing a semiconductor device, wherein the surface of the second resist layer is a flat surface.

Images