JP4436060B2 - Liquid crystal display panel and method for suppressing display spots on liquid crystal display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention generally relates to the technical field of liquid crystal display devices, and more particularly to a liquid crystal display panel of a liquid crystal display device.
[0002]
[Prior art]
In general, a liquid crystal display panel has a large number of pixels arranged in a matrix, and displays an appropriate image by controlling the orientation of liquid crystal molecules by changing the voltage applied to each pixel.
[0003]
FIG. 1 shows an equivalent circuit relating to one pixel of this type of liquid crystal display panel. As shown, this structure has a capacitance of C _LC And a thin film transistor 104 that controls charge and discharge of charges to and from the pixel capacitor unit 102. The gate electrode of the thin film transistor 104 is connected to the gate bus line 106, and the drain electrode of the thin film transistor 104 is connected to the drain bus line 108. Further, an auxiliary capacitance unit 110 having a capacitance of Cs is connected to the pixel capacitance unit 102 in parallel. A liquid crystal display panel is provided with a large number of such pixel structures in a matrix form.
[0004]
During operation, all thin film transistors 104 connected to the same gate bus line 106 are in a conductive state during a certain pulse period, and charge or discharge of charge to or from the respective pixel capacitor portions 102 is performed. When the pulse period ends, the thin film transistor 104 is turned off, and the charge accumulation state of the pixel capacitor portion 102 is maintained. In the next pulse period, all transistors connected to the gate bus line adjacent to the gate bus line 106 are turned on, and charge and discharge are performed. Thereafter, the same operation is repeated, and the state of the pixel is controlled for each gate bus line, whereby an appropriate image is displayed on the liquid crystal display panel.
[0005]
Ideally, the thin film transistor 104 does not pass any current in the non-passage state. However, since some leakage current actually flows, there is a possibility that the voltage of the pixel capacitor unit 102 fluctuates unnecessarily. In addition, a parasitic capacitance C between the pixel capacitor unit 102 and the drain bus line 108 is used. _DS As a result, the voltage of the pixel capacitor 102 may fluctuate. As described above, since pixel scanning is performed for each gate bus line, it is desirable that the pixel capacitor portions 102 related to different gate bus lines do not affect each other. However, the parasitic capacitance C between the pixel capacitor 102 and the drain bus line 108 _DS As a result, even if the gate bus lines are different, the common pixels of the drain bus lines 108 interact with each other, and so-called crosstalk noise is generated in the pixel capacitor portion 102. Further, a parasitic capacitance C between the pixel capacitor unit 102 and the gate bus line 106 is used. _GS There is also a possibility that noise resulting from the above will occur in the pixel capacitor 102. If the potential of the pixel capacitor portion 102 deviates from a desired value due to such current leakage or noise, the display content relating to that portion may not be appropriate.
[0006]
Thin film transistor leakage, parasitic capacitance C _DS , C _GS In order to cope with voltage fluctuations in the pixel capacitor unit 102 due to noise caused by the auxiliary capacitor unit 110, the auxiliary capacitor unit 110 is provided in parallel to the pixel capacitor unit 102. By providing the auxiliary capacitor portion 110, the capacitance related to one pixel increases, and the voltage fluctuation of the pixel capacitor portion 102 can be suppressed even if charge leaks to the thin film transistor 104. Further, when there is no auxiliary capacitance portion Cs, the parasitic capacitance C _DS , C _GS The voltage fluctuation or noise ΔV generated in the pixel capacitor 102 due to the
ΔV = Cp / (Cp + C _LC ) × ΔE (A)
It can be expressed as Here, Cp is a parasitic capacitance C to the drain bus line. _DS Or parasitic capacitance C between the gate bus line _GS It is. ΔE is a voltage change of the drain bus line or the gate bus line. On the other hand, the voltage fluctuation ΔV generated in the pixel capacitor 102 when the auxiliary capacitor Cs is provided is
ΔV = Cp / (Cs + Cp + C _LC ) × ΔE (B)
It can be expressed as Comparing equations (A) and (B), it can be seen that the denominator of equation (B) is larger than the denominator of equation (A). Therefore, by providing the auxiliary capacitor portion Cs, it is possible to suppress voltage fluctuation of the pixel capacitor portion 102. This type of liquid crystal display panel is disclosed in Patent Document 1, for example.
[0007]
[Patent Document 1]
Japanese Patent No. 3098345
[0008]
[Problems to be solved by the invention]
In such a conventional liquid crystal display panel, the transistor 104 and the parasitic capacitance C are the causes of voltage fluctuation or charge leakage of the pixel capacitor 102. _DS , C _GS It is assumed that what is attributed to is dominant.
[0009]
However, in the manufacturing process of the liquid crystal display panel, foreign substances may be mixed in the liquid crystal, and ions may be dissolved in the liquid crystal, thereby greatly reducing the specific resistance of the liquid crystal. For example, foreign substances such as human skin and synthetic rubber such as urethane, dust, particles, dust, etc. (hereinafter referred to as “foreign substances”) enter the liquid crystal, and the specific resistance of the liquid crystal is usually about 10E + 14, for example, about 10E + 10. To decrease. The size of the foreign matter itself is about 5 to 100 μm, but the range of the liquid crystal region contaminated by the foreign matter can be about 1 to 3 mm. Contamination of foreign matter into the liquid crystal is a concern as the size of the liquid crystal display panel to be manufactured increases.
[0010]
When the liquid crystal in the pixel is contaminated, the effect of leakage of charges from the pixel capacitor 102 through the liquid crystal becomes large, and the effect may be comparable to or exceed the magnitude of leakage due to the above-described transistor or the like. obtain. Since the conventional liquid crystal display panel does not sufficiently cope with such a situation, it becomes difficult to perform a good display when there is such contamination. When the leak of the pixel capacitor portion 102 becomes large, for example, when charge is accumulated in a certain pixel and reaches that pixel again after a predetermined writing cycle, most of the accumulated charge leaks, and in the vicinity thereof Display is not good (particularly, display spots may occur).
[0011]
For example, in the case of a normally black mode (vertical alignment type) liquid crystal, white should be displayed when a voltage is applied to the pixel, and black should be displayed when no voltage is applied (for simplicity, black and white). Is assumed.). Assuming that the liquid crystal around a certain pixel is contaminated, when white is to be displayed, the periphery of that pixel displays black, resulting in black spots (display spots). Similarly, in the case of a normally white mode liquid crystal, white spot-like spots are generated due to the contamination of the liquid crystal.
[0012]
The subject of this application is providing the liquid crystal display panel which can suppress the display spot of a liquid crystal display panel, and the method for it.
[0013]
Another problem of the present application is a liquid crystal display panel capable of suppressing display spots on the liquid crystal display panel caused by leakage of charges accumulated in the pixels of the liquid crystal display panel via the liquid crystal, and a method therefor Is to provide.
[0014]
[Means for Solving the Problems]
According to the present invention,
A liquid crystal display panel having a large number of pixels arranged in a predetermined format, wherein each pixel is
A transistor for controlling charge and discharge of the charge to the pixel;
A pixel capacitor layer comprising a pixel electrode layer connected to the transistor, and a counter electrode layer provided so that at least a part thereof faces the pixel electrode layer via a liquid crystal;
An auxiliary capacitance unit including the pixel electrode layer, the bus line layer, and an intermediate electrode layer positioned therebetween, wherein at least a part of the intermediate electrode layer is provided to face the pixel electrode through an insulating layer And an auxiliary capacitance portion in which at least a part of the intermediate electrode layer is provided to face the bus line layer with an insulating layer interposed therebetween.
The pixel electrode layer and the intermediate electrode layer in some of the pixels are electrically connected, and the pixel electrode layer and the intermediate electrode layer in the other pixels are electrically insulated. Characteristic LCD panel
Is provided.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
[First embodiment]
FIG. 2 is a plan view of one pixel (more specifically, a portion relating to one color in one pixel) in the liquid crystal display panel according to the first embodiment of the present application. FIG. 3 is a sectional view taken along the line AA shown in FIG. Hereinafter, the pixel structure 200 will be described with reference to FIGS. The pixel structure 200 includes a gate bus line 202 and a drain bus line 206, and the drain bus line 206 is provided via an insulating film 204 in a positional relationship orthogonal to the gate bus line 202. A thin film transistor 201 is provided at the intersection of the gate bus line 202 and the drain bus line 206 to control charge / discharge of charges with respect to the pixel structure. The thin film transistor 201 has a channel layer 208 made of amorphous silicon, which is provided on the insulating film 204 so as to face the gate bus line 202. An insulating channel protective layer 210 is provided on the channel layer 208. The thin film transistor 201 includes a source electrode 212 connected to the channel layer 208. The thin film transistor 201 is covered with an insulating protective layer 214. The pixel structure 200 has a pixel electrode 216 on the protective layer 214, and the pixel electrode 216 is connected to the source electrode 212 through a conductive contact portion 218.
[0016]
On the other hand, the pixel structure 200 includes a storage capacitor bus line 220 formed in the same process as the gate bus line 202. The pixel structure 200 has an intermediate electrode layer 222 at the same level as the source electrode 212, and a part of the intermediate electrode layer 222 provided on the insulating layer 204 is in a positional relationship facing the storage capacitor bus line 220. Portion 224 is not in such a positional relationship. That is, the other portion 224 does not overlap with the auxiliary capacity bus line. A pixel electrode 216 is located above the intermediate electrode layer 222 with an insulating layer 214 interposed therebetween. Although not shown, in practice, a counter electrode is provided on the pixel structure shown in FIGS. 2 and 3, and the space between them is filled with liquid crystal. That is, the orientation of the liquid crystal molecules is controlled by applying a voltage between the pixel electrode and the counter electrode through the thin film transistor 201. It is not essential for the present invention to form the gate bus line 202 and the auxiliary capacitor bus line 220 in the same process, but from the viewpoint of simplifying the manufacturing process, they may be formed simultaneously with the same material. desirable. The same applies to the formation of the source or drain electrode and the intermediate electrode layer 222.
[0017]
FIG. 4 shows an equivalent circuit diagram of the pixel structure shown in FIGS. As shown in the drawing, a thin film transistor 201 is provided at the intersection of the gate bus line 202 and the drain bus line 206. The source electrode 212 of the thin film transistor 201 is connected to the pixel electrode 216, and the pixel electrode 216 and the counter electrode (not shown) have a capacitance of C. _LC The pixel capacitor portion 224 is formed. The pixel electrode 216 and the intermediate electrode layer 222 have a capacitance of C. _S1 The first auxiliary capacitance portion 226 is formed, and the intermediate electrode layer 222 and the auxiliary capacitance bus line 220 have a capacitance of C. _S2 The second auxiliary capacitance portion 228 is formed. The first and second auxiliary capacitor units 226 and 228 are connected in series and connected in parallel to the pixel capacitor unit 224.
[0018]
Hereinafter, a method for suppressing display spots on the liquid crystal display panel will be described. The liquid crystal display panel according to the present embodiment is provided with a number of pixel structures as shown in FIGS. 2 to 4 in a matrix form. First, the liquid crystal display panel is operated to find out the coordinates of pixels that cause display spots and their affected ranges. This operation is performed, for example, with the driving frequency of the liquid crystal display panel to be inspected being lower than the original operating frequency. This is because the influence of charge leakage is promoted by extending the writing period for the pixel. Further, it is possible to perform an acceleration test by setting the temperature higher than the normal use temperature by utilizing the property that the resistance of the liquid crystal decreases when the temperature is increased. Furthermore, it is possible to perform a test while changing other parameters as necessary. In any case, if a display spot is observed as a result of the test, the coordinates and the influence range are specified.
[0019]
The pixel electrode 216 and the intermediate electrode layer 222 of each pixel (abnormal pixel) thus identified are electrically connected. For example, the connection process can be easily performed by irradiating the portion 224 with a laser (using the laser ablation effect) from the auxiliary capacitor bus line 220 side of the insulator 204 in FIG. Is possible.
[0020]
FIG. 5 is a cross-sectional view when the pixel electrode layer 216 and the intermediate electrode layer 222 are electrically connected. As shown in the figure, by performing laser irradiation, the metal forming the electrodes is melted and the electrodes are short-circuited. Note that the electrical connection portion 230 between the pixel electrode layer 216 and the intermediate electrode layer 222 can be formed by any method other than laser irradiation. However, from the viewpoint of forming the connection portion 230 simply and quickly, a portion 224 that does not overlap with the auxiliary capacitance bus line 220 is provided in advance as in the present embodiment, and from the substrate side where the thin film transistor is provided. It is desirable to irradiate a laser.
[0021]
FIG. 6 shows an equivalent circuit of a pixel structure when the pixel electrode layer 216 and the intermediate electrode layer 222 are electrically connected. Compared with FIG. 4 showing the pixel structure before connection, it can be seen that the first auxiliary capacitor 226 is removed after connection. The capacity of the auxiliary capacity section is (1 / C in the case shown in FIG. _S1 + 1 / C _S2 ) ^-1 = C _S1 C _S2 / (C _S1 + C _S2 This is C _S1 Less than and C _S1 The following values were obtained. On the other hand, the capacity of the auxiliary capacity unit in the case shown in FIG. _S2 Thus, it becomes larger than the case of FIG. For example, C _S1 = C _S2 Assuming = C, the capacity of the auxiliary capacitor portion is C / 2 before the connection portion 230 is formed, but increases to C (doubled) after the connection portion 230 is formed. Since the capacity of the auxiliary capacitance unit related to the abnormal pixel is increased, charge leakage related to the abnormal pixel is suppressed more than before connection.
[0022]
Hereinafter, it will be described that display spots can be suppressed by this method more than in the past. C for simplicity _S1 = C _S2 = C. The pixels of the conventional liquid crystal display panel have a structure as shown in FIGS. In this case, C which is the capacity of the auxiliary capacity unit _S2 The larger the is, the higher the ability to suppress the leakage current for that one pixel. However, as described above, due to the contamination of the liquid crystal, it may be difficult to sufficiently suppress the leakage current related to a certain pixel even if a large capacity is set. For this reason, pixels with very little leakage current (normal pixels) and other pixels with high leakage current (abnormal pixels) appear on the liquid crystal display panel, and the difference in display state between them (normal pixels and abnormal pixels) (Potential difference between the two) is observed as a noticeable display spot. That is, if the capacitance C is set large in order to reduce the leakage current, it is possible to suppress the leakage current itself by an amount corresponding to the increase in the capacitance C. However, when an abnormal pixel occurs, the normal pixel The potential difference between the abnormal pixel and the abnormal pixel is increased, and the display spots are increased.
[0023]
On the other hand, the pixels of the liquid crystal display panel according to the embodiment of the present invention initially have a structure as shown in FIGS. As described above, the capacity of the auxiliary capacity unit is C / 2, which is smaller than that of the structure shown in FIGS. Therefore, regarding each pixel, the pixel according to the embodiment of the present invention is initially set to have a lower ability to suppress the leakage current than a pixel having a conventional structure. The normal pixel of this embodiment is less affected by the leakage current than the conventional normal pixel, and the voltage is greatly reduced compared to the conventional normal pixel. On the other hand, when it is determined that a certain pixel is an abnormal pixel, the pixel is changed to the structure shown in FIGS. 5 and 6, and the ability to suppress the influence of the leakage current is enhanced to the same extent as the conventional pixel. It is done. Therefore, the current is present in the same degree as the conventional pixel. The normal pixel of this embodiment has a larger voltage drop due to the leakage current than the conventional normal pixel, and the abnormal pixel has a voltage drop comparable to that of the conventional pixel. Therefore, the difference amount between the normal pixel and the abnormal pixel in the embodiment of the present application (difference in the voltage of the pixel capacitance) is smaller than the difference amount between the normal pixel and the abnormal pixel in the related art. Display spots appearing on the liquid crystal display panel can be suppressed more than ever. According to this embodiment, instead of sacrificing the influence of leakage current of individual pixels, the potential difference between normal pixels and abnormal pixels in a large number of pixels is reduced, thereby suppressing display spots on the liquid crystal display panel. It becomes possible to do.
[0024]
[Second Embodiment]
FIG. 7 is a sectional view of a pixel structure according to the second embodiment of the present application. FIG. 8 shows an equivalent circuit diagram of the pixel structure shown in FIG. In general, the pixel structure according to the present embodiment is the same as that shown in FIG. 4, but the portions related to the intermediate electrode layer are different. The pixel structure 700 includes a gate bus line 702 and a drain bus line 706, and the drain bus line 706 is provided via an insulating film 704 in a positional relationship orthogonal to the gate bus line 702. A thin film transistor 701 for controlling charge / discharge of charges with respect to the pixel structure is provided at an intersection of the gate bus line 702 and the drain bus line 706. The thin film transistor 701 includes a channel layer 708 made of amorphous silicon, which is provided on the insulating film 704 so as to face the gate bus line 702. An insulating channel protective layer 710 is provided over the channel layer 708. The thin film transistor 701 includes a source electrode 712 connected to the channel layer 708. The thin film transistor 701 is covered with an insulating protective layer 714. The pixel structure 700 includes a pixel electrode 716 on the protective layer 714, and the pixel electrode 716 is connected to the source electrode 712 through a conductive contact portion 718.
[0025]
On the other hand, the pixel structure 700 has a storage capacitor bus line 720 at the same level as the gate bus line 702 (at the same height). The pixel structure 700 includes first and second intermediate electrode layers 722 and 723 at the same level as the source electrode 712, and part of the first and second intermediate electrode layers 722 and 723 provided on the insulating layer 704 is an auxiliary element. The other portions 724 and 725 are not in such a positional relationship, although they are in a positional relationship facing the capacitor bus line 720. That is, the other portions 724 and 725 do not overlap with the auxiliary capacity bus line 720. A pixel electrode 716 is located above the first and second intermediate electrode layers 722 and 723 with an insulating layer 714 interposed therebetween.
[0026]
FIG. 8 shows an equivalent circuit diagram of the pixel structure shown in FIG. As shown in the drawing, a thin film transistor 701 is provided at the intersection of the gate bus line 702 and the drain bus line 706. The source electrode 712 of the thin film transistor 701 is connected to the pixel electrode 716, and the pixel electrode 716 and the counter electrode (not illustrated) have a capacitance of C. _LC The pixel capacitor portion 724 is formed. The pixel electrode 716 and the first intermediate electrode layer 722 have a capacitance of C. _S1 The first auxiliary capacitance portion 732 is formed, and the first intermediate electrode layer 722 and the auxiliary capacitance bus line 720 have a capacitance of C. _S2 The second auxiliary capacitance portion 734 is formed. The first and second auxiliary capacitor units 732 and 734 are connected in series, and are connected in parallel to the pixel capacitor unit 724. Further, the pixel electrode 716 and the second intermediate electrode layer 723 have a capacitance of C. _S3 The third intermediate capacitor portion 736 is formed, and the second intermediate electrode layer 723 and the auxiliary capacitor bus line 720 have a capacitance of C. _S4 The fourth auxiliary capacitance portion 738 is formed. The third and fourth auxiliary capacitor portions 736 and 738 are also connected in series and are connected in parallel to the pixel capacitor portion 724.
[0027]
According to the present embodiment, the intermediate electrode layer is divided into two (722, 723), and each forms a different auxiliary capacitance portion. For this reason, in addition to being able to remove the first auxiliary capacitance unit 732, the capacity of the auxiliary capacitance unit can also remove the third auxiliary capacitance unit 736. By forming a connection portion as indicated by broken lines 727 and 729 in FIG. 7, the first or third auxiliary capacitance portions 732 and 736 can be removed. According to the present embodiment, there are more capacity value choices than in the first embodiment, and a more appropriate capacity value can be set. As described above, even if the capacitance value of the auxiliary capacitor portion is too large, display spots can be caused. Therefore, this embodiment can further suppress display spots than the first embodiment. 7 and 8 show an example in which the intermediate electrode layer is divided into two, it is also possible to divide the intermediate electrode layer into more regions.
[0028]
[simulation result]
FIG. 9 is a diagram showing simulation results regarding the embodiment of the present invention and the conventional example shown in FIGS. The main parameter values in the simulation are as follows.
[0029]
Pixel pitch (vertical) 294μm
Pixel pitch (horizontal) 98 μm
Capacitance (C _LC 200fF
Capacitance (C) 264.4 fF of auxiliary capacity section after connection
Auxiliary capacity before connection (C / 2) 132.2 fF
Voltage 2V
Transistor OFF leakage current 1 × 10 ^-11 A
Liquid crystal specific resistance (before contamination) 1 × 10 ¹⁴ Ω / m
Specific resistance of liquid crystal (after contamination) 1 × 10 ⁹ Ω / m
Frame frequency 60Hz
Write cycle 16.6ms
In this simulation, the liquid crystal is contaminated by foreign matters mixed in the liquid crystal, and the specific resistance of the liquid crystal is 1 × 10. ¹⁴ To 1 × 10 ⁹ It is assumed that it has changed to Ω / m. A graph 902 in FIG. 9 shows a voltage for a normal pixel in which the capacitance (auxiliary capacitance value) of the auxiliary capacitance unit is C. A graph 904 shows a voltage for an abnormal pixel having an auxiliary capacitance value C. A graph 906 shows a voltage for a normal pixel having an auxiliary capacitance value of C / 2. A graph 908 shows a voltage for an abnormal pixel having an auxiliary capacitance value of C / 2. As shown in the figure, in either case, the pixel voltage decreases with time. As is clear from the graphs 902 and 906 regarding the normal pixels and the graphs 904 and 908 regarding the abnormal pixels, the larger the capacitance value, the higher the ability to maintain the voltage (the ability to suppress the leakage current). Therefore, when the normal pixel has a large capacity 902, the pixel voltage can be maintained most, and when the abnormal pixel has a small capacity 908, the pixel voltage decreases most.
[0030]
In the conventional liquid crystal display panel, since all the pixels have the same auxiliary capacitance value C, voltage drop characteristics as shown in graphs 902 and 904 are exhibited. A difference (Δ1) in the vertical axis direction of these graphs affects display spots. In the present embodiment, the voltage drop characteristic shown in the graph 906 is shown for normal pixels. The abnormal pixel initially exhibits the voltage drop characteristic shown in the graph 908, but the repair operation described with reference to FIGS. 5 and 6 is performed, so that the abnormal pixel exhibits the voltage drop characteristic in the graph 904. Therefore, the potential difference (Δ2) that affects the display spots is the difference in the vertical axis direction between the graph 906 and the graph 904, which is smaller than the conventional value (Δ2 <Δ1). Therefore, the embodiment of the present application can suppress display spots more than the conventional example.
[0031]
FIG. 10 shows the potential difference in the simulation result shown in FIG. 9 in detail. That is, the potential difference (Δ1) between the normal pixel and the abnormal pixel in the conventional example is shown by a graph 1012, and the potential difference (Δ2) between the normal pixel and the abnormal pixel in this embodiment is shown by a graph 1014. ing. According to the embodiment of the present application, it is shown that the potential difference causing display spots can be suppressed to about 60%.
[0032]
FIG. 11 is also a diagram showing a simulation result similar to FIG. 10, but in this simulation, the value of the auxiliary capacitance value C is doubled (C _new = 2xC _old ). As described above, the larger the capacity of the auxiliary capacitance portion, the higher the ability to suppress the leakage current. Therefore, the potential difference between the graph 1102 related to the conventional example and the graph 1104 related to the present embodiment is generally low. In the case of this numerical example, it is shown that the embodiment of the present application can suppress the potential difference causing display spots to about 40%.
[0033]
The means taught by the present invention will be enumerated below.
[0034]
(Supplementary Note 1) A liquid crystal display panel having a large number of pixels arranged in a predetermined format, wherein each pixel is
A transistor for controlling charge and discharge of the charge to the pixel;
A pixel capacitor layer comprising a pixel electrode layer connected to the transistor, and a counter electrode layer provided so that at least a part thereof faces the pixel electrode layer via a liquid crystal;
An auxiliary capacitance unit including the pixel electrode layer, the bus line layer, and an intermediate electrode layer positioned therebetween, wherein at least a part of the intermediate electrode layer is provided to face the pixel electrode through an insulating layer And an auxiliary capacitance portion in which at least a part of the intermediate electrode layer is provided to face the bus line layer with an insulating layer interposed therebetween.
The pixel electrode layer and the intermediate electrode layer in some of the pixels are electrically connected, and the pixel electrode layer and the intermediate electrode layer in the other pixels are electrically insulated. A characteristic LCD panel.
[0035]
(Supplementary note 2) The liquid crystal display panel according to supplementary note 1, wherein the liquid crystal display panel has a conductive through hole provided in a portion where a pixel electrode layer and an intermediate electrode layer of a part of the plurality of pixels are opposed to each other.
[0036]
(Supplementary note 3) The liquid crystal display panel according to supplementary note 1, wherein a part of the intermediate electrode layer is formed so as not to face the bus line.
[0037]
(Supplementary note 4) The liquid crystal display panel according to supplementary note 1, wherein the intermediate electrode layer comprises a plurality of electrode layers insulated from each other.
[0038]
(Supplementary note 5) The liquid crystal display panel according to supplementary note 1, wherein each of the plurality of electrode layers has a portion that does not face the bus line.
[0039]
(Supplementary note 6) The liquid crystal display panel according to supplementary note 1, wherein an electrode layer forming a source and a drain of the transistor and the intermediate insulating layer are formed of the same material.
[0040]
(Additional remark 7) It is a method of suppressing the display spot of a liquid crystal display panel, Comprising: Each of many pixels arranged in the predetermined format within the said liquid crystal display panel is,
A transistor for controlling charge and discharge of the charge to the pixel;
A pixel capacitor layer comprising a pixel electrode layer connected to the transistor, and a counter electrode layer provided so that at least a part thereof faces the pixel electrode layer via a liquid crystal;
An auxiliary capacitance unit including the pixel electrode layer, the bus line layer, and an intermediate electrode layer positioned therebetween, wherein at least a part of the intermediate electrode layer is provided to face the pixel electrode through an insulating layer And an auxiliary capacitance portion in which at least a part of the intermediate electrode layer is provided to face the bus line layer with an insulating layer interposed therebetween.
And the method is
A specific step of identifying a pixel causing display spots on the liquid crystal display panel;
Connection step of electrically connecting the pixel electrode layer and the intermediate electrode layer of the pixel specified in the specifying step
A method for suppressing display spots on a liquid crystal display panel.
[0041]
(Supplementary note 8) The method according to supplementary note 7, wherein the connection step includes a step of forming a conductive connection portion between the pixel electrode layer and the intermediate electrode layer by irradiating a laser.
[0042]
(Supplementary note 9) The method according to supplementary note 7, wherein the source and drain electrode layers of the transistor and the intermediate electrode layer are formed in the same film formation step.
[0043]
【The invention's effect】
As described above, according to the present invention, display spots on the liquid crystal display panel can be suppressed. Furthermore, it is possible to suppress display spots on the liquid crystal display panel resulting from leakage of charge accumulated in the pixels of the liquid crystal display panel through the liquid crystal.
[0044]
[Brief description of the drawings]
FIG. 1 is an equivalent circuit diagram relating to one pixel of a conventional liquid crystal display panel.
FIG. 2 is a plan view of pixels in the liquid crystal display panel according to the first embodiment of the present application.
FIG. 3 is a sectional view taken along line AA shown in FIG. 2;
4 shows an equivalent circuit diagram of the pixel structure shown in FIGS. 2 and 3. FIG.
FIG. 5 is a cross-sectional view of a pixel structure when an auxiliary capacitance is increased in the first embodiment of the present application.
6 is an equivalent circuit diagram of the pixel structure shown in FIG.
FIG. 7 is a cross-sectional view of a pixel structure according to a second embodiment of the present application.
FIG. 8 is an equivalent circuit diagram of the pixel structure shown in FIG.
FIG. 9 is a diagram showing simulation results regarding the embodiment of the present invention and a conventional example.
FIG. 10 is a diagram showing simulation results regarding the embodiment of the present invention and a conventional example.
FIG. 11 is a diagram showing simulation results related to the embodiment of the present invention and a conventional example.
[Explanation of symbols]
102 Pixel capacity section
104 Thin film transistor
106 Gate bus line
108 Drain bus line
110 Auxiliary capacitor
200,700 pixel structure
201,701 Thin film transistor
202,702 Gate bus line
204,704 Insulating film
206,706 Drain electrode
208,708 channel layer
210,710 Channel protective film
212,712 Source electrode
214, 714 Insulating film
216,716 Pixel electrode
218,718 contact
220,720 Auxiliary capacity bus line
222,723 Intermediate electrode layer
226,228,732,734,736,738 Auxiliary capacity section

Claims (4)

A liquid crystal display panel having a large number of pixels arranged in a predetermined format, wherein each pixel is
A transistor for controlling charge and discharge of the charge to the pixel;
A pixel capacitor unit having a counter electrode layer pixel electrode layer connected to the transistor, and at least a portion through the liquid crystal is provided so as to face the pixel electrode layer,
An auxiliary capacitor having the pixel electrode layer, the bus line layer, and an intermediate electrode layer located between the pixel electrode layer and the bus line layer;
A part of the intermediate electrode layer is opposed to the pixel electrode layer and the bus line layer, and another part of the intermediate electrode layer is opposed to the pixel electrode layer. Are formed so as not to face each other
The other portion and the pixel electrode layer are electrically short-circuited in the case of pixels causing display spots in the liquid crystal display panel, and are electrically short-circuited in the case of other pixels. No LCD display panel.   The liquid crystal display panel according to claim 1, wherein the intermediate electrode layer includes a plurality of electrode layers insulated from each other.   The liquid crystal display panel according to claim 1, wherein an electrode layer forming a source and a drain of the transistor and the intermediate electrode layer are formed of the same material. A method for suppressing display spots on a liquid crystal display panel, each of a large number of pixels arranged in a predetermined format in the liquid crystal display panel,
A transistor for controlling charge and discharge of the charge to the pixel;
A pixel capacitor unit having a counter electrode layer pixel electrode layer connected to the transistor, and at least a portion through the liquid crystal is provided so as to face the pixel electrode layer,
An auxiliary capacitor having the pixel electrode layer, the bus line layer, and an intermediate electrode layer located between the pixel electrode layer and the bus line layer;
A part of the intermediate electrode layer is opposed to the pixel electrode layer and the bus line layer, and another part of the intermediate electrode layer is opposed to the pixel electrode layer. Are formed so as not to face each other.
A specific step of identifying a pixel causing display spots in the liquid crystal display panel;
A method of suppressing display unevenness of a liquid crystal display panel, comprising: electrically short-circuiting between the another portion of the pixel specified in the specifying step and the pixel electrode layer.

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