JP4435749B2 - ESD protection circuit - Google Patents

Description

  The present invention relates to an electrostatic breakdown protection circuit (hereinafter simply referred to as “protection circuit”) that is provided in a semiconductor integrated device and prevents electrostatic breakdown.

  2. Description of the Related Art In recent years, a semiconductor integrated device is mainly a CMOS-IC (Complementary Metal Oxide Semiconductor-Integrated Circuit) excellent in low power consumption and high integration. The MOS transistor used in this CMOS-IC has a structure in which a gate electrode is stacked on a semiconductor substrate with a thin gate oxide film sandwiched, and the source, drain and gate electrode are separated and formed by the gate oxide film. . Therefore, the CMOS-IC has an essential drawback that the gate oxide film is easily broken when an electrostatic surge enters from the outside. In order to cover this drawback, a protection circuit is provided regardless of the input terminal or the output terminal.

  FIG. 2 is a circuit diagram showing a conventional input terminal protection circuit, and FIG. 3 is a circuit diagram showing a conventional output terminal protection circuit.

The input terminal protection circuit includes a P-channel MOS transistor (hereinafter referred to as “PMOS”) 1 whose gate and source are connected to a source line Lv for transmitting a power supply potential VDD and fixed in an off state, and a ground GND. An N-channel MOS transistor (hereinafter referred to as “NMOS”) 2 having a gate and a source connected to a source line Lg for transmitting a potential and fixed in an OFF state, and an input pad Pi serving as an input terminal is The drains of the PMOS1 and NMOS2 are connected. An input pad Pi connected to the drains of the PMOS 1 and the NMOS 2 is connected to the gates of the transistors 4 a and 4 b in the internal circuit 4 to be protected via the gate protection resistance element 3.

  In such a general input terminal protection circuit, when an electrostatic surge enters the input pad Pi, the resistor element 3 delays the surge voltage applied to the gate of the internal circuit 4 to be protected, so that the PMOS 1 and the NMOS 2 The electrostatic surge is absorbed by the source line Lv or Lg.

In the output terminal protection circuit, the gate and the source are connected to the source line Lv that transmits the power supply potential VDD and the gate 5 and the source are connected to the PMOS 5 fixed in the off state, and the source line Lg that transmits the potential of the ground GND. The output pad Po serving as an output terminal is connected to the drains of the PMOS 5 and the NMOS 6. The output node N of the internal circuit 7 to be protected is an output transistor 7a that turns on and off between the node N and the power supply potential VDD, and an output transistor 7b that turns on and off between the node N and the power supply potential VDD. The node N is also connected to the drains of the PMOS 5 and the NMOS 6.

  In such an output terminal protection circuit, the electrostatic surge intrusion from the output pad Po is shunted to the PMOS 5 or NMOS 6 and the node N side, thereby ensuring the electrostatic breakdown resistance of the internal circuit 7.

JP-A-5-102475 JP-A-6-97380

  However, with the progress of miniaturization technology, it is difficult to ensure sufficient resistance to electrostatic breakdown with the conventional protection circuit. Hereinafter, problems of the conventional protection circuit will be described while explaining the operation of the protection circuit.

  When an electrostatic surge is applied to the input pad Pi, a breakdown occurs between the drain and the substrate of the PMOS 1 or NMOS 2, the PNP or NPN bipolar transistor parasitic on the structure of the PMOS 1 or NMOS 2 is turned on, and the surge current is a bipolar current. Is absorbed by the source lines Lv and Lg. Therefore, in order for PMOS1 or NMOS2 to function, the drain voltage must once reach breakdown. By the way, ordinary transistors are formed so that the impurity diffusions of the drain and the source are somewhat inserted under the gate, except for some protection transistors and high-voltage operation transistors. Therefore, the drain impurity diffusion layer and the gate overlap each other with the gate oxide film interposed therebetween at the end of the gate. Therefore, in the conventional protection circuit, a voltage stress equal to the breakdown voltage is applied to the portion of the gate oxide film sandwiched between the drain impurity diffusion layer and the gate until the drain breaks down.

  In order to prevent the gate oxide film at the gate end having such a structure from being destroyed, it is necessary to cause the drain to break down before the gate oxide film is destroyed. That is, it is necessary to set the gate oxide film thick so that the intrinsic breakdown voltage of the gate oxide film is higher than the breakdown voltage of the drain. The input terminal protection circuit is originally arranged for the purpose of protecting the gate of the transistor of the internal circuit 4 connected to the input terminal. The protection circuit for the input terminal is provided with PMOS 1 and NMOS 2 and the resistance element 3. A delay is applied while the surge voltage is released to the source lines Lv and Lg.

  When the gate oxide film is thin, it is necessary to increase the resistance of the resistance element 3 accordingly. However, this also delays the gate signal during normal operation, and cannot satisfy the requirement for high-speed operation. Also in the output terminal protection circuit, the destruction of the gate oxide film at the gate end of the MOS transistors 7a and 7b of the internal circuit 7 or the protection transistors PMOS5 or NMOS6 is a serious problem.

  As the miniaturization progresses, the gate oxide film becomes thinner, and the difference between the intrinsic breakdown voltage and the breakdown voltage of the drain is reduced. In other words, in recent semiconductor integrated devices, there is almost no difference between the breakdown voltage and the intrinsic breakdown voltage of the gate oxide film. Therefore, when a breakdown voltage near the intrinsic breakdown voltage is applied to the gate oxide film, the gate oxide film is destroyed. Not only is it easy to break, but also the problem that the characteristics of the PMOS 1 and the NMOS 2 deteriorate due to carrier injection into the gate oxide film due to the surge current has become apparent. Thus, in the conventional method in which the PMOS 1 and the NMOS 2 are once broken down and the subsequent bipolar current is absorbed into the source lines Lv and Lg, the drain breakdown voltage is set lower than the intrinsic breakdown voltage of the gate oxide film. Therefore, it was practically difficult to employ a thin gate oxide film having an intrinsic breakdown voltage lower than the breakdown voltage. If the gate oxide film can be made thin regardless of the breakdown voltage, the response speed, current drive capability, etc. can be greatly improved, and not only the performance of the semiconductor integrated device can be greatly improved, but also the manufacturing process can be set freely. The degree goes up dramatically.

  Further, in recent semiconductor integrated devices, the width of the potential supply wiring cannot catch up with the increase in the number of outputs, and the power supply potential VDD decreases when a plurality of output terminals are switched at the same time. In consideration of problems such as malfunction of the circuit and problems such as switching noise from the digital circuit adversely affecting the input or output level of the analog circuit due to fluctuations in the power supply potential VDD The potential supply wiring of the transistor and the potential supply wiring of the other circuits of the internal circuit 7 are made independent, or the potential supply wiring of the digital circuit and the analog circuit is provided separately, and each potential supply wiring is connected to the external connection terminal with gold wires Connected with the bonding used. An example of such an input / output protection circuit of a semiconductor integrated device having a plurality of power supplies is shown in FIG.

  FIG. 4 is a circuit diagram showing a conventional input / output protection circuit. Elements common to those in FIGS. 2 and 3 are denoted by common reference numerals.

This protection circuit includes an input stage of an internal circuit having input transistors 4a and 4b connected in series between an input power supply terminal Ti1 and an input ground terminal Ti2, an output power supply terminal To1, and an output ground terminal. Provided between the output stage of the internal circuit having the output transistors 7a and 7b connected in series with To2 and the input / output pad Pio, and includes the protection transistors PMOS8 and NMOS9. Yes. The source and gate of the PMOS 8 are connected to the power supply terminal To1, the source and gate of the NMOS 9 are connected to the ground terminal To2, and the drains of the PMOS 8 and NMOS 9 are connected to the input / output pad Pio. The drains of the PMOS 8 and NMOS 9 and the input / output pad Pio are connected to the gates of the input transistors 4 a and 4 b through the protective resistance element 3. Further, the protection circuit includes a PMOS 10 that is a protection transistor connected between the power supply terminals To1 and Ti1, and an NMOS 11 that is a protection transistor connected between the ground terminals To2 and Ti2. The gate and source of the PMOS10 is connected to the power supply terminal Ti1, a drain of the PMOS10 is connected to the power supply terminal To1, when usually the PMOS10 is turned so that to turn off. The gate and the source of NMOS11 is connected to the power supply terminal Ti2, a drain of the NMOS11 is connected to the power supply terminal To2, when usually the NMOS11 is turned so that to turn off.

In the protection circuit of Figure 4, the path dedicated protection transistor is not provided, that is, when the electrostatic surge between input output pad Pio and the input power supply terminal Ti1 or input ground terminal Ti2 has flowed, once protection PMOS 8 and NMOS 9 respond, and discharge a surge current to the power supply terminal To1 or the ground terminal To2, and then the PMOS 10 connected between the power supply terminals To1 and Ti1, or the NMOS connected between the ground terminals To2 and Ti2. Since the surge current is absorbed by passing the current through 11 , these protection transistors operate in two stages. Therefore, the response to the electrostatic surge is inevitably deteriorated and the resistance of the protection resistance element 3 must be increased. There is also a problem that the gate oxide films of the input transistors 4a and 4b are destroyed.

The electrostatic breakdown preventing circuit of the present invention includes a signal line connected to an input / output terminal, an output circuit, an input circuit, a first protection means, a first protection transistor, and a second protection means . I have.

The output circuit is connected to the signal line, a first potential supply line to which a first potential is applied, and a second potential supply line to which a second potential is applied. The input circuit is connected to the signal line, a third potential supply line to which a third potential is applied, and a fourth potential supply line to which a fourth potential is applied . Before SL first protection means, the first being connected between said third potential supply line and the potential supply line, before the power supply said third potential supply line and the first potential supply line And electrically connect. The first protection transistor includes a first electrode connected to the signal line, a second electrode connected to the first potential supply line, and a control connected to the first potential supply line. It consists of electrodes. Furthermore, the second protection means is connected between the signal line and the control electrode of the first protection transistor, and before the power supply, the control electrode of the first protection transistor and the first electrode of the first protection transistor The first electrode of the protection transistor is electrically connected.

Further, in the electrostatic breakdown prevention circuit, wherein the output circuit further comprises an output transistor, and a third protective Teto, the.

In the electrostatic breakdown preventing circuit, the first protection means further includes a second protection transistor and a fourth protection means.

In the electrostatic breakdown preventing circuit, the first protection means further includes an input transistor and a fifth protection means.

  According to the present invention, when the semiconductor integrated device is in an inactive state, the gate electrode and the first electrode of the protection transistor are short-circuited, so that no voltage is applied to the gate oxide film of the protection transistor, and the gate oxide film is destroyed. Can be prevented.

  The electrostatic breakdown prevention circuit includes a signal line connected to the input / output terminal, an output circuit, and first protection means. The output circuit is connected to the signal line, a first potential supply line to which a first potential is applied, and a second potential supply line to which a second potential is applied. The input circuit is connected to the signal line, a third potential supply line to which a third potential is applied, and a fourth potential supply line to which a fourth potential is applied. Further, the first protection means is connected between the first potential supply line and the third potential supply line, and before the power is supplied, the first potential supply line and the third potential supply. Electrically connect the wires.

  First, reference examples 1 to 3 which are the premise of the first embodiment of the present invention will be described with reference to FIGS.

FIG. 5 is a circuit diagram of a protection circuit showing Reference Example 1 of the present invention.
This protection circuit is provided between the input pad Pi that is an input terminal of the semiconductor integrated device and the gate of the input transistor of the internal circuit, and the anode is connected to the signal line Ls1 connected to the input pad Pi. And a pn diode 21 serving as a protective element whose cathode is connected to the potential supply line Lvd for supplying the first power supply potential VDD, and a potential for connecting the cathode to the signal line Ls1 and for the anode to supply the ground GND potential. And a pn diode 22 as a protection element connected to the supply line Lgd. Such a diode 21, 22 connected to the signal line Ls1, one end of the resistor 23 is connected to the other end of the resistor 23, de I repression type NMOS (hereinafter, referred to as D-NMOS) 24 third The drain as an electrode, the drain of the D- NMOS 25, and the gates of the PMOS 31 and the NMOS 32 of the input transistor constituting the input stage 30 of the internal circuit are connected.

The source that is the fourth electrode of the D-NMOS 24 is connected to the potential supply line Lvd, and the source of the D-NMOS 25 is connected to the potential supply line Lgd. The gates of the D-NMOS 24 and 25 are connected to a power supply line Lvb that supplies a second power supply potential VBB lower than the power supply potential VDD and the ground GND potential .

  In the input stage 30 of the internal circuit, the drains of the PMOS 31 and the NMOS 32 are connected, the source of the PMOS 31 is connected to the potential supply line Lvd, and the source of the NMOS 32 is connected to the potential supply line Lgd.

  FIG. 6 is a cross-sectional view showing the structure of the D-NMOS, and FIG. 7 is a characteristic diagram showing the current-voltage characteristics of the D-NMOS. With reference to FIGS. The difference in the likelihood of electrostatic breakdown in the apparatus will be described.

  In a CMOS semiconductor integrated device, electrostatic breakdown is most likely to occur when handled in an inactive state, that is, in a single state in which a power supply voltage is not supplied to a power supply terminal. This is easy to understand when considering when the semiconductor integrated device is in an active state. A semiconductor integrated device is in an active state when it is incorporated in a higher-level system such as a predetermined printed circuit board. Once the semiconductor integrated device is mounted on the substrate, other semiconductor integrated devices and various electronic devices are connected via wiring. Since it is connected to a component, even if an electrostatic surge is applied to a specific terminal, it is shunted to other semiconductor integrated devices and electronic components, so that the electrostatic stress is reduced as compared with the case where it is handled alone. In other words, a protection circuit for preventing electrostatic breakdown is provided for the purpose of imparting predetermined breakdown resistance to a semiconductor integrated device in an inactive state, that is, a state where it is handled alone.

  For example, as shown in FIG. 6, the D-NMOS 24 in FIG. 5 is doped with an N-type impurity in a P-type substrate surface region through a gate oxide film under the gate 24g, and an N-type source 24s and drain 24d are formed. This is short-circuited in the channel region 24c and functions as a resistance element indicated by the characteristic 40 in FIG. 7 when the semiconductor integrated device is in an inactive state. When a negative voltage equal to or lower than the threshold voltage is applied to the gate 24g of the D-NMOS 24, the P-type substrate surface turns into a storage layer and changes to the P-type region, and the channel region 24c disappears. Once the channel region 24c disappears, the source 24s and the drain 24d are substantially insulated with a very high resistance as indicated by the characteristic 41 in FIG. If the semiconductor integrated device is in an active state, that is, incorporated in a higher system, when the semiconductor integrated device has a built-in step-down circuit, the step-down circuit generates a negative voltage below the threshold value to the gate 24g. By supplying, the D-NMOS 24 can be replaced with an insulating element. Further, when the step-down circuit is not incorporated, the D-NMOS 24 can be similarly replaced with an insulating element by supplying the negative voltage directly from the external system side. The D-NMOS 25 functions similarly.

Next, the operation of the protection circuit of the first reference example will be described with the above two points as a background.
In the inactive state where the gate oxide film is easily destroyed as described above, since the potential VBB is not applied from the power supply line Lvb, the D-NMOS 24 functions as a resistance element, and the source of the signal line Ls1 and the PMOS 31 And are short-circuited. Similarly, the D-NMOS 25 short-circuits the signal line Ls1 and the source of the NMOS 32. Even if a positive or negative electrostatic surge enters the signal line Ls1 in this state, the signal Ls1 and the sources of the PMOS 31 and NMOS 32 of the CMOS input are short-circuited. In addition, the potential difference does not occur in the gate oxide film sandwiched between the gate electrode-source diffusion layers in the PMOS 31 and NMOS 32, and the gate oxide film regardless of the response speed of the diode 21 or 22 to the surge. Is effectively prevented from being destroyed.

  When a positive electrostatic surge enters the potential supply line Lvd, the electrostatic surge flows to the potential supply line Lgd via the D-NMOSs 24 and 25. When a positive electrostatic surge enters the potential supply line Lgd, the electrostatic surge flows to the potential supply line Lvd via the diodes 21 and 22 and the D-NMOSs 24 and 25.

  After the power supply voltage is applied to the power supply terminal and activated, the negative voltage VBB below the threshold value introduced from the step-down circuit or from the outside is supplied, and the D-NMOS 24 and 25 behave as insulating elements, Since the signal line Ls1 and the sources of the PMOS 31 and NMOS 32 are insulated from each other, they can be operated normally. Even if an electrostatic surge is applied to the signal line Ls1 in this state, it is already connected to other semiconductor integrated devices and various elements via wiring on the substrate, and surge stress is diverted. Therefore, the gate oxidation of the PMOS 31 and NMOS 32 The risk of the membrane being destroyed is small.

  As described above, in the first reference example, the D-NMOS 24 and 25 that are turned on when the semiconductor integrated device is inactive and are cut off when activated are provided in the input terminal protection circuit. There are advantages like

  (1) In an inactivated state where the gate oxide film is easily destroyed, when an electrostatic surge enters the signal line Ls1 from the outside of the semiconductor integrated device via the input pad Pi, the signal line Ls1 and the source of the PMOS 31 Is short-circuited by the D-NMOS 24 and the gate oxide film of the PMOS 31 can be reliably protected from electrostatic surge. Similarly, the signal line Ls1 and the source of the NMOS 32 are short-circuited by the D-NMOS 25, so that the gate oxide film of the NMOS 32 can be reliably protected from the electrostatic surge, and the breakdown of each gate oxide film can be prevented.

  In a state where the semiconductor integrated device is mounted on the substrate and can be supplied with the power supply voltage and electrostatic breakdown is unlikely to occur, the negative potential VBB below the threshold is supplied from the power supply line Lvb. Therefore, the D-NMOS 24 and 25 become insulating elements, and as a result, the device function is not adversely affected. Therefore, it is possible to realize an input terminal protection circuit having excellent resistance to electrostatic breakdown.

  (2) Since no high voltage is applied to the gate oxide film between the gate electrode and the source diffusion layer of each PMOS 31 and NMOS 32, the resistance value of the protection resistor 23 for delay can be kept low, and the gate signal during normal operation Can be reduced.

FIG. 8 is a circuit diagram of a protection circuit showing Reference Example 2 of the present invention.
The protection circuit, which provided for the output pad Po which is the output terminal of the semiconductor integrated device, the drain is the third electrode to the signal line Ls2 connected to the output pad Po is connected D-NMOS 51 and 52 as first protection means are provided.

The output stage 60 of the internal circuit of the semiconductor integrated device has PMOS 61 and NMOS 62 which are output transistors, and the drain which is the first electrode of these PMOS 61 and NMOS 62 is also connected to the signal line Ls2. The source which is the second electrode of the PMOS 61 is connected to a potential supply line Lvd for supplying the power supply potential VDD, and the internal signal line Ls3 of the semiconductor integrated device is connected to the gate of the PMOS 61. The source of the NMOS 62 is connected to the potential supply line Lgd that supplies the ground GND potential , and the internal signal line Ls4 of the semiconductor integrated device is connected to the gate of the NMOS 62. On the other hand, the source, which is the fourth electrode of each D-NMOS 51, 52, is connected to the gates of the PMOS 61 and NMOS 62, respectively, and the power line Lvb is connected to the gates of the D-NMOS 51, 52. The power supply line Lvb is connected to the ground GND in the inactive state so that the D-NMOSs 51 and 52 function as resistance elements when the semiconductor integrated device is in an inactive state and function as insulating elements in the active state. This wiring supplies a potential VBB lower than the potential to the gates of the D-NMOSs 51 and 52.

Next, the operation of the protection circuit of the reference example 2 will be described.
The operation of each D-NMOS 51, 52 with respect to the potential VBB is the same as in Reference Example 1, and the description thereof is omitted here.

  When the semiconductor integrated device is inactive, the gate of the PMOS 61 and the signal line Ls2 of the output stage 60 to be protected are connected to the signal line Ls2, and the gate of the NMOS 62 and the signal line Ls2 to be protected are connected to the D−. Shorted by NMOSs 51 and 52. In this state, even if an electrostatic surge is applied to the signal line Ls2, no voltage is applied to the gate oxide films of the PMOS 61 and NMOS 62.

  On the other hand, when the semiconductor integrated device is activated, the potential between the gate of the PMOS 61 and the signal line Ls2 and between the gate of the NMOS 62 and the signal line Ls2 is supplied to the gates of the D-NMOSs 51 and 52 from the power supply line Lvb. When VBB is supplied and the D-NMOS 51 and 52 become insulating elements, conduction is cut off. In this state, the PMOS 61 and the NMOS 62 are turned on and off based on the signals on the internal signal lines Ls3 and Ls4, set the potential of the signal line Ls2, and output it via the output pad Po.

As described above, in Reference Example 2, the D-NMOSs 51 and 52 are connected to the signal line Ls2 connected to the output pad Po, and the signal lines Ls2 and the PMOS 61 are in an inactive state where the gate oxide film is easily destroyed. Since the gate and the signal line Ls2 and the gate of the NMOS 62 are short-circuited, destruction of the gate oxide film in the PMOS 61 and the NMOS 62 can be reliably prevented. Further, when the semiconductor integrated device is mounted on the substrate and can be supplied with the power supply voltage, and it is difficult for electrostatic breakdown to occur, if the negative potential VBB is supplied to the gates of the D-NMOSs 51 and 52, the D-NMOS 51 is supplied. , 52 can be used as insulating elements, and normal device functions are not adversely affected. That is, an output protection circuit having excellent electrostatic breakdown resistance can be realized.

  FIG. 9 is a circuit diagram of a protection circuit showing Reference Example 3 of the present invention. Elements common to those in FIG. 8 are denoted by common reference numerals.

The feature of this protection circuit is that D-NMOS 53 and 54 as second protection means are further provided in the protection circuit of Reference Example 2, and the other configurations are the same as those in FIG. The drain that is the third electrode of the D-NMOS 53 is connected to the gate of the PMOS 61, and the source that is the fourth electrode of the D-NMOS 53 is connected to the potential supply line Lvd. The drain of the D-NMOS 54 is connected to the gate of the NMOS 62, and the source of the D-NMOS 54 is connected to the potential supply line Lgd. That is, the gate of the PMOS 61 to be protected is connected to the power supply potential VDD via the D-NMOS 53, and the gate of the NMOS 62 to be protected is connected to the ground GND potential via the D-NMOS 54. The gates of the D-NMOS 53 and 54 are connected to the power supply line Lvb.

Since the operations of the D-NMOS 51 and 52 are the same as those of the reference example 2, their description is omitted here.
In the protection circuit of Reference Example 3, when the semiconductor integrated device is in an inactive state, the D-NMOS 51 to 54 are in a conductive state, so the signal line Ls2 is connected to the potential supply line Lvd via the two D-NMOSs 51 and 53. At the same time, the signal line Ls2 is connected to the potential supply line Lgd via the two D-NMOSs 52 and 54 and short-circuited. In this state, even if an electrostatic surge enters the output pad Po, it directly enters the potential supply line Lvd via the two D-NMOSs 51 and 53 or directly via the D-NMOSs 52 and 54. To flow.

  On the other hand, when the semiconductor integrated device is activated. Since the potential VBB is supplied from the power supply line Lvb to the D-NMOSs 51 to 54 and the D-NMOSs 51 and 53 serve as insulating elements, the drain, source, and gate of the PMOS 61 are cut off. Similarly, since the D-NMOSs 52 and 54 serve as insulating elements, the drain, source, and gate of the NMOS 62 are cut off.

  As described above, in Reference Example 3, since the D-NMOS 53 and 54 are further provided in the protection circuit of Reference Example 2, in addition to the advantages of Reference Example 2, the following advantages can be obtained. .

  (1) Even if an electrostatic surge enters the output pad Po in an inactive state in which electrostatic breakdown is likely to occur, it can flow directly to the potential supply line Lvd or the potential supply line Lgd, thus adversely affecting normal device functions. In addition, the gate oxide film can be prevented from being destroyed more reliably than in the second reference example.

  (2) In response to a surge current flowing into the internal signal line Ls3 through the D-NMOS 51 and a surge current about to flow into the internal signal line Ls4 through the D-NMOS 52, the D-NMOSs 53 and 54 are connected to the potential supply line. Since a path for exiting to Lvd or Lgd is secured, there is no fear that the internal signal lines Ls3 and Ls4 themselves are destroyed by the surge current.

  FIG. 1 is a circuit diagram of a protection circuit showing a first embodiment of the present invention. Elements common to those in FIGS. 5 and 8 are denoted by common reference numerals.

  This protection circuit is provided for the input / output pad Pio of the semiconductor integrated device, and the resistance 23 and the same resistor 23 as in Reference Example 1 for protecting the PMOS 31 and NMOS 32 constituting the input stage 30 of the semiconductor integrated device. D-NMOS 24 and 25, and D-NMOS 51 and 52 similar to Reference Example 2 for protecting the PMOS 61 and NMOS 62 of the output stage 60, and these are signal lines Ls5 for inputting and outputting signals to the input / output pad Pio. On the other hand, it is connected in the same manner as in Reference Examples 1 and 2.

This protection circuit further includes a PMOS 71, which is a protection transistor in which the drain of the first electrode is connected to the signal line Ls5, and the source and gate of the second electrode are connected to the potential supply line Lvd, and similarly, the drain is a signal. The NMOS 72 which is a protection transistor connected to the line Ls5, the source and gate of which are connected to the potential supply line Lgd, the drain which is the third electrode is connected to the signal line Ls5, and the source which is the fourth electrode is the gate of the PMOS 71. And a D- NMOS 73 having a drain connected to the signal line Ls5 and a source connected to the gate of the NMOS 72. The gates of the D-NMOS 73 and 74 are commonly connected to the power supply line Lvb.

Next, the operation of the protection circuit according to the first embodiment will be described.
The basic operations of the resistor 23 and D-NMOS 24 and 25 provided for the input stage 30 of the semiconductor integrated device and the D-NMOS 51 and 52 provided for the output stage 60 are the same as those in the first and reference examples 2. Therefore, explanation is omitted here.

  In the first embodiment, the newly added protection target is two gate oxide films sandwiched between the gates of the PMOS 71 and the NMOS 72 and the drain diffusion layer connected to the signal line Ls5. The PMOS 71 and the NMOS 72 function so that when an electrostatic surge is applied to the signal line Ls5, a breakdown occurs between the drain and the substrate, and the surge current flows as a bipolar current to the potential supply line Lvd or Lgd. Here, when the semiconductor integrated device is in an inactive state, the D-NMOS 73 and 74 function as resistance elements, and the gates of the PMOS 71 and the NMOS 72 are short-circuited to the signal line Ls5. Therefore, even if an electrostatic surge is applied to the input / output pad Pio, a high voltage is not applied to the gate oxide films of the PMOS 71 and the NMOS 72.

  On the other hand, when the semiconductor integrated device is activated, the potential VBB from the power supply line Lvb is supplied to the gates of the D-NMOSs 73 and 74, and the D-NMOSs 73 and 74 function as insulating elements. The conduction between the signal line Ls5 and between the gate of the NMOS 72 and the signal line Ls5 is cut off.

As described above, in the first embodiment, the input circuit includes the PMOS 71 and the NMOS 72 that are connected between the signal line Ls5 and each of the potential supply lines Lvd and Lgd, and whose gates are respectively connected so as to be in an off state in a steady state. The output protection circuit is provided with D-NMOSs 73 and 73 that serve as resistance elements when the semiconductor integrated device is in an inactive state and serve as insulating elements when the semiconductor integrated device is in an active state. Therefore, it has the following advantages.

(1) When the semiconductor integrated device is inactive, the signal line Ls5 and the gate of the PMOS 71 are short-circuited by the D-NMOS 73, and the signal line Ls5 and the gate of the NMOS 72 are short-circuited by the D-NMOS 74. A high voltage is not applied to the gate oxide film. Therefore, those gate oxide films can be reliably protected. In addition, after the semiconductor integrated device is mounted on the substrate and is in an active state where the supply of power supply voltage can be received and the electrostatic breakdown is less likely to occur, the D-NMOS 73 and 74 become insulating elements, and the PMOS 71 and NMOS 72 Since the gate is cut off from the signal line Ls5, the normal device function is not adversely affected. That is, an input / output protection circuit excellent in resistance to electrostatic breakdown can be realized.

  (2) In general, in the manufacturing process of a semiconductor integrated device, the driving transistors 31, 32, 61, 62 used for the input stage 30 and the output stage 60 and the protection transistor 71 for ensuring the resistance to electrostatic breakdown are provided. 72 are formed at the same time, the gate oxide film thickness of the driving transistors 31, 32, 61, 62 and the gate oxide film thickness of the protection transistors 73, 74 are equal. This means that if the gate oxide film thickness is reduced for miniaturization, the gate oxide films of the protection transistors 71 and 72 are easily destroyed. However, in the first embodiment, since a high voltage is not applied to the gate oxide film between the drain diffusion layer and the gate in the protection transistors 71 and 72, when setting the gate oxide film thickness in the manufacturing process of semiconductor manufacturing, There is no restriction on the breakdown voltage, and it is possible to form a thin gate oxide film having an intrinsic breakdown voltage lower than the breakdown voltage. In other words, both the gate oxide films of the protection transistors 71 and 72 and the drive transistors 31, 32, 61 and 62 can be set thin, and the response speed of the drive transistor can be reduced by thinning the gate oxide film. In addition, since the current drive capability is improved and the gate oxide films of both the drive transistors 31, 32, 61, 62 and the protection transistors 71, 73 can be prevented from being destroyed, the performance of the semiconductor integrated device is greatly improved. In addition, the degree of freedom in setting the manufacturing process is greatly improved.

  FIG. 10 is a circuit diagram of a protection circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

The feature of this protection circuit, the protection circuit according to the first embodiment, in addition, is by providing the D -NMOS75,76, other configurations are made in the same manner as in FIG. 9 in the first embodiment. The drain as the third electrode and the source as the fourth electrode of the D-NMOS 75 are connected between the gate of the NMOS 71 and the potential supply line Lvd, and the drain and source of the D-NMOS 76 are connected to the gate of the NMOS 72 and the potential supply line. Lgd. The gates of the D-NMOS 75 and 76 are commonly connected to the power supply line Lvb.

Next, the operation of the protection circuit according to the second embodiment will be described.
The basic operations of the resistor 23 and D-NMOS 24 and 25 provided for the input stage 30 of the semiconductor integrated device and the D-NMOS 51 and 52 provided for the output stage 60 are the same as those in the first and reference examples 2. Since the PMOS 71 and the NMOS 72 operate in the same manner as in the first embodiment, description thereof is omitted here.

When the semiconductor integrated device is in an inactive state, the D-NMOSs 73 to 76 function as resistance elements, the signal line Ls5 is connected to the potential supply line Lvd via the D-NMOSs 73 and 75, and is further short-circuited. It is short-circuited by being connected to the potential supply line Lgd through 74 and 76. In this state, when an electrostatic surge is applied to the signal line Ls5 via the input / output pad Pio, the surge flows directly to the potential supply line Lvd or Lgd.

  On the other hand, when the semiconductor integrated device is activated, each D-NMOS 73 to 76 functions as an insulating element by the negative potential VBB below the threshold value of each D-NMOS 73 to 76 given from the power supply line Lvb. The gate of the NMOS 72 is cut off from the signal line Ls5 and the potential supply lines Lvd and Lgd. That is, when the semiconductor integrated device is activated, an environment that does not affect the normal device function of the semiconductor integrated device is set.

  As described above, in the second embodiment, since the D-NMOS 75 and 76 are provided in the protection circuit of the first embodiment, the following advantages can be obtained in addition to the advantages of the first embodiment.

  (1) The electrostatic surge that has entered from the input / output pad Pio can flow directly to the potential supply lines Lvd and Lgd, and the gate oxide films of the PMOS 71 and NMOS 72 can be protected more reliably than in the first embodiment.

(2) For an electrostatic surge that flows into the gate of the PMOS 71 via the D-NMOS 73, a path through which the D-NMOS 75 passes to the potential supply line Lvd is formed and flows into the gate of the NMOS 72 via the D-NMOS 74. On the other hand, since the path through which the D-NMOS 76 passes to the potential supply line Lgd is formed, it is possible to prevent the line connecting the gates of the PMOS 71 and the NMOS 72 and the power supply line Lvb from being destroyed.

  FIG. 11 is a circuit diagram of a protection circuit showing a third embodiment of the present invention. Elements common to the elements in FIG. 10 of the second embodiment are denoted by common reference numerals.

The protection circuit is characterized in that a resistor 77 is connected between the gate of the PMOS 71 and the potential supply line Lvd in the protection circuit of the second embodiment, and a resistor 78 is connected between the gate of the NMOS 72 and the potential supply line Lgd. Other configurations are the same as those of the second embodiment shown in FIG. When the resistance value of the resistor 77 is R1, the resistance value of the D-NMOS 73 is R2, and the resistance value of the D-NMOS 75 is R3, the following equation (1) is satisfied. When the resistance value of the resistor 78 is R4, the resistance value of the D-NMOS 74 is R5, and the resistance value of the D-NMOS 76 is R6, the following equation (2) is satisfied.
R1 × R3 / (R1 + R3) ≧ 1/4 × R2 (1)
R4 × R6 / (R4 + R6) ≧ 1/4 × R5 (2)

12, the current of the protection transistor of the third embodiment - a characteristic diagram showing a voltage characteristic, with reference to FIG. 12 of this, the operation of the protection circuit of the third embodiment.

  Assuming that the drain voltage at which the drain current starts flowing is the operation start voltage, in the case of the PMOS 71 in which the gate is short-circuited to the drain (VG = VD) and the source is connected to the ground potential, the drain voltage is set to the threshold voltage Vthp or less. At the time of lowering, a channel is formed under the gate, so that transistor current starts to flow. That is, the threshold voltage becomes the operation start voltage. On the other hand, in the case of the PMOS 71 whose gate is short-circuited to the source (VG = VS) and grounded, no channel flows under the gate even when the drain voltage reaches the threshold voltage Vthp. Current gradually begins to flow when the voltage is lowered to the breakdown voltage V1 or lower. That is, the operation start voltage becomes the breakdown voltage V1. Usually, the latter is used for the protection transistor. Similarly, in the case of the NMOS 72, when the gate is short-circuited to the drain, the transistor current starts to flow when the drain voltage is raised above the threshold voltage. Therefore, the operation start voltage is the threshold voltage Vthn, and the gate is short-circuited to the source. The operation start voltage is the breakdown voltage V2. Like the PMOS 71, the latter is used for the protection transistor.

  By the way, the transistor is destroyed by the electrostatic surge due to Joule heat generation accompanying the surge current, which is defined by (drain current) × (drain voltage), so that the drain voltage can be kept low. As a result, a larger amount of current can flow, and good electrostatic breakdown resistance can be ensured. Generally, the threshold voltage of a transistor is 0. Since the breakdown voltage VB is about 7 to 8 volts to several tens of volts, the protection transistor with the gate shorted to the drain has a lower operation start voltage than the transistor with the gate shorted to the source. When the current is flowing, the drain voltage is also lowered, and it has excellent electrostatic breakdown resistance.

  The signal line Ls5 in the third embodiment is temporarily connected to the gate of the PMOS 71 by the D-NMOS 73, and the gate is connected to the potential supply line Lvd via the resistance element 77 and the D-NMOS 75. Here, when the conditions of the expressions (1) and (2) are satisfied, the gate potential of the PMOS 71 is set lower than the threshold voltage Vthp when a negative electrostatic surge enters the signal line Ls5 when the semiconductor integrated device is inactive. Therefore, a channel is formed under the gate, and the electrostatic surge current can be absorbed by the potential supply line Lvd as a transistor current. Similarly, when a positive electrostatic surge enters the NMOS 72, the gate potential of the NMOS 72 is set higher than the threshold voltage Vthn, a channel is formed under the gate, and the electrostatic surge current is absorbed as a transistor current into the potential supply line Lgd. be able to. Other operations are the same as those in the second embodiment.

As described above, since the resistors 77 and 78 are provided in the third embodiment, the gate potential of the PMOS 71 is lowered to the drain side by the electrostatic surge of the negative electrode that has entered the input / output pad Pio in the inactive state. The channel is formed, and the surge current is directly supplied to the potential supply line Lvd as the transistor current, and the gate potential of the NMOS 72 is raised to the signal line Ls5 side by the positive electrostatic surge, and the surge current is directly supplied to the potential supply line Lgd as the transistor current. Can be flowed to. On the other hand, in the active state, by supplying a potential VBB having a negative threshold voltage to the gates of the D-NMOS 73 and 75 and the D-NMOS 74 and 76, they can be used as insulating elements. Therefore, it does not adversely affect the operation of a normal semiconductor integrated device. That is, for electrostatic surge, because PMOS71 and NMOS72 protection transistor operates in the threshold voltage, than the protection circuit starts operating in the breakdown voltage, furthermore, it is possible to suppress the drain voltage low can reduce the Joule heat . Furthermore, the PMOS 71 and the NMOS 72 themselves can be prevented from being destroyed with a transistor area smaller than that of the second embodiment.

  FIG. 13 is a circuit diagram of a protection circuit showing a fourth embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.

In this protection circuit, the semiconductor integrated device has a plurality of power supply terminals for inputting a common potential, a plurality of lines for transmitting a common potential VDD from each terminal, and a plurality of lines for transmitting a common ground GND potential. The protection circuit is shown.

That is, the sources of the PMOSs 61 and 71 in the first embodiment are connected to the potential supply line Lvd1, the source of the PMOS 31 in the input stage 30 is connected to the potential supply line Lvd2, and the sources of the NMOSs 62 and 72 are connected to the potential supply line Lgd1. The source of the NMOS 32 is connected to the potential supply line Lgd2. Then, the potential supply line LVD1, the drain is a third electrode D -NMOS81 is connected to the fourth source is an electrode of the D-NMOS 81 is connected to a voltage supply line LVD2. On the other hand, the potential supply line Lgd1, drain a third electrode D -NMOS82 is connected to the fourth source is an electrode of the D-NMOS 82 is connected to a voltage supply line Lgd2. A power line Lvb is connected to the gates of the D-NMOSs 81 and 82. The other structure is the same as that of FIG.
Here, the PMOS 31 and NMOS 32 are input transistors, the PMOS 61 and NMOS 62 are output transistors, the PMOS 71 and NMOS 72 are first protection transistors, the D-NMOSs 81 and 82 are first protection means, and the D-NMOSs 73 and 74 are second protection means. Further, the D-NMOS 51 and 52 are third protection means.

  In the protection circuit of the fourth embodiment, when the semiconductor integrated device is in an inactive state, the potential supply lines Lvd1 and Lvd2 are short-circuited by the D-NMOS 81, and similarly, the potential supply lines Lgd1 and Lgd2 are short-circuited by the D-NMOS 82. Yes. Therefore, for example, when an electrostatic surge is applied between the potential supply line Lvd2 and the signal line Ls5, a surge current flows to the gate of the PMOS 71. However, since the gate is short-circuited, the surge current is applied to the potential supply line Lvd1. Flows. Furthermore, since the potential supply lines Lvd1 and Lvd2 are short-circuited, a surge current is discharged to the potential supply line Lvd2 via the D-NMOS 81. On the other hand, when the semiconductor integrated device is in an active state, the threshold voltage VBB is applied from the power supply line Lvb, so that the D-NMOSs 81 and 82 become insulating elements, which adversely affects normal operations performed by the semiconductor integrated device. There is no. Other operations are the same as those in the first embodiment.

  As described above, in the fourth embodiment, the D-NMOS 81 is provided between the independent potential supply line Lvd1 and the potential supply line Lvd2 that supply the same potential VDD, and the potential supply line Lgd1 and the potential supply line Lgd2 Since the D-NMOS 82 is provided between the power terminals, when an electrostatic surge enters a power supply terminal or a ground terminal different from that to which the protection transistor PMOS 71 or NMOS 72 is connected, between the power terminals or the ground terminals. Since the D-NMOSs 81 and 82 are short-circuited to each other, the PMOS 71 or the NMOS 72 is provided to the potential supply line Lvd2 and the potential supply line Lgd2 connected to the terminal where the protection transistor is not originally installed. Behaves as if it were a protected transistor, so good resistance to electrostatic breakdown can be obtained. A.

  In the fourth embodiment, two potential supply lines for independently supplying the same power supply potential are provided. However, in the case of three or more, the D-NMOSs 81 and 82 are similarly connected to connect the plurality of the plurality of potential supply lines. When potential supply lines are connected in parallel, electrostatic breakdown resistance can be effectively obtained with a small number of D-NMOSs 81 and 82.

  FIG. 14 is a circuit diagram of a protection circuit showing a fifth embodiment of the present invention. Elements common to those in FIG. 13 showing the fourth embodiment are denoted by common reference numerals.

This protection circuit is also used in a semiconductor integrated device in which a plurality of potential supply lines for supplying a common power supply potential VDD or ground GND potential are independent, and the sources of the PMOSs 61 and 71 are supplied with potential as in the fourth embodiment. The source of the PMOS 31 of the input stage 30 is connected to the potential supply line Lvd2, the sources of the NMOSs 62 and 72 are connected to the potential supply line Lgd1, and the source of the NMOS 32 is connected to the potential supply line Lgd2.

The potential supply line Lvd1 in the protection circuit of the fifth embodiment, the drain is a first electrode of the N MOS83 is connected, the source and gate of the second electrode of the NMOS83 is connected to the potential supply line LVD2. On the other hand, the potential supply line Lgd1, drain a first electrode of the N MOS84 is connected, the source and gate connected to the voltage supply line Lgd2 a second electrode of said NMOS84. The gate and drain of the NMOS 83 are connected by a D- NMOS 85, and the gate and drain of the NMOS 84 are connected by a D- NMOS 86. The gates of the D-NMOS 85 and 86 are connected to the power supply line Lvb.
Here, NNOS 83 and 84 are second protection transistors, D-NMOS 85 and 86 are fourth protection means, and D-NMOS 24 and 25 are fifth protection means.

Next, the operation of the protection circuit according to the fifth embodiment will be described.
When the semiconductor integrated device is inactive, the potential supply line Lvd1 and the gate of the NMOS 83 are short-circuited by the D-NMOS 85, and the potential supply line Lgd1 and the gate of the NMOS 84 are short-circuited by the D-NMOS 86. In this state, when an electrostatic surge is applied between the signal line Ls5 and the potential supply line Lvd2, the surge current flows to the gate of the PMOS 71 via the D-NMOS 73, but the gate is connected to the potential supply line Lvd1. Therefore, the current passes through the potential supply line Lvd1 as it is, and thereafter, the NMOS 83 causes a breakdown and releases an electrostatic surge to the potential supply line Lvd2. Until the electrostatic surge is released to the potential supply line Lvd2, the D-NMOS 85 prevents a surge voltage from being applied to the gate oxide film sandwiched between the drain diffusion layer and the gate of the NMOS 83. That is, the breakdown resistance of the NMOS 83 is ensured. Similarly, even when an electrostatic surge is applied between the signal line Ls5 and the potential supply line Lgd2, the surge current flows to the gate of the PMOS 72 via the D-NMOS 74, and passes through the potential supply line Lgd1, and thereafter the NMOS 84 Causes breakdown and releases an electrostatic surge to the potential supply line Lgd2. Until this electrostatic surge is released to the potential supply line Lgd2, the D-NMOS 86 prevents a surge voltage from being applied to the gate oxide film sandwiched between the drain diffusion layer and the gate of the NMOS 84. That is, the breakdown resistance of the NMOS 84 is ensured.

  On the other hand, when the semiconductor integrated device is in an active state, the supply of the potential VBB from the power supply line Lvb causes the D-NMOS 85 and 86 to become insulating elements, and the conduction is cut off. Therefore, the normal operation performed by the semiconductor integrated device is not adversely affected. Other operations are the same as those in the first and fourth embodiments.

  As described above, in the fifth embodiment, when an electrostatic surge enters a power supply terminal or a ground terminal different from that to which the protection transistors PMOS 71 and NMOS 72 are connected, the PMOS 71 and NMOS 72 are connected. D-NMOS 85 and 86 are provided in a protective circuit that once discharges electrostatic surges to the potential supply lines Lvd1 and Lgd1 and then finally discharges the electrostatic surges to the potential supply lines Lvd2 and Lgd2 by the NMOSs 83 and 84, respectively. . Therefore, a high voltage is not applied to the gate oxide films of the NMOSs 83 and 84, and the gate oxide films can be prevented from being destroyed. This is because the protection transistors 83 and 84 formed of a thin gate oxide film having an intrinsic breakdown voltage lower than the breakdown voltage are arranged between the potential supply lines Lvd1 and Lvd2 and between the potential supply lines Lgd1 and Lgd2. As a result, the degree of freedom of the process will be improved.

  FIG. 15 is a circuit diagram of a protection circuit showing Embodiment 6 of the present invention. Elements common to those in FIG. 5 showing Reference Example 1 are denoted by common reference numerals.

In the first to fifth embodiments, the D-NMOS 24 , 25 , 51 to 54 , 73 to 76 , 85 , 86 are used. Instead, an N type junction field effect transistor (hereinafter referred to as “N type FET”). It is possible to construct a protection circuit using Here, as an example, an example in which the D-NMOSs 24 and 25 of Reference Example 1 are replaced with N-type FETs 91 and 92 will be described.

  The anode of the pn diode 21 whose cathode is connected to the potential supply line Lvd is connected to the signal line Ls1 connected to the input pad Pi, and the cathode of the pn diode 22 whose anode is connected to the potential supply line Lgd. It is connected. Thus, one end of the resistor 23 is connected to the signal line Ls1 connected to the diodes 21 and 22, and the other end of the resistor 23 is connected to the drain of the protective N-type FET 91, the drain of the N-type FET 92, The gates of the PMOS 31 and NMOS 32 are connected.

  The source of the N-type FET 91 is connected to the potential supply line Lvd, and the source of the N-type FET 92 is connected to the potential supply line Lgd. The gates of the N-type FETs 91 and 92 are connected to the power supply line Lvb.

  In the input stage 30 of the internal circuit, the drains of the PMOS 31 and the NMOS 32 are connected, the source of the PMOS 31 is connected to the potential supply line Lvd, and the source of the NMOS 32 is connected to the potential supply line Lgd.

  FIG. 16 is a cross-sectional view showing the structure of an N-type FET, and FIG. 17 is a characteristic diagram showing current-voltage characteristics of the N-type FET. The operation of the protection circuit according to the sixth embodiment will be described with reference to FIGS. 16 and 17.

  For example, as shown in FIG. 16, the N-type FET 91 of the sixth embodiment is an element that short-circuits an N-type source 91s and a drain 91d by a channel 93 of a low-concentration N-type impurity region. A gate 91g which is a P-type impurity diffusion region is provided on the type impurity region. The N-type FET 91 functions as a resistance element as shown by the characteristic 94 in FIG. 17 when the semiconductor integrated device is in an inactive state. Further, when a negative voltage equal to or lower than the threshold voltage is applied to the gate 91g of the N-type FET, the low-concentration N-type impurity region is depleted and the channel 93 disappears. Once the channel 93 disappears, the source 91s and the drain 91d become extremely high resistance and substantially insulated as shown by the characteristic 95 in FIG. The N-type FET 92 operates similarly.

Therefore, as in Reference Example 1, when the semiconductor integrated circuit is in an inactive state, the N-type FET 91 becomes a resistance element, and shorts the signal line Ls1 and the source of the PMOS 31. Similarly, the N-type FET 92 short-circuits the signal line Ls1 and the source of the NMOS 32. That is, even if either a positive or negative electrostatic surge enters the signal line Ls1, the electrostatic surge flows through the diode 21 or 22 to the potential supply lines Lvd and Lgd and is absorbed, and the PMOS 31 and the gate of NMOS 32 - a potential difference is not generated in the gate oxide film sandwiched between the source diffusion layers, regardless of the response speed against the surge of the diode 21 or 22, breakdown of the gate oxide film can be effectively prevented.

  Even if each D-NMOS in the protection circuits of Embodiments 2 to 5 is replaced with an N-type FET, the operation is the same as those of the protection circuits of Embodiments 2 to 5.

  As described above, in the sixth embodiment, since the D-NMOS in the protection circuit of the first to fifth embodiments is replaced with an N-type FET, a protection circuit having the same advantages as those of the first to fifth embodiments can be realized. In addition, since the N-type FET does not have a gate oxide film like D-NMOS, it is not necessary to consider that the gate oxide film is destroyed.

FIG. 18 is a plan view of a transistor showing Example 7 of the present invention.
This transistor is a protection transistor in which the D-NMOS 51 to 54 , 73 to 76 , 85 , 86 in Examples 4 to 6 or N-type FETs 91 and 92 replaced with these D-NMOS are connected to the respective gates. PMOS 71 and NMOS 72, 83, 84.

  The gate electrode disposed between the drain and source of each of the transistors 71, 72, 83, 84 is formed of a polysilicon gate pattern 100. On the gate pattern 100, an aluminum metal wiring 101 having the same potential as that of the gate electrode is provided. The pattern 100 and the aluminum metal wiring 101 are connected by connection holes 102 provided at predetermined intervals.

Polysilicon, which is a material for the gate electrode, has a sheet resistance value of several Ω to several ten Ω. Therefore, when there is no metal wiring 101, resistances of several hundreds Ω are attached to both ends of the pattern 100 in the longitudinal direction. Even if D-NMOS 51-54 , 73-76 , 85 , 86 are connected to one end of the gate electrode of the protection transistor in such a state, a potential difference is caused at the other end of the gate electrode due to a resistance of several hundred Ω. As a result, the effect of short-circuiting the gate electrode and the drain diffusion layer cannot be obtained sufficiently and the gate oxide film may be destroyed.

  On the other hand, the potential difference does not occur in the longitudinal direction of the gate electrode by providing the metal wiring 101 and connecting them at regular intervals. Therefore, it is possible to prevent the gate oxide films of the PMOS 71 and the NMOSs 72, 83, 84 from being broken in the fourth to sixth embodiments.

FIG. 19 is a plan view of a transistor showing Embodiment 8 of the present invention.
This transistor is a D-NMOS 51-54 , 73-76 , 85 , 86 in Examples 4-6, or a transistor in which N-type FETs 91, 92 substituted for these D-NMOS are connected to each gate. One of the PMOS 71 and NMOS 72, 83, 84. This transistor includes a plurality of drain electrodes 110 and source electrodes 111 made of metal and arranged alternately, and a plurality of polysilicon patterns 112 respectively formed between the drain electrodes 110 and the source electrodes 111. ing. The plurality of polysilicon patterns 112 serve as gate electrodes, and the patterns 112 are further connected in a ladder or grid pattern with the same polysilicon.

  The transistor structure of the PMOS 71 and NMOS 72, 83, and 84 is such that the pattern 112 is connected in a ladder or grid pattern as shown in FIG. And the other end no longer generate a potential difference, and the gate oxide film can be prevented from being destroyed. Further, in the eighth embodiment, since the resistance value in the longitudinal direction of the gate electrode is reduced by using only the polysilicon material as compared with the seventh embodiment, the metal wiring on the pattern 112 becomes unnecessary, and the semiconductor integrated device has a low resistance. Cost can be reduced.

(Modification)
The present invention is not limited to the reference examples and examples described above, and various modifications can be made.

  (I) In the reference example 1, the diodes 21 and 22 are used as protection elements, but the protection transistors PMOS 71 and NMOS 72 used in the first embodiment may be used instead of the diodes 21 and 22.

(Ii) In the first to fifth embodiments , D-NMOS 51 to 54 , 73 to 76 , 85 and 86 are used as the protection means, and in the sixth embodiment, an example using the N-type FETs 91 and 92 will be described. Is explained. These protection circuits are circuits suitable for mounting a dynamic random access memory (hereinafter referred to as DRAM). The DRAM has a plurality of memory cells and an internal circuit for accessing them, and also includes a substrate potential generation circuit for generating a substrate potential VBB that becomes the second power supply potential. There is no need, and the substrate potential generating circuit can be used effectively. Here, the DRAM includes an internal booster circuit for reading data written in the memory cell. By using this booster circuit, a protection circuit that functions in the same manner as in the first to fifth embodiments can be realized.

In this case, the D-NMOSs 51 to 54 , 73 to 76 , 85 and 86 in the respective embodiments may be replaced with depletion type PMOS or P channel type junction field effect transistors.

It is a circuit diagram of the protection circuit which shows Example 1 of this invention. It is a circuit diagram which shows the conventional protection circuit for input terminals. It is a circuit diagram which shows the conventional output terminal protection circuit. It is a circuit diagram which shows the conventional input / output protection circuit. It is a circuit diagram of the protection circuit which shows the reference example 1 of this invention. It is sectional drawing which shows the structure of D-NMOS. It is a characteristic view which shows the current-voltage characteristic of D-NMOS. It is a circuit diagram of the protection circuit which shows the reference example 2 of this invention. It is a circuit diagram of the protection circuit which shows the reference example 3 of this invention. It is a circuit diagram of the protection circuit which shows Example 2 of this invention. It is a circuit diagram of the protection circuit which shows Example 3 of this invention. It is a characteristic view which shows the current-voltage characteristic of the protection transistor of the present Example 3. It is a circuit diagram of the protection circuit which shows Example 4 of this invention. It is a circuit diagram of the protection circuit which shows Example 5 of this invention. It is a circuit diagram of the protection circuit which shows Example 6 of this invention. It is sectional drawing which shows the structure of N type FET. It is a characteristic view which shows the electric current-voltage characteristic of N type FET. It is a top view of the transistor which shows Example 7 of this invention. It is a top view of the transistor which shows Example 8 of this invention.

Explanation of symbols

21,22 Diode (protective element)
24 , 25 , 51-54 , 73-76 , 85 , 86 D-NMOS (protection means)
71, 72, 83, 84 Protection transistor

Claims (21)

A signal line connected to the input / output terminal;
An output circuit connected to the signal line, a first potential supply line to which a first potential is applied, and a second potential supply line to which a second potential is applied;
An input circuit connected to the signal line, a third potential supply line to which a third potential is applied, and a fourth potential supply line to which a fourth potential is applied;
Which is connected between a first of said third potential supply line and the potential supply line, first before the power supply for electrically connecting the said third potential supply line and the first potential supply line Protection means,
A first protection comprising a first electrode connected to the signal line, a second electrode connected to the first potential supply line, and a control electrode connected to the first potential supply line A transistor,
The signal line and the control electrode of the first protection transistor are connected between the signal line and the control electrode of the first protection transistor and the first electrode of the first protection transistor before power supply. A second protective means for electrical connection;
An electrostatic breakdown prevention circuit comprising: In the electrostatic breakdown prevention circuit according to claim 1,
The electrostatic protection circuit according to claim 1, wherein the first protection means cuts off the first potential supply line and the third potential supply line after power is supplied. In the electrostatic breakdown prevention circuit according to claim 1 or 2 ,
The output circuit is
An output transistor comprising a first electrode connected to the signal line, a second electrode connected to the first potential supply line, and a control electrode connected to an internal signal line;
Connected between the control electrode of said output transistor and said signal line, the third protection before the power supply for electrically connecting the control electrode of said output transistor and said first electrode of said output transistor Hand throwing,
An electrostatic breakdown preventing circuit further comprising: The electrostatic breakdown preventing circuit according to claim 3,
The third protection means, electrostatic breakdown preventing circuit, characterized in that for blocking said control electrode after power supply is the output transistor and the first electrode of the output transistor. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 4 ,
The first protection means includes
It consists of a first electrode connected to said first potential supply line, and a second electrode connected to said third potential supply line, and the third control electrode connected to the potential supply line A second protection transistor;
Wherein said control electrode of the second protection transistor is connected between the first potential supply line, before the power supply electricity to the first potential supply line and the control electrode of the second protection transistor A fourth protective means to be connected
An electrostatic breakdown preventing circuit, further comprising: In the electrostatic breakdown preventing circuit according to claim 5,
4. The electrostatic breakdown prevention circuit according to claim 4 , wherein the fourth protection means shuts off the control electrode of the second protection transistor and the first power supply line after power is supplied. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 6 ,
The first protection means includes
A control electrode connected to said signal line, a first electrode connected to said third potential supply line, and input transistor and a second electrode connected to the fourth potential supply line ,
Connected between said third potential supply line and the signal line, before the power supply protection of the 5 for electrically connecting the first electrode of the input transistor and the control electrode of the input transistor Means,
An electrostatic breakdown preventing circuit further comprising: The electrostatic breakdown preventing circuit according to claim 7,
It said fifth protection means, said first electrode and an electrostatic breakdown preventing circuit, characterized in that for blocking after power supply is the control electrode and the input transistors of the input transistor. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 8,
The electrostatic protection circuit according to claim 1, wherein the second protection means shuts off the control electrode of the first protection transistor and the first electrode of the first protection transistor after power is supplied. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 9,
The electrostatic protection circuit according to claim 1, wherein the first protection means includes a depletion type N-type MOS transistor. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 9,
The electrostatic protection circuit according to claim 1, wherein the first protection means includes an N-channel junction field effect transistor. In the electrostatic breakdown prevention circuit according to any one of claims 3 to 11,
The third protection means includes a depletion type N-type MOS transistor. In the electrostatic breakdown prevention circuit according to any one of claims 3 to 11,
The third protection means includes an N-channel junction field effect transistor. In the electrostatic breakdown prevention circuit according to any one of claims 5 to 13,
The fourth protection means includes a depletion type N-type MOS transistor. In the electrostatic breakdown prevention circuit according to any one of claims 5 to 13,
The fourth protection means includes an N-channel junction field effect transistor. In the electrostatic breakdown prevention circuit according to any one of claims 7 to 15,
The fifth protection means includes a depletion type N-type MOS transistor. In the electrostatic breakdown prevention circuit according to any one of claims 7 to 15,
5. The electrostatic breakdown preventing circuit according to claim 5, wherein the fifth protection means includes an N-channel junction field effect transistor. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 17,
The electrostatic protection circuit according to claim 1, wherein the second protection means includes a depletion type N-type MOS transistor. In the electrostatic breakdown prevention circuit according to any one of claims 1 to 17,
The second protection means is. An electrostatic breakdown preventing circuit comprising an N-channel junction field effect transistor. In the electrostatic breakdown prevention circuit according to any one of claims 3 to 9,
The first protection means includes a first depletion type N-type MOS transistor,
The third protection means includes a second depletion type N-type MOS transistor,
The control electrode of the first depletion-type N-type MOS transistor and the control electrode of the second depletion-type N-type MOS transistor are connected to the same power supply line. circuit. In the electrostatic breakdown prevention circuit according to any one of claims 5 to 9,
The third protection means includes a first depletion type N-type MOS transistor,
The fourth protection means includes a second depletion type N-type MOS transistor,
An electrostatic breakdown prevention circuit characterized in that the control electrode of the first depletion type N-type MOS transistor and the control electrode of the second depletion type N-type MOS transistor are connected to the same power line. .

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