JP4434289B2 - Integrated circuit device, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device, an electro-optical device, an electronic apparatus, and the like.

  In recent years, high-speed serial interfaces such as LVDS (Low Voltage Differential Signaling) have attracted attention as communication means between LSIs. In this high-speed serial transfer, the transmitter circuit transmits serialized data as a differential signal, and the receiver circuit differentially amplifies the differential signal to realize data transfer.

  A general projector (projection display device) includes a substrate portion that performs processing of an image to be displayed and the like, and an optical system portion provided with a liquid crystal panel (electro-optical panel), a light source, a lens, and the like. Then, image data is transmitted from the substrate portion by the host processor, and a display driver (driver) receives the image data in the optical system portion to drive the liquid crystal panel. If a high-speed serial interface is used in such data transfer, high-speed communication corresponding to high-definition image display can be performed.

  However, the high-speed serial interface has a problem that unnecessary electromagnetic radiation (EMI noise) is generated from the serial bus because high-speed data transfer is performed even if a differential signal is used. In particular, unnecessary electromagnetic radiation tends to be prominent between the components separated like the substrate and the optical system because the transmitting side and the receiving side are separated.

  By the way, in conventional display drivers, an MPU interface which is a parallel interface for MPU (Micro Processor Unit) is widely used as an interface with a host processor. For this reason, both interfaces may be integrated in the display driver. At this time, if the terminals of the interface circuit can be made common, the cost can be reduced. However, if the interface is different, the function of the terminal is different, so that there is a problem that the terminal cannot be made common.

  According to some embodiments of the present invention, it is possible to provide an integrated circuit device, an electro-optical device, and an electronic apparatus that can share terminals between a high-speed serial interface and a parallel interface.

  The present invention includes a high-speed serial interface circuit including a receiver circuit that receives a differential signal via a serial bus, first and second guard terminals for preventing radiation, and the first and second guard terminals. Between the first terminal to which the first signal constituting the differential signal is input and the first and second guard terminals to constitute the differential signal. A second terminal to which a second signal is input; a first power supply terminal to which a power supply voltage on the high voltage side for the receiver circuit is supplied; and a second power supply to which a power supply voltage on the low voltage side is supplied. A first switch element provided between the terminal, the wiring from the first guard terminal and the wiring from the second power supply terminal, the wiring from the second guard terminal, and the second A second switch element provided between the power supply terminal and the wiring; A first I / O buffer that inputs / outputs a parallel interface signal via a guard terminal; and a second I / O buffer that inputs / outputs a parallel interface signal via the second guard terminal; In the high-speed serial interface mode, the first and second switch elements are turned on, and the outputs of the first and second I / O buffers are set to a low voltage side level or a high impedance state. Related to integrated circuit devices.

  According to the present invention, sharing of terminals can be realized by a high-speed serial interface and a parallel interface. Thus, an integrated circuit device that realizes interface selection without increasing the number of terminals can be provided. In the present invention, the interface is switched using the voltage supplied to the power supply terminal VDDA. This makes it possible to select an interface without adding terminals or signals.

  Further, according to the present invention, a switch is provided in the integrated circuit device, and the guard line and the ground wiring of the serial bus can be connected via the switch. Thereby, it is possible to prevent unnecessary electromagnetic radiation from increasing due to the parasitic resistance of the guard wire. Further, by taking measures against the integrated circuit device itself, it is possible to reduce unnecessary electromagnetic radiation countermeasure parts necessary for the wiring board.

  According to the present invention, the first and second I / O buffers include an input buffer, an output buffer, and a logic circuit, and the logic circuit is provided in a stage preceding the output buffer, and a high-speed serial interface is provided. Based on the power supply voltage on the high voltage side from the first power supply terminal during the mode, a fixed level signal is output, and when the fixed level signal of the logic circuit is input to the output buffer, The low potential side level may be output.

  As a result, an interface switchable I / O buffer can be realized.

  According to the present invention, the first and second I / O buffers include an input buffer, an output buffer, and a logic circuit, and the logic circuit supplies the power supply voltage on the high voltage side in the high-speed serial interface mode. The output of the output buffer may be set to the high impedance state based on the fixed level signal of the logic circuit.

  In this way, it is possible to realize an I / O buffer whose interface can be switched.

  In the present invention, a parallel interface circuit is included, and in the parallel interface mode, the first and second switch elements are turned off. The parallel interface circuit includes the first and second terminals and the first and second terminals. A parallel interface signal may be input via the guard terminal.

  As a result, it is possible to realize sharing of terminals between the high-speed serial interface and the parallel interface while suppressing unnecessary electromagnetic radiation in the high-speed serial interface mode.

  In the present invention, the first switch element is constituted by a first transistor, the second switch element is constituted by a second transistor, and the first and second transistors have gates connected to the first transistor. The power supply voltage on the high voltage side from one power supply terminal may be input.

  As described above, the present invention uses the power supply voltage for the receiver circuit of the high-speed serial interface circuit to control the transistor for countermeasures against radiation. As a result, sharing of terminals can be realized, and interface switching can be realized without newly adding a control terminal.

  In the present invention, a termination resistor may be provided between the first and second terminals, and the on-resistance of the first and second transistors may be equal to or less than the resistance value of the termination resistor.

  Thereby, unnecessary electromagnetic radiation can be more effectively suppressed.

  In the present invention, the first and second transistors may also be used as electrostatic protection transistors.

  This eliminates the need to provide a separate transistor for electrostatic protection, thereby reducing the cost of the integrated circuit device.

  In the present invention, the electrostatic protection transistor may be a gate control device.

  As a result, it is possible to realize the use of both a transistor for preventing unnecessary electromagnetic radiation and a transistor for electrostatic protection.

  In the present invention, a first input buffer to which a first parallel interface signal of the plurality of parallel interface signals is input from the first terminal, and the plurality of parallel interfaces from the second terminal. And a second input buffer to which a second parallel interface signal of the signals is input. The first and second input buffers are supplied to the first power supply terminal in the high-speed serial interface mode. A fixed level signal may be output based on the power supply voltage on the high voltage side.

  According to the present invention, in the high-speed serial interface mode, no signal is input to the logic circuit at the subsequent stage of the parallel interface circuit that is not used in the mode. Thereby, current consumption can be reduced. Further, by using the power supply voltage for the receiver circuit, the input buffer can be controlled without providing a new control terminal.

  The present invention further includes an inverter that operates at a power supply voltage different from the power supply voltage on the high voltage side, and the inverter is supplied with the power supply voltage on the high voltage side supplied to the first power supply terminal. The first and second input buffers may be controlled by the output of the inverter.

  As a result, the input buffer can be controlled using the power supply voltage for the receiver circuit.

  In the present invention, a low-side power supply voltage may be supplied to the first power supply terminal in the parallel interface mode.

  Thereby, interface switching can be realized using the power supply voltage for the receiver circuit.

  The present invention also includes the integrated circuit device according to any one of the above, an electro-optical panel, and a wiring board, wherein the wiring board includes a first wiring connected to the first terminal, and the first wiring. A second wiring connected to the second terminal, a first guard wiring connected to the first guard terminal, and a second guard wiring connected to the second guard terminal; , Having a first power supply wiring connected to the first power supply terminal and a second power supply wiring connected to the second power supply terminal, wherein the first and second wirings are the first power supply wiring. The present invention relates to an electro-optical device that is wired between second guard wires.

  According to the present invention, an electro-optical device that suppresses an increase in unnecessary electromagnetic radiation of the serial bus can be realized.

  In the present invention, the second power supply wiring may have a smaller wiring resistance than the first and second guard wirings.

  Thereby, increase of unnecessary electromagnetic radiation can be prevented effectively.

  According to another aspect of the invention, there is provided an electronic apparatus including the electro-optical device according to any one of the above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Electro-Optical Device FIG. 1 shows a configuration example of the electro-optical device of the present embodiment. The integrated circuit device of this embodiment can be applied to the configuration example of FIG. For example, this configuration example is used for a display unit of a projector, and is connected to an electronic board inside the projector by a connector CN. However, the integrated circuit device of the present embodiment can also be applied to other electronic devices such as a display unit such as a mobile phone.

  1 includes an electro-optical panel 400 (display panel), a wiring board 200, and a driver 100 (integrated circuit device). The electro-optical panel 400 can be composed of an active matrix liquid crystal panel such as a TFT. Further, a liquid crystal panel or an organic EL (Electro Luminescence) panel that is not an active matrix system can be used. The wiring board 200 can be configured using a printed board such as a flexible board, and wiring such as power lines and signal lines of the electro-optical panel 400 and the driver 100 is formed. The driver 100 is mounted on the wiring board 200, receives a signal via a wiring formed on the wiring board 200, and drives the electro-optical panel 400.

  Specifically, the wiring board 200 is provided with a ground wiring VSF1 (second power supply wiring) as a wiring for supplying power to the driver 100, and a power wiring VDF as a wiring for supplying power to the high-speed serial interface of the driver 100. (First power supply wiring) is wired. A plurality of ground lines can be provided. In the configuration example of FIG. 1, two lines, VSF1 and VSF2, are wired. The wiring board 200 is provided with a first wiring DPF, a second wiring DMF, a first guard wiring GF1, and a second guard wiring GF2 as wirings for transmitting signals to the driver 100. . The wiring DPF and the wiring DMF are wired between the guard wiring GF1 and the guard wiring GF2.

  The driver 100 communicates with, for example, a display information processing circuit 720 shown in FIG. 13 described later using a high-speed serial interface. At this time, the driver 100 receives the differential signal via the wirings DPF and DMF, and a ground voltage (fixed voltage in a broad sense) is applied to the guard wirings GF1 and GF2 from the electronic board of the projector via the connector CN. It is done.

  The driver 100 can also communicate using a parallel interface. At this time, the interface circuit of the driver 100 can include an I / O buffer, and can transmit and receive a CMOS level signal via the wirings GF1, DPF, DMF, and GF2.

  Here, by making the driver 100 compatible with both the high-speed serial interface and the parallel interface, the interface can be selected according to the required communication speed. In this case, if the serial bus terminal and the CMOS level signal terminal can be used in common, the number of terminals can be reduced.

  However, if the terminals are shared, the parallel interface I / O buffer is connected to the guard line of the serial bus in the high-speed serial interface mode. Therefore, there is a problem that it is necessary to switch the output of the I / O buffer between the high-speed serial interface mode and the parallel interface mode.

  By the way, in the high-speed serial interface, unnecessary electromagnetic radiation is generated from the wirings DPF and DMF as the differential signal is transmitted. Particularly in recent years, the transmission speed has been increased, and suppression of unnecessary electromagnetic radiation has become a problem in designing a high-speed serial interface. For example, standards such as VCCI exist in Japan, and electronic devices such as projectors must satisfy such standards. For this purpose, it is necessary to take effective measures against the source of unnecessary electromagnetic radiation such as a high-speed serial interface.

  For this reason, the serial bus of the high-speed serial interface is provided with a guard line for suppressing unnecessary electromagnetic radiation. In the configuration example of FIG. 1, the guard wirings GF1 and GF2 correspond to guard lines. As described above, the guard wirings GF1 and GF2 are fixed to the ground voltage, thereby absorbing unnecessary electromagnetic radiation from the wirings DPF and DMF.

  However, the guard line has a parasitic resistance due to wiring such as printed wiring. Therefore, absorption of unnecessary electromagnetic radiation by the guard wire is hindered, and there is a problem that unnecessary electromagnetic radiation from the serial bus increases.

2. High-Speed Serial / Parallel Interface Switching Circuit FIG. 2 shows a configuration example of an integrated circuit device according to this embodiment that can solve these problems. The integrated circuit device of this embodiment includes a first guard terminal G1, a second guard terminal G2, a first terminal DP, and a second terminal DM. The terminals DP and DM are arranged between the guard terminals G1 and G2.

  Specifically, in the high-speed serial interface mode, the guard terminals G1 and G2 are radiation prevention terminals, a first signal constituting a differential signal is input to the terminal DP, and a differential signal is input to the terminal DM. A second signal constituting the signal is input. That is, the differential signals are input to the terminals DP and DM via the wirings DPF and DMF in FIG. 1, and the guard wirings GF1 and GF2 in FIG. 1 are connected to the guard terminals G1 and G2 to be fixed to the ground voltage. The On the other hand, in the parallel interface mode, CMOS level signals are input to the terminals DP, DM, G1, and G2 via the wirings DPF, DMF, GF1, and GF2 in FIG.

  The integrated circuit device of this embodiment includes a high-speed serial interface circuit 40, a first power supply terminal VDDA, and a second power supply terminal VSS. The high-speed serial interface circuit 40 includes a receiver circuit 42 that receives a differential signal via a serial bus. The power supply terminal VDDA is a terminal to which a power supply voltage for the receiver circuit 42 (a power supply voltage on the high voltage side) is supplied, and is connected to the power supply wiring VDF in FIG. The ground terminal VSS (second power supply terminal) is a terminal to which a ground voltage (low-voltage side power supply voltage) is supplied, and is connected to the ground wiring VSF1. In addition to the terminal VSS, a ground terminal connected to the ground wiring VSF2 may be provided.

  For example, the receiver circuit 42 can be configured by a termination resistor R and a differential amplifier 44 as shown in FIG. The termination resistor R is provided between the wiring DPL from the terminal DP and the wiring DML from the terminal DM, and a voltage generated at both ends of the termination resistance R by the differential signal input to the terminals DP and DM is supplied to the differential amplifier 44. Entered.

  Further, the present embodiment shown in FIG. 2 includes a parallel interface circuit 60. The parallel interface circuit 60 includes I / O buffers 62-1, 62-2, 64-1, and 64-2. In the parallel interface mode, the I / O buffers 62-1 and 62-2 receive CMOS level signals via the terminals G1 and G2, and the I / O buffers 64-1 and 64-2 receive CMOS level signals via the terminals DP and DM. Input and output. On the other hand, in the high-speed serial interface mode, the outputs of the I / O buffers 62-1 and 62-2 are set to the ground voltage (low voltage side level) or the high impedance state. As a result, the high-speed serial interface circuit 40 and the parallel interface circuit 60 can share terminals. The I / O buffers 64-1 and 64-2 can be set to a high impedance state in the high-speed serial interface mode. Since this can be realized in the same manner as the I / O buffers 62-1 and 62-2, only the I / O buffers 62-1 and 62-2 will be described below.

  By the way, in the present embodiment, first and second switch elements are provided in order to suppress unnecessary electromagnetic radiation of the serial bus. For example, the first and second switch elements can be composed of first and second transistors T1 and T2 as shown in FIG. Specifically, the transistor T1 is provided between the wiring GL1 from the guard terminal G1 and the wiring VSL from the ground terminal VSS, and the transistor T2 is connected to the wiring GL2 from the guard terminal G2 and the ground terminal VSS. Provided between the wiring VSL. In the high-speed serial interface mode, when these transistors T1 and T2 are turned on, the guard wirings GF1 and GF2 are connected to the ground wiring VSF1 through the transistors T1 and T2. Thereby, it can suppress that unnecessary electromagnetic radiation increases by the wiring resistance which guard wiring GF1 and GF2 have.

3. I / O buffer 3.1. First Configuration Example FIGS. 3A and 3B show a first configuration example of the I / O buffer 62-1. Hereinafter, the I / O buffer 62-1 will be described as an example, but the same applies to the I / O buffer 62-2.

  The I / O buffer 62-1 shown in FIGS. 3A and 3B includes an input buffer BI, an output buffer BQ, and a logic circuit. This logic circuit is provided in the preceding stage of the output buffer BQ, and can be constituted by, for example, an AND circuit ANA (logical product circuit) and an inverter INA.

  As shown in FIG. 3A, in the high-speed serial interface mode, the logic circuit sets the low potential side level (fixed level in a broad sense) based on the power supply voltage for the receiver circuit 42 supplied to the power supply terminal VDDA. Output. Specifically, the power supply voltage for the receiver circuit 42 is input to the inverter INA. That is, since a voltage corresponding to the high potential side level (H) is input to the inverter INA, the inverter INA outputs a low potential side level (L). The output of the inverter INA and the output signal DQ are input to the AND circuit ANA, and the AND circuit ANA outputs the low potential side level (L) regardless of the output signal DQ. The output buffer BQ receives the output of the AND circuit ANA and outputs a low potential side level (L).

  On the other hand, as shown in FIG. 3B, the ground voltage is supplied to the power supply terminal VDDA in the parallel interface mode. This is because the power supply voltage for the receiver circuit 42 is unnecessary in the parallel interface mode. In this case, since a voltage corresponding to the low potential side level (L) is input to the inverter INA, the inverter INA outputs a high potential side logic level (H). Therefore, the AND circuit ANA outputs the output signal DQ, and the output buffer BQ outputs the output signal DQ to the wiring GF1 via the terminal G1.

  The I / O buffer 62-1 can control input / output by the output enable signal DE. For example, when the output enable signal DE is active, the output buffer BQ performs the output described with reference to FIGS. 3 (A) and 3 (B). On the other hand, when the output enable signal DE is inactive, the output buffer BQ is set to a high impedance state, and a CMOS level signal is input to the input buffer BI via the terminal G1. Such an output buffer BQ can be constituted by a clocked inverter as shown in FIG. 5, for example.

3.2. Second Configuration Example FIG. 4 shows a second configuration example of the I / O buffer 62-1. The second configuration example includes an input buffer BI, an output buffer BQ, an inverter INB, and an AND circuit ANB. The output of the inverter INB and the output enable signal DE are input to the AND circuit ANB. An output signal DQ is input to the output buffer BQ.

  Specifically, in the high-speed serial interface mode, the inverter INB outputs a low potential side level. In response to this, the AND circuit ANB outputs a low potential side level (fixed level in a broad sense) regardless of the output enable signal DE. The output of the output buffer BQ is set to a high impedance state based on the output of the AND circuit ANB.

  On the other hand, in the parallel interface mode, the inverter INB outputs a high potential side level. In response to this, the AND circuit ANB outputs an output enable signal DE. Based on the output of the AND circuit ANB, the output buffer BQ is set to a high impedance state or outputs an output signal DQ. For example, when the output enable signal DE is active, the output buffer BQ outputs the output signal DQ. On the other hand, when the output enable signal DE is inactive, the output of the output buffer BQ is set to a high impedance state, and a CMOS level signal is input to the input buffer BI via the terminal G1.

  By the way, when terminals are shared in the high-speed serial interface mode and the parallel interface mode, there is a problem that it is necessary to switch the output of the I / O buffer.

  In this regard, according to the first and second configuration examples, sharing of terminals can be realized. Therefore, it is possible to integrate the high-speed serial interface circuit and the parallel interface circuit without adding a terminal. As a result, an integrated circuit device capable of realizing interface selection while suppressing an increase in cost can be provided.

  In this embodiment, the interface is switched using the voltage supplied to the power supply terminal VDDA. This makes it possible to select an interface without adding a terminal or signal for controlling the I / O buffer.

4). Transistors T1, T2
6A and 6B, the operation of the transistors T1 and T2 of this embodiment shown in FIG. 2 will be described. 6A and 6B show the respective terminals and wiring boards on the case where the integrated circuit device of this embodiment shown in FIG. 2 is applied to the electro-optical device of this embodiment shown in FIG. Connection with wiring is shown. Specifically, the wirings DPF and DPM are connected to the terminals DP and DM, the guard wirings GF1 and GF2 are connected to the guard terminals G1 and G2, and the ground wiring VSF1 is connected to the ground terminal VSS. The connection of the power supply terminal VDDA can be changed depending on the mode as shown in FIGS. 6 (A) and 6 (B). A transistor T1 is provided between the wiring GL1 from the terminal G1 and the wiring VSL from the terminal VSS, and a transistor T2 is provided between the wiring GL2 from the terminal G2 and the wiring VSL from the terminal VSS.

  The transistors T1 and T2 are provided to suppress unnecessary electromagnetic radiation of the serial bus as described above. For example, the transistors T1 and T2 can be composed of CMOS transistors. Specifically, the gates of the transistors T1 and T2 are connected to the wiring VDL from the power supply terminal VDDA, and a voltage supplied to the power supply terminal VDDA is input.

  Specifically, as shown in FIG. 6A, in the high-speed serial interface mode, the power supply terminal VDDA is connected to the power supply wiring VDF. Since power for the receiver circuit 42 is supplied to the power supply wiring VDF, the voltage of the wiring VDL from the power supply terminal VDDA becomes the power supply voltage for the receiver circuit 42. In this case, the gates of the transistors T1 and T2 are input with the logic level on the high voltage side (first logic level in a broad sense) from the wiring VDL, and the transistors T1 and T2 are set to the on state. The Thereby, the wirings GL1 and GL2 from the guard terminals G1 and G2 are connected to the wiring VSL from the ground terminal VSL, and thus the guard wirings GF1 and GF2 are connected to the ground wiring VSF1 through the transistors T1 and T2. .

  On the other hand, as shown in FIG. 6B, in the parallel interface mode, the power supply terminal VDDA is connected to the ground wiring VSF1, and a ground voltage (power supply voltage on the low voltage side) is supplied. This is because the power supply for the receiver circuit 42 is not necessary in the parallel interface mode. In this case, the low-voltage side logic level (second logic level in a broad sense) is input to the gates of the transistors T1 and T2 from the wiring VDL, and the transistors T1 and T2 are set to the off state. The Thus, since the guard wirings GF1 and GF2 are not connected to the ground wiring VSF1, a CMOS level signal can be input to the terminals G1 and G2.

  By the way, in the high-speed serial interface, there is a problem that unnecessary electromagnetic radiation is increased due to the parasitic resistance of the guard wire preventing absorption of unnecessary electromagnetic radiation.

  In this respect, since the integrated circuit device of this embodiment can connect the guard line to the ground wiring via the transistor in the high-speed serial interface mode, the guard ground voltage can be reinforced using the power supply ground wiring. Thereby, the resistance value between a guard line and a ground voltage can be made small, and the increase in unnecessary electromagnetic radiation can be prevented.

  This will be described in detail with reference to FIG. FIG. 7 schematically shows the serial bus in this embodiment, which corresponds to the case where the serial bus is used in the high-speed serial interface mode of FIG.

  Specifically, the wirings DPF and DMF, the guard wirings GF1 and GF2, and the ground wiring VSF1 are wirings on the wiring board 200 in FIG. The wirings DPF and DMF form a transmission line by the line capacitance and the wiring inductance. In FIG. 7, this is simplified by the line capacitance CD and the wiring inductances L 1 and L 2. Guard wirings GF1 and GF2 are wired on both sides of the transmission line, CG1 represents a coupling capacitance between the wirings GF1 and DPF, and CG2 represents a coupling capacitance between the wirings GF2 and DPF. The guard wirings GF1 and GF2 are connected to the ground wiring VSF1 via the on-resistances RP1 and RP2 of the transistors T1 and T2 in FIG. The resistor R is the terminating resistor R of the receiver circuit 42 in FIG. 2, and a differential signal is input to both ends of the resistor R via a transmission line.

  As described above, the guard wirings GF1 and GF2 are fixed to the ground voltage via the connector CN of FIG. 1, and absorb unnecessary electromagnetic radiation from the wirings DPF and DMF. The absorption of this unnecessary electromagnetic radiation can be considered in place of the fact that the differential signal is transmitted as voltage noise to the guard line via the coupling capacitors CG1 and CG2 in FIG.

  First, considering the case where the transistors T1 and T2 are not provided, the voltage noise transmitted to the guard wirings GF1 and GF2 is absorbed by the ground via the connector CN. At this time, if the guard wirings GF1 and GF2 are maintained at the ground voltage, the voltage noise is sufficiently absorbed, and unnecessary electromagnetic radiation generated by the differential signal is sufficiently absorbed by the guard wirings GF1 and GF2. Will be. However, since the guard wires GF1 and GF2 have parasitic resistances RP1 and RP2, absorption of voltage noise is hindered. In this case, unnecessary electromagnetic radiation absorbed by the guard wirings GF1 and GF2 is reduced as compared with the case where the guard wirings GF1 and GF2 are maintained at the ground voltage, and as a result, unnecessary electromagnetic radiation generated from the serial bus is increased. Resulting in.

  In this regard, in the present embodiment, by providing the transistors T1 and T2, the resistance values of the guard wirings GF1 and GF2 with respect to the ground are reduced by the on-resistances RT1 and RT2. More specifically, in the present embodiment of FIG. 1, the ground wiring VSF1 has a wiring resistance smaller than that of the guard wirings GF1 and GF2. Therefore, the resistance values of the guard wirings GF1 and GF2 with respect to the ground can be greatly reduced by providing the transistors T1 and T2. Thereby, compared with the case where the transistors T1 and T2 are not provided, the guard wirings GF1 and GF2 can absorb voltage noise, and unnecessary electromagnetic radiation generated from the serial bus can be reduced.

  For example, by setting the on-resistances RT1 and RT2 of the transistors T1 and T2 to be equal to or less than the resistance value of the termination resistor R of the receiver circuit 42, unnecessary electromagnetic radiation can be further suppressed. The reason will be described below.

  The resistance value of the termination resistor R in FIG. 7 is set to a resistance value equal to the characteristic impedance ZD of the transmission line composed of the wirings DPF and DMF in order to efficiently receive the differential signal. Here, the guard wiring GF1 and the wiring DPF also constitute a transmission line by the coupling capacitor CG1 and the inductance L1, and this characteristic impedance is ZG1. Similarly, the guard wiring GF2 and the wiring DMF also constitute a transmission line, and the characteristic impedance is ZG2. The characteristic impedances ZG1 and ZG2 are wired such that the distance between the guard wiring GF1 and the wiring DPF and the distance between the guard wiring GF2 and the wiring DMF are substantially equal to the distance between the wiring DPF and DMF. It is almost equal to ZD. Therefore, the characteristic impedances ZG1 and ZG2 are substantially equal to the resistance value of the termination resistor R.

  Here, one of differential signals is input to the transmission lines of the characteristic impedances ZG1 and ZG2 from the wirings DPF and DMF, respectively. At this time, if the on resistances RT1 and RT2 are made smaller than the characteristic impedances ZG1 and ZG2, the amplitude of the voltage noise of the guard wirings GF1 and GF2 can be made smaller than the voltage amplitude of the wirings DPF and DMF. That is, since the characteristic impedances ZG1 and ZG2 are approximately equal to the resistance value of the termination resistor R, unnecessary electromagnetic radiation can be suppressed by making the on-resistances RT1 and RT2 smaller than the resistance value of the termination resistor R.

  As described above, according to the present embodiment, it is possible to prevent an increase in unnecessary electromagnetic radiation in the high-speed serial interface mode. As a result, it is possible to reduce the cost of equipment using a high-speed serial interface.

  For example, when the serial bus is routed over a long distance on the wiring board, unnecessary electromagnetic radiation is likely to increase. This is because the longer the differential signal transmission line, the greater the amount of unnecessary electromagnetic radiation generated, and the longer the guard line, the greater the parasitic resistance. For this reason, when it is necessary to route the serial bus, it is necessary to add filter parts as a countermeasure, resulting in an increase in cost.

  In this regard, in this embodiment, an increase in unnecessary electromagnetic radiation can be suppressed even in a long serial bus. In particular, the vicinity of the connection portion between the interface circuit and the serial bus is far away from the connector of the wiring board and the parasitic resistance increases. However, the countermeasure effect on the interface circuit maintains the effect of the guard line at the end of the serial bus. Thereby, cost components can be suppressed by reducing countermeasure parts such as filter parts in the wiring board. In addition, since the serial bus can be routed without increasing the cost of countermeasures against unnecessary electromagnetic radiation, the degree of freedom in designing electronic devices is improved.

  In addition, although an active element such as an IC outputs a high-speed serial interface signal that is a direct generation source of unnecessary electromagnetic radiation, actual unnecessary electromagnetic radiation is generated from wiring on the wiring board. Therefore, for example, when an electronic device manufacturer purchases an IC including a high-speed serial interface from an IC manufacturer and mounts the IC on the wiring substrate, the electronic device manufacturer has to design a wiring substrate in consideration of unnecessary electromagnetic radiation countermeasures.

  In this regard, in the present embodiment, since the countermeasure is incorporated in the integrated circuit device itself, the above design burden can be reduced. Thereby, the IC manufacturer can provide the electronic device manufacturer with an IC including a high-speed serial interface that can be easily mounted on the wiring board.

  Here, in the present embodiment, a guard line is connected to a ground line using a transistor to take measures against unnecessary electromagnetic radiation. In this case, if a terminal is shared by the high-speed serial interface and the parallel interface, there arises a problem that it is necessary to newly provide a signal and a terminal for controlling the transistor.

  In this regard, in the present embodiment, on / off of the transistor is controlled using the power supply voltage for the receiver circuit 42. As a result, it is possible to realize terminal sharing between the high-speed serial interface and the parallel interface. Further, the existing power supply terminal VDDA and the wiring VDL can be used, and the cost of the integrated circuit device can be reduced as compared with the case where a new signal or terminal is provided.

  As shown in FIG. 1, coupling capacitors CF1 and CF2 may be provided between the guard wiring and the ground wiring. Thereby, the impedance of the guard wiring can be further reduced, and unnecessary electromagnetic radiation can be suppressed.

5). Combined use of transistors T1, T2 and GCD The transistors T1, T2 of this embodiment described with reference to FIG. 2 and the like can also be used as electrostatic protection transistors. For example, it can also be used as an electrostatic protection transistor which is a gate control device.

  This will be described with reference to FIGS. 8A, 8B, and 8C. Since the transistors T1 and T2 can be considered similarly, only the transistor T1 is shown.

  First, FIG. 8A shows an example of a gate control device (GCD). The transistor TGC is a gate control device, and is provided between the wiring from the terminal G1 and the ground terminal VSS, and the ground voltage from the ground terminal is input to the gate. For example, when a pulse having a voltage lower than the ground voltage is applied to the terminal G1, a pulse voltage is applied between the gate and the source (or drain), and the transistor TGC is turned on. Since the pulse escapes to the ground via the transistor TGC, it can be avoided that the pulse is applied in the integrated circuit device.

  Next, FIGS. 8B and 8C illustrate the transistor T1 in this embodiment. As described in FIG. 2 and the like, the wiring from the power supply terminal VDDA is connected to the gate of the transistor T1.

  As shown in FIG. 8B, the power supply terminal VDDA is connected to the ground wiring VSF1 on the wiring board 200 in the parallel interface mode. That is, the gate of the transistor T1 is connected to the source (or drain) of the transistor T1 through the wiring VSF1, and has the same connection relationship as that of the gate control device shown in FIG.

  On the other hand, as shown in FIG. 8C, in the high-speed serial interface mode, the power supply terminal VDDA is connected to the power supply wiring VDF on the wiring board 200. In this case, if the power supply voltage of the receiver circuit 42 is supplied to the power supply terminal VDDA, even if a pulse having a voltage lower than the ground voltage is applied to the terminal G1, the pulse is applied in the same manner as the gate control device in FIG. Can escape to the ground. Actually, electrostatic breakdown is likely to occur when mounting on a wiring board. In this case, power is not supplied to the terminals VDDA and VSS, but the voltage of the terminal VDDA is considered to be equal to that of the terminal VSS as compared with a pulse voltage that causes electrostatic breakdown. Then, in this case as well, the pulse can be released to the ground as in the gate control device of FIG.

  As described above, according to this embodiment, the transistors T1 and T2 can also be used as transistors for electrostatic protection. Accordingly, the area of the integrated circuit can be reduced as compared with the case where the transistor for preventing unnecessary electromagnetic radiation is provided separately from the transistor for electrostatic protection.

6). Configuration Example of Input Buffer of I / O Buffer FIGS. 9A and 9B show configuration examples of the input buffer of the I / O buffer. For simplicity, FIGS. 9A and 9B show only input buffers applied to the I / O buffers 62-1, 62-2, 64-1, and 64-2 of the parallel interface circuit 60. FIG. . In the case where the parallel interface circuit 60 only inputs a CMOS level signal, the parallel interface circuit 60 may be configured by an input buffer shown in FIG.

  The parallel interface circuit 60 in FIGS. 9A and 9B includes first and second input buffers BFP and BFM. Signals from terminals DP and DM are input to the input buffers BFP and BFM, respectively. The parallel interface circuit 60 can include an inverter INV to which a voltage from the terminal VDDA is input. Furthermore, the parallel interface circuit 60 can include input buffers BF1 and BF2 to which signals from the terminals G1 and G2 are input. Here, the terminal VDD is a power supply voltage different from the power supply voltage for the receiver circuit 42 supplied from the terminal VDDA. The input buffers BFP, BFM, BF1, BF2, and the inverter INV operate with the power supply voltage supplied from the terminal VDD.

  Specifically, the input buffers BFP and BFM can be configured by AND circuits (logical product circuits). The outputs of the input buffers BFP and BFM are controlled by the output of the inverter INV, and are determined based on the voltage from the terminal VDDA.

  More specifically, as shown in FIG. 9A, in the high-speed serial interface mode, the power supply voltage for the receiver circuit 42 is supplied to the terminal VDDA, and the inverter INV has a logic level (L) on the low voltage side. Is output. Therefore, the input buffers BFP and BFM output a signal having a logic level (L. In a broad sense, a fixed level) on the low voltage side. Since the terminals G1 and G2 are fixed to the ground voltage by the guard wiring, the outputs of the input buffers BF1 and BF2 are also fixed to the logic level on the low voltage side.

  On the other hand, as shown in FIG. 9B, in the parallel interface mode, the power supply for the receiver circuit 42 is not required, and therefore the ground voltage is supplied to the terminal VDDA. In this case, since the inverter INV outputs the logic level (H) on the high voltage side, the input buffers BFP and BFM buffer and output CMOS level signals input via the terminals DP and DM, respectively. In the parallel interface mode, since CMOS level signals (first and second parallel interface signals) are also input to the terminals G1 and G2, the input buffers BF1 and BF2 are also input via the terminals G1 and G2, respectively. A CMOS level signal is buffered and output.

  By the way, in this embodiment, terminals are shared by the high-speed serial interface and the parallel interface. In this case, in the high-speed serial interface mode, there is a problem that the input buffer of the parallel interface circuit buffers the high-speed serial signal, resulting in an increase in current consumption.

  In this regard, in this embodiment, since the input buffer outputs a fixed voltage in the high-speed serial interface mode based on the voltage supplied to the terminal VDDA, an increase in current consumption can be prevented. That is, it is possible to prevent the buffered high-frequency signal from being input to the logic circuit at the subsequent stage of the parallel interface circuit and consuming current in the logic circuit that should not be used in the high-speed serial interface mode. Furthermore, by using the power supply voltage for the receiver circuit 42 for this control, interface switching is realized without providing a new control terminal or control signal.

7). High Speed Serial Interface Circuit FIG. 10 shows a detailed configuration example of the high speed serial interface circuit 40. The high-speed serial interface circuit 40 includes a physical layer circuit 50 and a logic circuit 70.

  The physical layer circuit 50 (receiver) is a circuit for receiving data (packets) and clocks using differential signals (differential data signals and differential clock signals). Specifically, data or the like is received from a differential signal line of a current-driven or voltage-driven serial bus. The physical layer circuit 50 can include a data receiver circuit 52, a clock receiver circuit 54, and the like. The data receiver circuit 52 and the clock receiver circuit 54 correspond to the receiver circuit 42 of the present embodiment. The physical layer circuit 50 can also include a transmitter circuit, and in that case, data and clocks can be transmitted.

  The logic circuit 70 performs interface processing between the high-speed serial interface circuit 40 and the internal circuit of the driver. Specifically, the logic circuit 70 can include a sampling circuit 72 and a serial / parallel conversion circuit 74. The sampling circuit 72 samples the data signal from the data receiver circuit 52 with the clock from the clock receiver circuit 54 to generate serial data. The serial / parallel conversion circuit 74 converts the serial data into parallel data and outputs the parallel data to the internal circuit of the driver. The logic circuit 70 can also include a link controller for performing processing on the link layer, which is the upper layer of the physical layer.

8). Detailed Configuration Example of Electro-Optical Device FIG. 11 shows a detailed configuration example of the electro-optical device of the present embodiment. FIG. 11 illustrates a case where the present embodiment is applied to a liquid crystal display device. However, this embodiment can also be applied to a display device using a light emitting element such as an EL element.

  A liquid crystal display device (electro-optical device, display device) of this embodiment shown in FIG. 11 includes a liquid crystal panel 400 (electro-optical panel, display panel), a data driver 20 (data line driving circuit), and a scanning driver 30 (scanning line driving). Circuit, gate driver), power supply circuit 80, and display controller 150. Here, the interface switching circuit in the present embodiment shown in FIG. Note that it is not necessary to include all these circuit blocks in the present embodiment, and some of the circuit blocks may be omitted.

  The liquid crystal panel 400 is a liquid crystal panel formed on, for example, an active matrix substrate (for example, a glass substrate). The active matrix substrate has a position corresponding to the intersection of the gate line GK (1 ≦ K ≦ M, K and M are natural numbers) and the data lines SRL, SGL, and SBL (1 ≦ L ≦ N, L and N are natural numbers). In addition, thin film transistors TFTKL-R, TFTKL-G, and TFTKL-B are provided.

  For example, the gate of the TFTKL-R is connected to the gate line GK, and the source and drain of the TFTKL-R are connected to the data line SRL and the pixel electrode PEKL-R. A liquid crystal (electro-optical material) is sandwiched between the pixel electrode PEKL-R and the counter electrode CE (common electrode) to form a liquid crystal capacitor CLKL-R and an auxiliary capacitor CSKL-R.

  The active matrix substrate is provided with data voltage supply lines S1 to SN, and a demultiplexer is provided corresponding to S1 to SN. The demultiplexer DMUXL divides and supplies the grayscale voltage supplied to the source voltage supply line SL to the data lines SRL, SGL, and SBL based on the multiplex control signal from the data driver 20.

  The voltage level of the common electrode voltage VCOM applied to the common electrode CE is generated by a common electrode voltage generation circuit included in the power supply circuit 80. For example, the counter electrode CE is formed on one surface on the counter substrate.

  The data driver 20 drives the data voltage supply lines S1 to SN of the liquid crystal panel 400 based on the gradation data. As described above, since the separation control is performed by the demultiplexer, the data driver 20 can drive the data lines SR1 to SRN, SG1 to SGN, and SB1 to SBN. On the other hand, the scanning driver 30 scans (sequentially drives) the scanning lines G1 to GM of the liquid crystal panel 400.

  The display controller 150 outputs control signals to the data driver 20, the scan driver 30, and the power supply circuit 80 to the interface circuit 90 according to the contents set by a host such as a central processing unit (CPU) (not shown). .

  The interface circuit 90 interfaces the control signal input from the display controller 150 to the data driver 20, the scan driver 30, and the power supply circuit 80.

  The power supply circuit 80 generates various voltage levels (grayscale voltages) necessary for driving the liquid crystal panel 400 and the voltage level of the counter electrode voltage VCOM of the counter electrode CE based on a reference voltage supplied from the outside.

  In FIG. 11, the liquid crystal display device includes the display controller 150, but the display controller 150 may be provided outside the liquid crystal display device. Further, some or all of the data driver 20, the scan driver 30, the power supply circuit 80, and the display controller 150 may be formed on the liquid crystal panel 400.

8.1. Data Driver FIG. 12 shows a configuration example of the data driver 20 of FIG. The data driver 20 includes a shift register 22, line latches 24 and 26, a multiplexing circuit 28, a reference voltage generation circuit 38, a DAC 32 (data voltage generation circuit), a data line drive circuit 34, and a multiplex drive control unit 36.

  The shift register 22 sequentially shifts the enable input / output signal EIO to adjacent flip-flops in synchronization with the clock signal CLK.

  The line latch 24 receives gradation data DIO from the display controller 150 in units of 18 bits (6 bits (gradation data) × 3 (RGB colors)), for example. The line latch 24 latches the gradation data DIO in synchronization with the EIO that is sequentially shifted by the shift register 22.

  The line latch 26 latches the grayscale data of one horizontal scan unit latched by the line latch 24 in synchronization with the horizontal synchronization signal LP supplied from the display controller 150.

  The multiplexing circuit 28 time-division multiplexes the gradation data for the three data lines latched corresponding to each data line in the line latch 26.

  The multiplex drive control unit 36 generates a multiplex control signal that defines the time division timing of the data voltage supply line, and activates the multiplex control signals RSEL, GSEL, and BSEL in order within one horizontal scanning period. The multiplexing circuit 28 multiplexes based on the multiplex control signal so as to supply the gradation voltage to the data voltage supply line in a time division manner. The multiplex control signal is also supplied to the demultiplexer of the liquid crystal panel 400.

  The reference voltage generation circuit 38 generates, for example, 64 types of reference voltages. The 64 types of reference voltages generated by the reference voltage generation circuit 38 are supplied to the DAC 32.

  The DAC 32 selects one of the reference voltages from the reference voltage generation circuit 38 based on the digital gradation data from the multiplexing circuit 28, and applies an analog data voltage corresponding to the digital gradation data to each data line. Output to.

  In the data line drive circuit 34, a voltage follower-connected operational amplifier OPC provided for each data line buffers the data voltage from the DAC 32 and outputs the data voltage to the data line to drive the data line.

  In FIG. 12, the digital gradation data is converted from digital to analog and output to the data line via the data line driving circuit 34. However, the analog video signal is sampled and held. A configuration in which data is output to the data line via the data line driving circuit 34 can also be adopted.

9. Electronic device As an electronic device configured using the above-described liquid crystal display device, for example, there is a projector (projection display device). FIG. 13 is a block diagram showing a configuration example of a projector to which the liquid crystal display device according to this embodiment is applied.

  The projector in FIG. 13 includes a display information output source 710, a display information processing circuit 720, a driver 100 (integrated circuit device), a liquid crystal panel 400, a clock generation circuit 750, and a power supply circuit 760. The display information output source 710 includes a ROM (Read Only Memory) and a RAM (Random Access Memory), a memory such as an optical disk device, a tuning circuit that tunes and outputs an image signal, and the like. Based on this, display information such as an image signal in a predetermined format is output to the display information processing circuit 720. The display information processing circuit 720 can include an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The driver 100 includes a scanning driver and a data driver, and drives the liquid crystal panel 400. The power supply circuit 760 supplies power to each circuit described above.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (liquid crystal display devices, drivers) described at least once together with different terms (electro-optical devices, integrated circuit devices, electro-optical panels, low-potential side power supply voltages, etc.) in a broader sense or the same meaning , Liquid crystal panel, ground, etc.) can be replaced by the different terms in any part of the specification or drawings. The configuration and operation of the high-speed serial interface circuit, parallel interface circuit, data driver, scanning driver, power supply circuit, driver, electro-optical device, electronic device, etc. are not limited to those described in this embodiment, and various modifications are possible. Implementation is possible.

Configuration example of electro-optical device according to this embodiment Configuration example of integrated circuit device of this embodiment 3A and 3B show a first configuration example of the I / O buffer. Second configuration example of I / O buffer Configuration example of output buffer of I / O buffer 6A and 6B are diagrams illustrating operation of the transistor. Illustration of serial bus FIG. 8A, FIG. 8B, and FIG. 8C are configuration examples of transistors that are also used as gate control devices. FIGS. 9A and 9B are configuration examples of the input buffer of the I / O buffer. High-speed serial interface circuit configuration example Detailed configuration example of the electro-optical device of this embodiment Data driver configuration example Configuration example of electronic device of this embodiment

Explanation of symbols

40 high-speed serial interface circuit, 42 receiver circuit,
44 differential amplifier, 60 parallel interface circuit,
62-1, 62-2, 64-1, 64-2 I / O buffer,
100 integrated circuit device, 200 wiring board, 400 electro-optical panel,
DPF, DMF 1st, 2nd wiring, GF1, GF2 1st, 2nd guard wiring,
VDF first power supply wiring, VSF1 second power supply wiring,
DP, DM first and second terminals, G1, G2 first and second guard terminals,
VDDA first power supply terminal, VSS second power supply terminal,
T1, T2 first and second transistors,
GL1, GL2 Wiring from the first and second guard terminals, R termination resistance,
VSL wiring from second power supply terminal, TGC transistor for electrostatic protection,
BFP, BFM First and second input buffers, INV inverter

Claims (14)

A high-speed serial interface circuit including a receiver circuit for receiving a differential signal via a serial bus;
First and second guard terminals for preventing radiation;
A first terminal that is disposed between the first and second guard terminals and to which a first signal constituting the differential signal is input;
A second terminal disposed between the first and second guard terminals and to which a second signal constituting the differential signal is input;
A first power supply terminal to which a power supply voltage on the high voltage side for the receiver circuit is supplied;
A second power supply terminal to which a power supply voltage on the low voltage side is supplied;
A first switch element provided between the wiring from the first guard terminal and the wiring from the second power supply terminal;
A second switch element provided between the wiring from the second guard terminal and the wiring from the second power supply terminal;
A first I / O buffer for inputting / outputting a parallel interface signal via the first guard terminal;
A second I / O buffer for inputting / outputting a parallel interface signal via the second guard terminal;
Including
In the high-speed serial interface mode, the first and second switch elements are turned on, and the outputs of the first and second I / O buffers are set to a low voltage side level or a high impedance state. Integrated circuit device. In claim 1,
The first and second I / O buffers are:
An input buffer, an output buffer, and a logic circuit;
The logic circuit is:
Provided in the previous stage of the output buffer, based on the high-voltage side power supply voltage from the first power supply terminal in the high-speed serial interface mode, to output a fixed level signal,
The output buffer is
The integrated circuit device, wherein the low voltage side level is output when the fixed level signal of the logic circuit is input. In claim 1,
The first and second I / O buffers are:
An input buffer, an output buffer, and a logic circuit;
The logic circuit is:
Based on the power supply voltage on the high voltage side in the high-speed serial interface mode, a fixed level signal is output,
The output of the output buffer is set to the high impedance state based on the fixed level signal of the logic circuit. In any one of Claims 1 thru | or 3,
Including a parallel interface circuit,
In the parallel interface mode, the first and second switch elements are turned off, and the parallel interface circuit includes a plurality of parallel interfaces via the first and second terminals and the first and second guard terminals. An integrated circuit device, wherein a signal is input. In claim 4,
The first switch element includes:
Constituted by a first transistor;
The second switch element is
Constituted by a second transistor;
2. The integrated circuit device according to claim 1, wherein the power supply voltage on the high voltage side from the first power supply terminal is input to the gates of the first and second transistors. In claim 5,
An integrated circuit device, wherein a termination resistor is provided between the first and second terminals, and an on-resistance of the first and second transistors is equal to or less than a resistance value of the termination resistor. In claim 5 or 6,
The integrated circuit device, wherein the first and second transistors are also used as electrostatic protection transistors. In claim 7,
The transistor for electrostatic protection is
An integrated circuit device which is a gate control device. In any of claims 4 to 8,
A first input buffer to which a first parallel interface signal of the plurality of parallel interface signals is input from the first terminal;
A second input buffer to which a second parallel interface signal of the plurality of parallel interface signals is input from the second terminal;
Including
The first and second input buffers are:
In the high-speed serial interface mode, an integrated circuit device outputs a signal of a fixed level based on the power supply voltage on the high voltage side supplied to the first power supply terminal. In claim 9,
Including an inverter that operates at a power supply voltage different from the power supply voltage on the high voltage side,
In the inverter,
The high-voltage power supply voltage supplied to the first power supply terminal is input,
The first and second input buffers are:
An integrated circuit device controlled by the output of the inverter. In any of claims 5 to 10,
An integrated circuit device, wherein a power supply voltage on a low voltage side is supplied to the first power supply terminal in a parallel interface mode. An integrated circuit device according to any one of claims 1 to 11,
An electro-optic panel;
A wiring board;
Including
The wiring board is
A first wiring connected to the first terminal; a second wiring connected to the second terminal; a first guard wiring connected to the first guard terminal; A second guard wiring connected to the second guard terminal; a first power supply wiring connected to the first power supply terminal; and a second power supply wiring connected to the second power supply terminal. Have
The first and second wirings are
An electro-optical device, wherein the electro-optical device is wired between the first and second guard wires. In claim 12,
The second power supply wiring is
An electro-optical device having a wiring resistance smaller than that of the first and second guard wirings.   An electronic apparatus comprising the electro-optical device according to claim 12.

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