JP4433870B2 - Clamp circuit - Google Patents

Description

  The present invention relates to a clamp circuit, and more particularly to a clamp circuit that clamps a voltage between the terminals to a constant voltage by a transistor having an emitter and a collector connected between two terminals.

  2. Description of the Related Art Conventionally, an input terminal is provided with a PNP transistor having an emitter connected to an input terminal of an internal circuit and a collector grounded, and a resistance voltage dividing circuit for applying a constant voltage to the base of the transistor, and into which an input current flows. Has been proposed (see, for example, Patent Document 1).

  A clamp circuit in which the PNP transistor in the technique of Patent Document 1 is replaced with two PNP transistors connected in Darlington connection has also been proposed (see, for example, FIG. 3 of Patent Document 2).

In addition, a clamp circuit in which an NPN transistor driven by a PNP transistor in the technique of Patent Document 1 is added has also been proposed (see, for example, FIGS. 1 and 4 of Patent Document 2).
Japanese Patent Laid-Open No. 2000-209085 (pages 2 to 3 in FIG. 1) Japanese Patent Laid-Open No. 5-335491 (pages 2 to 3 and FIGS. 1 to 4)

  Patent Document 1 only describes clamping the input terminal (input side) of the internal circuit to a constant voltage, but the technique of Patent Document 1 clamps the output terminal (output side) of the internal circuit to a constant voltage. Can also be used.

FIG. 10 is a circuit diagram showing a clamp circuit 50 configured by extracting only the main part from the clamp circuit of Patent Document 1. In FIG.
The clamp circuit 50 includes a PNP transistor T1, a first terminal A, a second terminal B, a bias resistor R1, and a constant voltage source P.

The transistor T1 constitutes a collector grounding circuit, its emitter is connected to the terminal A, its collector is connected to the terminal B and grounded, and its base is grounded via the resistor R1.
The constant voltage source P generates a constant voltage Vf, and the constant voltage Vf is supplied to the base of the transistor T1 and the resistor R1.
The clamp circuit 50 clamps the voltage at the terminal A to a constant voltage (clamp voltage) Vk.

  That is, in the clamp circuit 50, when the voltage at the terminal A rises above the voltage Vk (= Vf + VBE) obtained by adding the base-emitter voltage VBE of the transistor T1 to the constant voltage Vf, the transistor T1 is turned on. The voltage at the terminal A is lowered by drawing the collector current I2 to the ground side (terminal B) through the terminal A, and the voltage at the terminal A is clamped to the constant voltage Vk.

Here, if the terminal B is connected to the ground terminal of the internal circuit (not shown) connected to the clamp circuit, and the terminal A is connected to the input terminal of the internal circuit, the clamp circuit 50 is connected to the input terminal (input side of the internal circuit). ) Can be clamped to a constant voltage.
Further, if the terminal B is connected to the ground terminal of the internal circuit and the terminal A is connected to the output terminal of the internal circuit, the clamp circuit 50 can clamp the output terminal (output side) of the internal circuit to a constant voltage.

The technique shown in FIG. 1 of Patent Document 1 is provided with a resistor voltage dividing circuit configured by connecting another resistor in series to the resistor R1, and a voltage obtained by dividing the constant voltage Vf by the resistor voltage dividing circuit is used as the transistor T1. The voltage is applied to the base.
In the technique shown in FIG. 3 of Patent Document 2, the transistor T1 is replaced with two PNP transistors connected in Darlington, and a resistance voltage dividing circuit similar to the technique shown in FIG. 1 of Patent Document 1 is provided. It is.
In the technique shown in FIG. 4 of Patent Document 2, an NPN transistor driven by a PNP transistor T1 is added, a load resistance is provided between the collector of the transistor T1 and the ground, and the base voltage of the NPN transistor is generated by the load resistance. Thus, a bias voltage is applied and a resistance voltage dividing circuit similar to the technique shown in FIG.

In the clamp circuit 50 shown in FIG. 10, the voltage of the terminal A is clamped to the constant voltage Vk by drawing the collector current I2 from the terminal A through the transistor T1 to the ground side (terminal B). Is determined by the current drive capability (maximum collector current) of the transistor T1.
The collector current I2 is a value obtained by multiplying the base current Ib of the transistor T1 by the DC current amplification factor β (hFE) of the transistor T1 (I2 = Ib × β).
Therefore, in order to increase the collector current I2, it is necessary to increase the base current Ib.

In order to increase the collector current I2, the transistor T1 having a large maximum collector current must be used. However, the base current Ib necessary to turn on the transistor T1 having a large maximum collector current is large.
In order to increase the base current Ib, the current I1 flowing through the resistor R1 must be increased. However, in order to increase the current I1, the resistance value of the resistor R1 needs to be reduced.

However, when the resistance value of the resistor R1 is reduced, a large current I1 flows through the resistor R1 even when the transistor T1 is turned off and the clamp circuit 50 is not operated, and the current I1 becomes a dark current.
As a result, the power consumed by the resistor R1 is increased by the dark current I1 that flows when the clamp circuit 50 is not operating, and the power consumption of the clamp circuit 50 is also increased.

That is, the collector current I2 is limited by the base current Ib, and the base current Ib is limited by the current I1 flowing through the resistor R1.
Therefore, when the transistor T1 having a large maximum collector current is used to increase the current drive capability of the clamp circuit 50, the dark current I1 flowing through the resistor R1 increases when the clamp circuit 50 stops operating, and when the clamp circuit 50 stops operating. There is a problem that power consumption increases.

Incidentally, in the technique shown in FIG. 3 of Patent Document 2, the transistor T1 is replaced with two PNP transistors connected in Darlington connection.
In the technique shown in FIG. 4 of Patent Document 2, an NPN transistor driven by a PNP transistor T1 is added.
Therefore, according to these techniques, although the dark current can be reduced as compared with the clamp circuit 50, the dark current is still increased when the current driving capability of the clamp circuit is increased.

  The present invention has been made to solve the above problem, and an object of the present invention is to provide a clamp circuit capable of reducing power consumption by reducing dark current that flows when the clamp circuit is not operating. Is to provide.

(Claim 1: corresponds to the first embodiment)
The invention according to claim 1 is a clamp circuit that clamps the voltage between the first terminal and the second terminal to a constant voltage, the emitter being connected to the first terminal, and from the first terminal to the second terminal. A PNP transistor through which a collector current flows, a resistor connected between the base of the transistor and a second terminal, a constant voltage source for supplying a constant voltage to the base of the transistor and the resistor, and a collector current of the transistor A technical feature is that it includes a current mirror circuit for supplying a corresponding current from the base of the transistor to the second terminal.

(Claim 2: corresponds to the second embodiment)
The invention according to claim 2 is a clamp circuit that clamps the voltage between the first terminal and the second terminal to a constant voltage, the emitter being connected to the first terminal, and from the first terminal to the second terminal. A first PNP transistor for flowing a collector current; a second PNP transistor connected to the first PNP transistor by Darlington; a resistor connected between a base and a second terminal of the second PNP transistor; a base of the second PNP transistor; Technical features comprising: a constant voltage source for supplying a constant voltage to the resistor; and a current mirror circuit for causing a current corresponding to the collector current of the first PNP transistor to flow from the base of the second PNP transistor to the second terminal. And

(Claim 3: corresponds to the third embodiment and the fourth embodiment)
The invention according to claim 3 is a clamp circuit that clamps the voltage between the first terminal and the second terminal to a constant voltage, the collector being connected to the first terminal, and from the first terminal to the second terminal. An NPN transistor for flowing a collector current; an emitter connected to a first terminal; the PNP transistor driving the NPN transistor; a resistor connected between a base of the PNP transistor and a second terminal; Technical features comprising: a constant voltage source for supplying a constant voltage to the base and the resistor; and a current mirror circuit for causing a current corresponding to the collector current of the NPN transistor to flow from the base of the PNP transistor to the second terminal. And

(Claim 1)
In the first aspect of the invention, when the voltage at the first terminal rises above the voltage obtained by adding the base-emitter voltage (VBE) of the transistor to the constant voltage of the constant voltage source, the transistor is turned on, and the transistor is turned on from the first terminal. The voltage at the first terminal is lowered by drawing the collector current to the second terminal through the first terminal, and the voltage at the first terminal is made constant (the constant voltage of the constant voltage source plus the voltage between the base and emitter of the transistor). Clamp.

If the second terminal is connected to the ground terminal of the internal circuit connected to the clamp circuit of claim 1 and the first terminal is connected to the input terminal of the internal circuit, the clamp circuit of claim 1 The input terminal (input side) of the circuit can be clamped to a constant voltage.
Further, if the second terminal B is connected to the ground terminal of the internal circuit and the first terminal is connected to the output terminal of the internal circuit, the clamp circuit of claim 1 keeps the output terminal (output side) of the internal circuit constant. Can be clamped to voltage.

In the clamp circuit according to claim 1, the collector current is drawn from the first terminal to the second terminal through the transistor to clamp the voltage of the first terminal to a constant voltage. Therefore, the maximum value of the collector current is the current driving capability of the transistor. (Maximum collector current).
The collector current is a value obtained by multiplying the base current of the transistor by the DC current amplification factor β (hFE) of the transistor.

Therefore, it is necessary to increase the base current to increase the collector current.
In order to increase the collector current, a transistor having a large maximum collector current must be used. However, a base current required to turn on a transistor having a large maximum collector current is large.
Here, since the current mirror circuit is provided, a current corresponding to the collector current of the transistor flows from the base of the transistor to the second terminal.

The current mirror circuit does not operate when the transistor is off. Therefore, it is necessary to flow a base current in order to turn on the transistor. To flow the base current, it is sufficient to flow a current from the constant voltage source to the second terminal via a resistor.
When the transistor is turned on and a collector current flows, the current mirror circuit operates, and a current corresponding to the collector current of the transistor flows from the base of the transistor to the second terminal.

That is, in the clamp circuit according to the first aspect, the base current is generated by the current flowing through the resistor when the transistor is off, and the base current is generated by the collector current when the transistor is on.
In other words, the current flowing through the resistor is necessary only when the transistor is turned on (started up), and is unnecessary after the transistor is turned on (after start-up).

Here, in order to increase the base current when the transistor is on, it is only necessary to increase the current flowing from the base of the transistor to the second terminal by the current mirror circuit.
The current that flows from the base of the transistor to the second terminal by the current mirror circuit corresponds to the collector current of the transistor, and the current that flows from the base to the second terminal increases as the collector current increases.

Therefore, in the clamp circuit according to claim 1, the current flowing from the constant voltage source to the second terminal via the resistor is a minimum current value necessary for turning on the transistor, and the resistance value of the resistor is Can be bigger.
When the resistance value of the resistor is increased, the dark current flowing through the resistor can be reduced when the transistor is turned off and the clamp circuit is not operated.
As a result, the power consumed by the resistor is reduced by the dark current that flows when the clamp circuit of claim 1 is not operating, and the power consumption of the clamp circuit is also reduced.

In other words, in the clamp circuit according to the first aspect, the collector current of the transistor is limited by the base current, and the base current is limited by the current flowing from the base of the transistor to the second terminal by the current mirror circuit. It is not limited by the flowing current.
Therefore, even when a transistor having a large maximum collector current is used to increase the current drive capability of the clamp circuit of claim 1, it is possible to reduce the dark current flowing through the resistor when the clamp circuit is stopped, and when the clamp circuit is stopped. Power consumption can be reduced.

(Claim 2)
According to a second aspect of the present invention, when the voltage at the first terminal rises above the voltage obtained by adding the base-emitter voltage (VBE) of each of the first PNP transistor and the second PNP transistor to the constant voltage of the constant voltage source, the first PNP transistor And the second PNP transistor is turned on, and the collector current is drawn from the first terminal to the second terminal through the first PNP transistor to lower the voltage at the first terminal, and the voltage at the first terminal is kept constant (the constant voltage source Clamped to a constant voltage plus the base-emitter voltage of each transistor).

In other words, the clamp circuit of claim 2 is obtained by replacing the PNP transistor of the clamp circuit of claim 1 with two transistors (first PNP transistor and second PNP transistor) connected in Darlington connection.
3. The clamp circuit according to claim 2, wherein the collector current of the first PNP transistor is a value obtained by multiplying the base current of the second PNP transistor by the respective DC current amplification factors of the second PNP transistor and the first PNP transistor.
On the other hand, in the clamp circuit according to claim 1, the collector current of the transistor is a value obtained by multiplying the base current of the transistor by a DC current amplification factor of the transistor.

Therefore, when the direct current amplification factors of the first PNP transistor of claim 2 and the transistor of claim 1 are equal, the clamp circuit of claim 2 obtains the same collector current as compared to the clamp circuit of claim 1. Therefore, the base current required for this can be reduced by the amount divided by the direct current amplification factor of the second PNP transistor.
Therefore, according to the clamp circuit of the second aspect, it is possible to reduce the current flowing through the resistor as much as the base current is smaller than that of the clamp circuit of the first aspect, and to increase the resistance value of the resistor. Thus, the above-mentioned action / effect of the invention of claim 1 can be further enhanced.

(Claim 3)
According to the invention of claim 3, when the voltage at the first terminal rises above the voltage obtained by adding the base-emitter voltage (VBE) of the PNP transistor to the constant voltage of the constant voltage source, the NPN transistor is turned on after the PNP transistor is turned on. The voltage at the first terminal is lowered by drawing the collector current from the first terminal to the second terminal through the NPN transistor, and the voltage at the first terminal is lowered to a constant voltage (the constant voltage of the PNP transistor・ Clamp to the voltage of the emitter voltage.

Here, the NPN transistor is driven by the PNP transistor.
Therefore, in the clamp circuit of claim 3, the collector current of the NPN transistor is a value obtained by multiplying the base current of the PNP transistor by the direct current amplification factor of the PNP transistor and the direct current amplification factor of the NPN transistor.
On the other hand, in the clamp circuit according to claim 1, the collector current of the transistor is a value obtained by multiplying the base current of the transistor by a DC current amplification factor of the transistor.

Therefore, according to the clamp circuit of the third aspect, the base current required to obtain the same collector current can be reduced as compared with the clamp circuit of the first aspect.
Therefore, according to the clamp circuit of claim 3, it is possible to reduce the current flowing through the resistor as much as the base current is smaller than that of the clamp circuit of claim 1, and to increase the resistance value of the resistor. Thus, the above-mentioned action / effect of the invention of claim 1 can be further enhanced.

  Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. In each embodiment, the same constituent members as those in the prior art shown in FIG. Moreover, in each embodiment, the code | symbol is equal about the component same as 1st Embodiment, and the description is abbreviate | omitted.

(First embodiment)
FIG. 1 is a circuit diagram showing a clamp circuit 10 according to the first embodiment.
The clamp circuit 10 includes a PNP transistor T1, a first terminal A, a second terminal B, a bias resistor R1, a constant voltage source P, and a current mirror circuit CM.
That is, the first embodiment is different from the prior art clamp circuit 50 only in that a current mirror circuit CM is provided.

The transistor T1 constitutes a collector ground circuit, its emitter is connected to the terminal A, its collector is connected to the terminal B through the NPN transistor T2, and grounded, and its base is grounded through the resistor R1. .
The constant voltage source P generates a constant voltage Vf, and the constant voltage Vf is supplied to the base of the transistor T1 and the resistor R1.

The current mirror circuit CM is a Wideler type current mirror circuit composed of NPN transistors T2 and T3.
The emitters of the transistors T2 and T3 are grounded, and the base of the input side transistor T2 is coupled (connected) to the base of the output side transistor T3.
Note that the DC current gain β (hFE) of each of the transistors T2 and T3 is set to a sufficiently high value.

The input side transistor T2 has a diode connection in which a base and a collector are coupled. The base and collector of the input side transistor T2 are coupled to the collector of the transistor T1.
The collector of output side transistor T3 is coupled to the base of transistor T1.

[Operations and effects of the first embodiment]
According to the clamp circuit 10 of the first embodiment, the following operations and effects can be obtained.

  [1-1] In the clamp circuit 10, when the voltage at the terminal A rises above the voltage Vk (= Vf + VBE) obtained by adding the base-emitter voltage VBE of the transistor T1 to the constant voltage Vf, the transistor T2 is turned on after the transistor T1 is turned on. Is turned on, the collector current I2 is pulled from the terminal A through the transistors T1 and T2 to the ground side (terminal B), the voltage at the terminal A is lowered, and the voltage at the terminal A is set to a constant voltage (clamp voltage) Vk. Clamp.

Here, if the terminal B is connected to the ground terminal of the internal circuit (not shown) connected to the clamp circuit 10 and the terminal A is connected to the input terminal of the internal circuit, the clamp circuit 10 is connected to the input terminal (input) of the internal circuit. Side) can be clamped to a constant voltage.
Further, if the terminal B is connected to the ground terminal of the internal circuit and the terminal A is connected to the output terminal of the internal circuit, the clamp circuit 10 can clamp the output terminal (output side) of the internal circuit to a constant voltage.

[1-2] The clamp circuit 10 clamps the voltage at the terminal A to the constant voltage Vk by drawing the collector current I2 from the terminal A through the transistor T1 to the ground side (terminal B). The value is determined by the current driving capability (maximum collector current) of the transistor T1.
The collector current I2 is a value obtained by multiplying the base current Ib of the transistor T1 by the DC current amplification factor β (hFE) of the transistor T1 (I2 = Ib × β).

Therefore, in order to increase the collector current I2, it is necessary to increase the base current Ib.
In order to increase the collector current I2, the transistor T1 having a large maximum collector current must be used. However, the base current Ib necessary to turn on the transistor T1 having a large maximum collector current is large.

[1-3] Since the transistors T1 and T2 are connected in series, a common collector current I2 flows through the transistors T1 and T2.
In the current mirror circuit CM, the collector current I3 of the output side transistor T3 is equal to the collector current I2 of the input side transistor T2.

[1-4] When the transistor T1 is off, the collector current I2 does not flow through the transistor T2, so the current mirror circuit CM does not operate and the collector current I3 does not flow through the transistor T3.
In order to turn on the transistor T1, it is necessary to flow the base current Ib, and in order to flow the base current Ib, the current I1 may flow through the resistor R1.
When the transistor T1 is turned on and the collector current I2 flows, the collector current I2 also flows through the transistor T2, the current mirror circuit CM operates, and the collector current I3 flows through the transistor T3.

That is, in the clamp circuit 10, the base current Ib is generated by the current I1 flowing through the resistor R1 when the transistor T1 is off, and the base current Ib is generated by the collector current I3 when the transistor T1 is on.
In other words, the current I1 flowing through the resistor R1 is necessary only when the transistor T1 is turned on (started up), and becomes unnecessary after the transistor T1 is turned on (after start-up).

Here, in order to increase the base current Ib when the transistor T1 is turned on, the collector current I3 of the output side transistor T3 may be increased.
The collector current I3 is equal to the collector current I2, and the collector current I3 increases as the collector current I2 increases.

Therefore, in the clamp circuit 10, the current I1 flowing through the resistor R1 can be a minimum current value necessary for turning on the transistor T1, and the resistance value of the resistor R1 can be increased.
When the resistance value of the resistor R1 is increased, the dark current I1 flowing through the resistor R1 can be reduced when the transistor T1 is turned off and the clamp circuit 50 is not operated.
As a result, the power consumed by the resistor R1 is reduced by the dark current I1 that flows when the clamp circuit 10 is not operating, and the power consumption of the clamp circuit 10 is also reduced.

That is, in the clamp circuit 10, since the collector current I2 is limited by the base current Ib and the base current Ib is limited by the collector current I3, the base current Ib is not limited by the current I1 flowing through the resistor R1, and each collector current I2 , I3 are equalized by the current mirror circuit CM.
Therefore, even when the transistor T1 having a large maximum collector current is used to increase the current drive capability of the clamp circuit 10, the dark current I1 flowing through the resistor R1 when the operation of the clamp circuit 10 is stopped can be reduced, and the operation of the clamp circuit 10 is improved. Power consumption at the time of a stop can be reduced.

[Modification of First Embodiment]
Next, modified examples in which the configuration of the current mirror circuit CM in the first embodiment is partially changed will be described with reference to the drawings. In each modification, the only difference from the first embodiment is the configuration of the current mirror circuit CM, and the other constituent members have the same reference numerals as those of the first embodiment.

[First Modification]
FIG. 2 is a circuit diagram showing an electrical configuration of the clamp circuit 10 in the first modification.
The first modification differs from the current mirror circuit CM of the first embodiment in that the diode-connected input side transistor T2 is replaced with a diode D1 as shown in FIG.

That is, the current mirror circuit CM of the first modification is a wideler type simplified (simple mirror) circuit.
According to the first modification, the same effects as those of the first embodiment can be obtained, and the component cost can be reduced by replacing the input side transistor T2 with the diode D1.

[Second Modification]
FIG. 3 is a circuit diagram showing an electrical configuration of the clamp circuit 10 in the second modification.
The second modification differs from the current mirror circuit CM of the first embodiment in that the emitters of the transistors T2 and T3 are grounded via the emitter resistors R2 and R3, respectively. The resistance values of the resistors R2 and R3 are the same.

In other words, the current mirror circuit CM of the second modification is a wideler type emitter resistance additional circuit.
According to the second modification, the collector currents I2 and I3 of the transistors T2 and T3 can be made equal to each other with high accuracy and the stability of the current mirror circuit CM can be improved as compared with the first embodiment. Can do.

[Third Modification]
FIG. 4 is a circuit diagram showing an electrical configuration of the clamp circuit 10 in the third modification.
The third modification is different from the current mirror circuit CM of the first embodiment in that an NPN transistor T4 is added.
The base of the transistor T4 is coupled to the collector of the input-side transistor T2, the emitter of the transistor T4 is coupled to the bases of the transistors T2 and T3, and the constant voltage Vf of the constant voltage source P is supplied to the collector of the transistor T4. . That is, the base currents of the transistors T2 and T3 are supplied from the transistor T4.

That is, the current mirror circuit CM of the third modification is a base current compensation type circuit.
According to the third modification, the collector currents I2 and I3 of the transistors T2 and T3 can be made equal to each other with high accuracy as compared with the first embodiment. However, the condition is that the influence of the base current of the transistor T4 on the collector current of the input-side transistor T2 is so small that it can be ignored.

[Fourth Modification]
FIG. 5 is a circuit diagram showing an electrical configuration of the clamp circuit 10 in the fourth modification.
The fourth modification differs from the current mirror circuit CM of the first embodiment in that the diode connection of the input side transistor T2 is released, the output side transistor T3 is diode-connected, and the NPN transistor T5 is added. It is.

  The base of transistor T5 is coupled to the collector of input side transistor T2, the emitter of transistor T5 is coupled to the collector of output side transistor T3, and the collector of transistor T5 is coupled to the base of transistor T1.

That is, the current mirror circuit CM of the fourth modification is a Wilson circuit.
According to the fourth modification, the collector currents Ic of the transistors T2 and T3 can be made equal to each other with higher accuracy than in the first embodiment.

[Fifth Modification]
FIG. 6 is a circuit diagram showing an electrical configuration of the clamp circuit 10 in the fifth modification.
The fifth modification differs from the current mirror circuit CM of the fourth modification in that a diode-connected NPN transistor T6 is added.

  The collector of the transistor T6 is coupled to the collector of the transistor T1, the emitter of the transistor T6 is coupled to the collector of the input side transistor T2, and the bases of the transistors T6 and T5 are coupled and connected to the transistor T1.

That is, the current mirror circuit CM of the fifth modification is a high-precision Wilson circuit.
According to the fifth modification, since the operating conditions of the transistors T2 and T3 are the same as in the fourth modification, the collector currents I2 and I3 of the transistors T2 and T3 can be equalized with higher accuracy. it can.

(Second Embodiment)
FIG. 7 is a circuit diagram showing the clamp circuit 20 of the second embodiment.
The clamp circuit 20 includes a first PNP transistor T1, a second PNP transistor T7, a first terminal A, a second terminal B, a bias resistor R1, a constant voltage source P, and a current mirror circuit CM.
That is, the second embodiment is different from the clamp circuit 10 of the first embodiment in that a PNP transistor T7 is added and the PNP transistor T1 is replaced with two Darlington-connected PNP transistors T1 and T7. Only.
That is, in the second embodiment, the technique shown in FIG. 3 of Patent Document 2 is applied to the first embodiment.

[Operation and Effect of Second Embodiment]
According to the second embodiment, in addition to the same operations and effects as in the first embodiment, the following operations and effects can be obtained.

  [2-1] In the clamp circuit 20, the voltage at the terminal A is equal to or higher than the voltage Vk (= Vf + VBEa + VBEb) obtained by adding the base-emitter voltage VBEa of the transistor T7 and the base-emitter voltage VBEb of the transistor T1 to the constant voltage Vf. When rising, the transistor T2 is turned on after the transistors T1 and T7 are turned on, and the voltage at the terminal A is lowered by drawing the collector current I2 from the terminal A to the ground side (terminal B) via the transistors T1 and T2. The voltage at terminal A is clamped to a constant voltage Vk.

[2-2] In the clamp circuit 20, the collector current I2 of the transistor T1 is a value obtained by multiplying the base current Ib of the transistor T7 by the DC current gain βa of the transistor T7 and the DC current gain βb of the transistor T1 ( I2 = Ib × βa × βb).
On the other hand, in the clamp circuit 10, the collector current I2 of the transistor T1 has a value obtained by multiplying the base current Ib of the transistor T1 by the DC current amplification factor βb of the transistor T1 (I2 = Ib × βb).

Therefore, according to the clamp circuit 20, the base current Ib necessary for obtaining the same collector current I2 can be made smaller than the clamp circuit 10 by dividing the base current Ib by the DC current amplification factor βa (that is, the base current Ib is 1). / Βa).
Therefore, according to the clamp circuit 20, the current I1 flowing through the resistor R1 can be reduced by the amount that the base current Ib is smaller than that of the clamp circuit 10, and the resistance value of the resistor R1 can be increased. The action and effect of [1-4] of the first embodiment can be further enhanced.

(Third embodiment)
FIG. 8 is a circuit diagram showing the clamp circuit 30 of the third embodiment.
The clamp circuit 30 includes a PNP transistor T1, a first terminal A, a second terminal B, bias resistors R1 and R4, a constant voltage source P, a current mirror circuit CM, and an NPN transistor T8.
That is, the third embodiment is different from the clamp circuit 10 of the first embodiment only in that a biasing resistor R4 and an NPN transistor T8 are added.

The transistor T1 constitutes a collector ground circuit, its emitter is connected to the terminal A, its collector is connected to the terminal B via the resistor R4 and grounded, and its base is grounded via the resistor R1.
Transistor T8 constitutes a grounded emitter circuit, the collector of which is connected to terminal A, the emitter of which is connected to terminal B through transistor T2 and grounded, and the base of which is coupled to the collector of transistor T1.
The constant voltage source P generates a constant voltage Vf, and the constant voltage Vf is supplied to the base of the transistor T1 and the resistor R1.

The current mirror circuit CM is a Wideler type current mirror circuit composed of NPN transistors T2 and T3.
The input side transistor T2 has a diode connection in which the base and the collector are coupled. The base and collector of the input side transistor T2 are coupled to the collector of the transistor T8.
The collector of output side transistor T3 is coupled to the base of transistor T1.

[Operation and Effect of Third Embodiment]
According to the third embodiment, in addition to the same operations and effects as in the first embodiment, the following operations and effects can be obtained.

  [3-1] In the clamp circuit 30, when the voltage at the terminal A rises above the voltage Vk (= Vf + VBE) obtained by adding the base-emitter voltage VBE of the transistor T1 to the constant voltage Vf, each transistor is turned on after the transistor T1 is turned on. T8 and T2 are sequentially turned on, and the voltage at the terminal A is lowered to the constant voltage Vk by pulling out the collector current I2 from the terminal A to the ground side (terminal B) through the transistors T8 and T2. Clamp.

That is, the NPN transistor T8 is driven by the PNP transistor T1. The resistor R4 functions as a load resistor of the transistor T1 and is provided for generating a base voltage of the transistor T8 and applying a bias.
That is, in the third embodiment, the technique shown in FIG. 4 of Patent Document 2 is applied to the first embodiment.

[3-2] In the clamp circuit 30, the collector current I2 of the transistor T8 is a value obtained by multiplying the base current Ib of the transistor T1 by the DC current amplification degree G of the transistor T1 and the DC current amplification factor βc of the transistor T8 ( I2 = Ib × G × βc).
On the other hand, in the clamp circuit 10, the collector current I2 of the transistor T1 has a value obtained by multiplying the base current Ib of the transistor T1 by the DC current amplification factor βb of the transistor T1 (I2 = Ib × βb).

Therefore, according to the clamp circuit 30, the base current Ib necessary for obtaining the same collector current I2 can be reduced as compared with the clamp circuit 10.
Therefore, according to the clamp circuit 30, the current I1 flowing through the resistor R1 can be reduced by the amount that the base current Ib is smaller than that of the clamp circuit 10, and the resistance value of the resistor R1 can be increased. The action and effect of [1-4] of the first embodiment can be further enhanced.

[3-3] Generally, in a bipolar semiconductor integrated circuit, an element such as a transistor is generated on a P-type substrate by an epitaxial growth technique.
In this case, in the NPN transistor, a P-type diffusion layer serving as a base is generated in an N-type epitaxial layer generated by epitaxial growth on a P-type substrate, and an N-type diffusion layer serving as an emitter is generated in the P-type diffusion layer. The N-type epitaxial layer becomes the collector. That is, the NPN transistor is formed in a vertical structure.
On the other hand, in a PNP transistor, a P-type diffusion layer serving as an emitter and a P-type diffusion layer serving as a collector are formed side by side on an N-type epitaxial layer formed by epitaxial growth on a P-type substrate. A shaped epitaxial layer is the base. That is, the PNP transistor is formed in a lateral structure.

The current drive capability (maximum collector current) of the transistor depends on the emitter area and the emitter current density.
Since the PNP transistor has a lateral structure, since current flows near the surface of the substrate, it is easily affected by the surface of the substrate, and the emitter current density cannot be increased. In addition, the emitter area has a length in the thickness direction of the P-type diffusion layer. Because it depends, the emitter area cannot be increased.

Therefore, the PNP transistor of the bipolar integrated circuit is significantly inferior in current driving capability as compared with the NPN transistor of the same occupation area on the same substrate, and is 1/10 to 1/100 as well known.
In other words, the PNP transistor requires a substrate occupation area (chip area) 10 to 100 times that of the NPN transistor in order to obtain a current drive capability equivalent to that of the NPN transistor.

In the clamp circuit 30, the voltage at the terminal A is clamped to a constant voltage Vk by drawing the collector current I2 from the terminal A to the ground side (terminal B) via the NPN transistor T8, so the maximum value of the collector current I2 is NPN transistor. It is determined by the current drive capability (maximum collector current) of T8.
On the other hand, in the clamp circuit 10, the voltage of the terminal A is clamped to the constant voltage Vk by extracting the collector current I2 from the terminal A to the ground side (terminal B) via the PNP transistor T1, and therefore the maximum value of the collector current I2 is It is determined by the current drive capability (maximum collector current) of the PNP transistor T1.
Therefore, according to the clamp circuit 30, it is possible to reduce the occupied area of the circuit on the semiconductor substrate as compared with the clamp circuit 10 while obtaining the same current driving capability (maximum collector current I 2) as that of the clamp circuit 10.

(Fourth embodiment)
FIG. 9 is a circuit diagram showing the clamp circuit 40 of the fourth embodiment.
The clamp circuit 40 includes a PNP transistor T1, terminals A and B, bias resistors R1 and R4, a constant voltage source P, a current mirror circuit CM, an NPN transistor T8, and a diode D2.
That is, the fourth embodiment is different from the clamp circuit 30 of the third embodiment only in that the diode D2 is forward-connected between the collector of the transistor T8 and the terminal A.

The cathode of the diode D2 is formed in the N-type epitaxial layer, and the anode of the diode D2 is formed in the P-type diffusion layer.
That is, the fourth embodiment is obtained by applying the technique shown in FIG. 1 of Patent Document 2 to the third embodiment.

Therefore, according to the clamp circuit 40, even when the voltage at the terminal A drops below the potential of the P-type substrate, the parasitic NPN transistor does not occur, and the clamp circuit 40 malfunctions due to the parasitic NPN transistor. Can be prevented.
Incidentally, when a parasitic NPN transistor is generated, a parasitic current may flow from the collector of the NPN transistor other than the clamp circuit 40 formed on the P-type substrate and the base of the PNP transistor, and the clamp circuit 40 may malfunction.

[Another embodiment]
By the way, the present invention is not limited to the above-described embodiments, and may be embodied as follows. Even in this case, operations and effects equivalent to or more than those of the above-described embodiments can be obtained.

  [1] In each embodiment, the current mirror circuit CM is configured such that the collector current of the input-side transistor T2 and the collector current of the output-side transistor T3 are equal, but the input-side and output-side currents correspond at a constant ratio. You may make it do.

[2] In each embodiment, the bipolar transistors T2 and T3 constituting the Wideler type current mirror circuit CM may be replaced with MOS-FETs.
If the MOS-FET is used, the collector currents of the transistors T2 and T3 can be equalized with higher accuracy.

  [3] The current mirror circuit CM in the second to fourth embodiments may have the same configuration as that of each modification of the first embodiment.

1 is a circuit diagram showing a clamp circuit 10 according to a first embodiment that embodies the present invention; The circuit diagram which shows the electric constitution of the clamp circuit 10 in the 1st modification of 1st Embodiment. The circuit diagram which shows the electric constitution of the clamp circuit 10 in the 2nd modification of 1st Embodiment. The circuit diagram which shows the electric constitution of the clamp circuit 10 in the 3rd modification of 1st Embodiment. The circuit diagram which shows the electric constitution of the clamp circuit 10 in the 4th modification of 1st Embodiment. The circuit diagram which shows the electrical constitution of the clamp circuit 10 in the 5th modification of 1st Embodiment. The circuit diagram which shows the clamp circuit 20 of 2nd Embodiment which actualized this invention. The circuit diagram which shows the clamp circuit 30 of 3rd Embodiment which actualized this invention. The circuit diagram which shows the clamp circuit 40 of 4th Embodiment which actualized this invention. The circuit diagram which shows the clamp circuit 50 of a prior art.

Explanation of symbols

10, 20, 30, 40, 50 ... clamp circuit T1 ... PNP transistor (first PNP transistor)
T7 ... second PNP transistor T8 ... NPN transistor A ... first terminal B ... second terminal R1 ... bias resistor P ... constant voltage source CM ... current mirror circuit

Claims (3)

A clamp circuit for clamping a voltage between a first terminal and a second terminal to a constant voltage,
A PNP transistor having an emitter connected to the first terminal and flowing a collector current from the first terminal to the second terminal;
A resistor connected between the base of the transistor and the second terminal;
A constant voltage source for supplying a constant voltage to the base of the transistor and the resistor;
A clamp circuit comprising: a current mirror circuit configured to flow a current corresponding to a collector current of the transistor from a base of the transistor to a second terminal. A clamp circuit for clamping a voltage between a first terminal and a second terminal to a constant voltage,
A first PNP transistor having an emitter connected to the first terminal and flowing a collector current from the first terminal to the second terminal;
A second PNP transistor Darlington connected to the first PNP transistor;
A resistor connected between a base of the second PNP transistor and a second terminal;
A constant voltage source for supplying a constant voltage to a base of the second PNP transistor and the resistor;
A clamp circuit, comprising: a current mirror circuit for causing a current corresponding to a collector current of the first PNP transistor to flow from a base of the second PNP transistor to a second terminal. A clamp circuit that clamps a voltage between a first terminal and a second terminal to a constant voltage,
An NPN transistor having a collector connected to the first terminal and flowing a collector current from the first terminal to the second terminal;
A PNP transistor having an emitter connected to the first terminal and driving the NPN transistor;
A resistor connected between the base of the PNP transistor and the second terminal;
A constant voltage source for supplying a constant voltage to the base of the PNP transistor and the resistor;
And a current mirror circuit for supplying a current corresponding to a collector current of the NPN transistor from a base of the PNP transistor to a second terminal.

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