JP4431215B2 - Manufacturing method of semiconductor wafer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly to a method for manufacturing a semiconductor wafer that is effective for dividing a thin semiconductor wafer.
[0002]
[Prior art]
In the manufacture of power devices such as power transistors and power MOSFETs, a diffusion wafer in which a high concentration dopant is diffused on one side of a silicon wafer is used. As a method for manufacturing this diffusion wafer, a method is known in which a silicon wafer in which a dopant is diffused on both sides is divided into two. According to this two-divided method, two single-sided diffusion wafers can be obtained from one silicon wafer, which is preferable from the viewpoint of productivity, and this method is mainly used at present.
[0003]
Further, in the above two-division method, various methods for dividing a plurality of silicon wafers at once have been attempted in order to improve production efficiency. Such batch cutting of a plurality of wafers has already reached a practical level by using a wire saw, and many known examples have been reported.
[0004]
[Problems to be solved by the invention]
In the manufacture of power devices, the thickness of the wafer is not considered as a problem. Therefore, if a thin semiconductor wafer can be divided, a reduction in material cost can be expected. Therefore, it is desired to improve the wafer cutting accuracy and reduce the production cost as compared with known methods.
[0005]
Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor wafer that is effective for dividing a semiconductor wafer having a small thickness.
[0006]
[Means for Solving the Problems]
The following approach has been taken as means for achieving the above object, and will be described here. First, we examined the accuracy of fragmentation by the following method.
[0007]
FIG. 1 is a schematic perspective view showing a test method for dividing a semiconductor wafer. The division shown in the figure is performed by cutting with the wire saw 12 with the stacked body 20 of the semiconductor wafer 18 fixedly placed on the carbon slice plate 36 and the outer peripheral surface of the stacked body 20 fixed with wax. . When the semiconductor wafer was actually cut by this method and its parallelism was examined, the following results were obtained. The parallelism is a parameter indicating how uniform the thickness of one semiconductor wafer is in a plane.
[0008]
FIG. 2 is a conceptual diagram showing a method for measuring parallelism. As shown in the figure, the thicknesses at arbitrary points A to E of the divided semiconductor wafer 18 are respectively measured, and the difference between the minimum value and the maximum value among the measured results is taken and the values are parallelized. Degree. If the difference between the minimum value and the maximum value is small, the parallelism is good, and if the difference is large, the parallelism is bad.
[0009]
FIG. 3 is a graph showing measurement results of wafer parallelism measured by the method shown in FIG. As shown in the figure, the parallelism measured by the method of FIG. 2 was small near the center of the stack and large outside. More specifically, the thickness variation in the vertical lines A, E, and C in FIG. 2 is large, and this vertical line variation appears in the poor parallelism of the semiconductor wafer laminated on the outside shown in FIG. ing. That is, a specific distribution occurs in the parallelism depending on the stacking position of the semiconductor wafer. From this measurement result, it can be considered that the semiconductor wafer is cut in the following state.
[0010]
FIG. 4 is a schematic side view showing a state of the semiconductor wafer at the time of cutting. If the parallelism of the vertical lines is poor, it is conceivable that the cut portions of each semiconductor wafer 18 will spread in a fan shape as shown in FIG. This is because, as shown in FIG. 1, even if the outer peripheral surface of the laminated body 20 is fixed with the wax 44, the wax 44 is also divided at the same time as the cutting progresses, so that the holding power in the laminated state is reduced. is there. Since the semiconductor wafer 18 is divided from the upper part to the lower part of the stacked body 20, the interval between the semiconductor wafers 18 is opened in order from the upper part. As a result, the stacked body 20 has a fan shape as shown in FIG. Become.
[0011]
In this way, when the cutting progresses while each semiconductor wafer 18 is opened, the semiconductor wafers 18 stacked on the outside are cut obliquely, and as a result, the parallelism after the division has a distribution as shown in FIG. become. As the thin semiconductor wafer is obtained, the tolerance of parallelism becomes stricter. Therefore, it is difficult to cut the thin semiconductor wafer by the above-described cutting method spreading in a fan shape.
[0012]
Therefore, the creative act was repeated from the viewpoint of suppressing the fan-shaped spread, and the idea of “cutting while sandwiched in the stacking direction” was obtained. The present invention is intended to solve the above-described problems based on such an idea.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
(Summary of Invention)
The feature of the present invention conceived on the basis of the above-described idea is that the dividing operation is performed while the laminate is sandwiched. As a result, even if the wire enters the inside of the semiconductor wafer and the divided portion tries to spread outward, the spread is suppressed by the clamping force. As a result, the dividing operation proceeds with the semiconductor wafer standing, and the parallelism after the dividing is improved.
[0014]
(Mode of Invention)
FIG. 5 is a schematic side view showing a method for dividing a semiconductor wafer according to the present invention. The configuration of the present invention will be described below with reference to FIG.
[0015]
First, an important point in the present invention is that the wire 30 is inserted in a state where the stacked body 20 of the semiconductor wafer 18 is sandwiched as shown in FIG. The stacked body 20 is sandwiched along the stacking direction of the semiconductor wafer 18, and the stacked body 20 is preferably sandwiched from both ends thereof. In this way, by sandwiching from both ends, it is possible to always maintain the laminated state regardless of which position the wire 30 divides.
[0016]
As a method of sandwiching both ends of the stacked body 20, as shown in the figure, a method of bringing the sandwiching member 14 into contact with the semiconductor wafers 18 positioned at both ends of the stacked body 20 can be considered. This clamping may be performed by applying a force from both sides of the laminate 20 or may be performed by applying a force from the other side while fixing one side. The clamping force is set so that the semiconductor wafer 18 is not damaged.
[0017]
The significance of sandwiching the laminated body 20 from both ends becomes clearer when compared with the conventional method in which the outer peripheral surface of the laminated body 20 is fixed with wax. That is, in the conventional wax fixing, since the wax is also cut at the same time as the cutting progresses, the fixed state cannot be obtained at all times. Since the position of the member 14 and the course of the wire 30 indicated by the dotted line in the figure do not overlap, the laminated state can always be maintained.
[0018]
As described above, when the wire 30 is inserted in a state where the stacked body 20 is sandwiched, the semiconductor wafers 18 constituting the stacked body 20 are divided in a standing state. Ideally, as shown in the figure, each semiconductor wafer 18 is divided into two with high accuracy through the center of the semiconductor wafer 18 where the path of the wire 30 stands. As a result, since the parallelism of the divided semiconductor wafer is improved, it becomes possible to divide the thin semiconductor wafer.
[0019]
In addition, this invention does not exclude fixing the outer periphery of the laminated body 20 with wax, and it is within the scope of the present invention to cut while sandwiching the laminated body fixed with wax. For example, it is within the scope of the present invention to stack the semiconductor wafers 18 outside the wire saw, and then fix them with wax and sandwich them in the wire saw.
[0020]
In addition, a method of performing both lamination and clamping of the semiconductor wafer inside the wire saw, and a laminated body sandwiched and laminated using a predetermined jig outside the wire saw are put into the wire saw together with the jig, A method of performing the cutting operation as it is is also within the scope of the present invention.
[0021]
【Example】
(wrap up)
The stacked body 20 made of a plurality of semiconductor wafers is placed on the carbon slice plate 36, and the stacked body 20 is sandwiched by the clamp table 24. And the laminated body 20 is raised with the clamp stand 24, and the semiconductor wafer which comprises this laminated body 20 is parted with the wire saw 12 (refer FIG. 8).
[0022]
(Preferred embodiment)
The above-described technical idea of “cutting while sandwiched in the stacking direction” is a very useful idea in the field of diffusion wafer manufacturing. Here, an example in which this characteristic technical idea is embodied in an industrially preferable manner is shown. In the following description, among the above-described components, those that are not particularly required to be described are given the same names and the same reference numerals, and detailed descriptions thereof are omitted.
[0023]
In this embodiment, an example of upper cut (upper cut) will be described. However, the same applies to lower cut (down cut). Moreover, the Example shown below is one example of implementation of this invention, and does not limit this invention.
[0024]
FIG. 6 is a perspective view showing a semiconductor wafer laminating process. As shown in the figure, when a diffusion wafer is manufactured by a two-division method, first, a plurality of semiconductor wafers 18 having dopants diffused on both surfaces in advance are placed on a carbon slice plate 36, and the stacked body 20 is formed. Form.
[0025]
The carbon slice plate 36 is a relatively soft support plate made of carbon, and is cut by the wire saw 12 together with the semiconductor wafer 18. A curved surface corresponding to the curvature of the semiconductor wafer 18 is formed on the upper portion of the carbon slice plate 36, that is, on the portion where the semiconductor wafer 18 is placed, and each semiconductor wafer 18 has an orientation flat facing upward. It is mounted on this curved surface in a state.
[0026]
Next, the clamp shaft 34 is rotated, the clamping plate 32 is pressed against the laminate 20, and the laminate 20 is sandwiched between the clamping plate 32 and the reference surface 38. At this time, the force for sandwiching the stacked body 20 is set such that the semiconductor wafer 18 is not broken. Here, since it is necessary to adjust the parallelism of the clamping plate 32 and the reference surface 38, it is needless to say that the present invention also includes an example having both parallelism adjustment functions.
[0027]
Thereafter, the clamp base 24 sandwiching the laminated body 20 is placed and installed inside the wire saw.
[0028]
FIG. 7 is a side view showing a step of confirming the stacked state of the semiconductor wafer. After the clamp base 24 is inserted and installed in the wire saw, as shown in the figure, the wire 30 is disposed above the laminate 20 sandwiched by the clamp base 24, and the camera 26 is disposed thereon. .
[0029]
The camera 26 is disposed so as to be movable in the direction indicated by the arrow in the drawing, that is, the stacking direction of the semiconductor wafer, and images the orientation flat of the wire 30 and the semiconductor wafer 18 simultaneously from above. An image captured by the camera 26 is enlarged and displayed on a monitor (not shown) connected to the camera 26, and the operator positions the wire 30 based on the enlarged display.
[0030]
The positioning of the wire 30 is performed with reference to the semiconductor wafer 18 stacked near the center, as shown in FIG. For example, as shown in the figure, a wire 30 for cutting the semiconductor wafer 18 is arranged at the center of the thickness of the fifth semiconductor wafer 18 from the reference plane 38, and this position is set as a cutting position.
[0031]
As described above, the reason for positioning the wire with reference to the semiconductor wafer laminated near the center is that the clamping plate is based on the semiconductor wafer laminated outside, for example, the semiconductor wafer in contact with the reference surface 38. This is because the position of the wire 30 for cutting the semiconductor wafer in contact with 32 is greatly shifted due to a stacking error. On the other hand, when a semiconductor wafer laminated in the vicinity of the center is used as a reference for wire positioning, the lamination error can be reduced and the processing accuracy can be further improved.
[0032]
After determining the cutting position of the reference wafer as described above, the cutting position of the remaining semiconductor wafer 18 is confirmed as follows. First, while moving the camera 26 little by little, the respective semiconductor wafers 18 and the wires 30 thereabove are sequentially imaged. If the position of each wire 30 is not within the allowable range from the thickness center of each semiconductor wafer 18, the stacking of the semiconductor wafer 18 is performed again, and the alignment of the wire 30 is performed again. At this time, a thickness correcting wafer and a spacer for thickness adjustment may be used. On the other hand, if the position of each wire 30 is within an allowable range from the thickness center of each semiconductor wafer 18, it is determined that cutting is possible, and the process proceeds to the next dividing step.
[0033]
FIG. 8 is a perspective view showing a semiconductor wafer dividing step. As shown in the figure, after positioning the wire shown in FIG. 7, the wire saw table unit 42 loaded with the clamp base is raised, and each semiconductor wafer constituting the stacked body 20 is divided by the wire saw 12. To do. Here, it goes without saying that the function of adjusting the parallelism of the ascending direction of the table and the reference surface 38 on the wire saw table unit 42 and the clamping plate 32 is provided in the wire saw 12 or the present mechanism.
[0034]
The wire saw 12 is formed by winding a single wire 30 around a plurality of work rollers 28. And the multiple cutting | disconnection part 10 for cut | disconnecting a semiconductor wafer is formed by the multiple winding of this wire 30. FIG. Each work roller 28 has a V-groove formed by a chaser bite process, and the wire 30 is wound along the V-groove. The czer bite processing is a processing method in which a plurality of V grooves are simultaneously formed using a comb-shaped blade. According to this processing method, the pitch error of the V grooves is very small. As very preferred. In addition, since the wire saw itself is well-known, the other description regarding a wire saw is abbreviate | omitted.
When the diffusion wafer was manufactured by the method as described above, it was possible to cut a semiconductor wafer thinner than the conventional one, and to obtain a diffusion wafer having less thickness variation and excellent parallelism.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view showing a semiconductor wafer cutting method performed as a test.
FIG. 2 is a conceptual diagram showing a method for measuring parallelism.
FIG. 3 is a graph showing measurement results of wafer parallelism measured by the method shown in FIG.
FIG. 4 is a schematic side view showing a state of a semiconductor wafer at the time of cutting.
FIG. 5 is a schematic side view showing a method for dividing a semiconductor wafer according to the present invention.
FIG. 6 is a perspective view showing a semiconductor wafer stacking step.
FIG. 7 is a side view showing a step of confirming the stacked state of the semiconductor wafer.
FIG. 8 is a perspective view showing a semiconductor wafer dividing step.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Cutting part, 12 ... Wire saw, 14 ... Holding member, 18 ... Semiconductor wafer, 20 ... Laminated body, 24 ... Clamp stand, 26 ... Camera, 28 ... Work roller, 30 ... Wire, 32 ... Clamping plate, 34 ... Clamp shaft, 36 ... Carbon slice plate, 38 ... Reference plane, 42 ... Wire saw table unit, 44 ... Wax, 46 ... Orientation flat

Claims (3)

A step of forming a laminate (20) by laminating a plurality of semiconductor wafers (18);
Sandwiching the stacked body along the stacking direction of the semiconductor wafer;
A step of dividing the semiconductor wafer constituting the laminated body with a wire saw (12) in a state where the laminated body is sandwiched. The sandwich of the laminate is
The method for producing a semiconductor wafer according to claim 1, wherein the method is performed from both ends of the laminate. A step of forming a laminate (20) by laminating a plurality of semiconductor wafers (18);
Clamping the laminate using a clamp base (24);
Installing a clamp base sandwiching the laminate inside the wire saw (12);
A step of cutting the semiconductor wafer constituting the laminated body with the wire saw while the laminated body is held by a clamp base.

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