JP4428624B2 - Image display system - Google Patents

Description

  The present invention relates to an image display system such as a projector that deflects and displays light from a light modulation element with a deflection element, and in particular, divides one frame of image data to be displayed into a plurality of subframe image data. The present invention relates to an image display system capable of realizing display with resolution higher than that of a light modulation element by division and efficiently performing image processing of image data used for the modulation.

In recent years, the resolution of display images has been increased due to a dramatic increase in processing capability of information processing apparatuses, and accordingly, there has been an increasing demand for higher resolution in image display systems such as projectors.
On the other hand, in an image display system, an original image is often displayed after being subjected to various processes. However, as the resolution increases, a higher processing speed is required. For example, in QXGA (horizontal 2048 pixels × vertical 1536 pixels), the clock frequency for processing is about 300 MHz.
The prior art disclosed in Patent Document 1 is intended to solve such a problem, and is processed in four phases so that the pixel series image data to be processed can be processed in parallel (in parallel in units of four pixels). And four processing circuits are provided in association with the image data divided into four and four in parallel, and the input image data divided into four is processed in parallel (here, compression / enlargement processing) to generate a clock. The frequency is lowered.
Further, in the prior art disclosed in Patent Document 2, the image data divided into four by four-phase (four-parallel) in units of four consecutive pixels is further multiphased and divided using delay means, Select four of the multi-phased input image data corresponding to each of the subsequent four filter operation units, and reduce the clock frequency by parallel processing each of the selected four image data with the four filter operation units. ing. There are also Patent Documents 3 and 4 as related documents.

JP 2001-142451 A JP 2001-143060 A JP-A-6-324320 Japanese Patent No. 3022405

However, in the conventional techniques shown in Patent Document 1 and Patent Document 2, if high-definition display is realized by time-division display in units of subframes using a deflection element, four phases are used for image processing. In order to perform display while dividing, it is necessary to perform a two-stage division operation of re-dividing into subframes. This increases the circuit scale, thus increasing the number of parts and increasing the cost.
In the prior application of the present applicant, the image is processed and divided into subframes to be displayed, and an image of each subframe using the light modulation element and the deflection element (the number of pixels of the light modulation element is equal to the number of subframes). The number of pixels for one frame is a value obtained by multiplying the number of pixels of the light modulation element by the number of subframes). In this method, when parallel image processing is not performed, there is an advantage in terms of the circuit scale of the processing circuit. However, if parallel processing is performed by the same method as the above-described conventional technique, the circuit scale is similarly increased, Cost increases.
An object of the present invention is to solve such problems of the prior art. Specifically, one frame is divided into sub-frames to be displayed, and each sub-frame is formed using a light modulation element and a deflection element. An object of the present invention is to provide an image display system capable of realizing parallel image processing without increasing the circuit scale in image display in which images of frames are displayed in a time division manner.

In the present invention, there is provided image data dividing means for dividing image data for one frame to be displayed in correspondence with a plurality of subframes, and each image data divided by the image data dividing means is modulated with image data. In an image display system that deflects the modulated light using an optical deflecting element and displays each subframe at a corresponding position in the frame in a time-sharing manner, image processing of each subframe data is performed for each subframe, An image processing circuit that performs image processing for each subframe in parallel processing, a plurality of memories for holding the subframes, an address decoder that gives a common address to the plurality of memories, and the plurality of memories And an input / output control circuit for controlling input / output of the subframe.

According to the image display system of the present invention, image processing of each subframe data can be performed for each subframe, and image processing for each subframe can be performed in parallel processing, so that processing per image processing circuit is possible. As a result, the amount of data is reduced, and as a result, it is possible to use low-speed components. Therefore, even if a plurality of image processing circuits are provided, the cost can be reduced. In addition, by providing a plurality of memories that hold subframes and giving a common address to the plurality of memories, it is possible to handle address designation in a single way even if the memory to be accessed changes, so the processing can be simplified. .

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the components, types, combinations, shapes, relative positions, and the like described in this embodiment are not merely intended to limit the scope of this description unless otherwise specified, but are merely illustrative examples. .
The image display system of this embodiment divides one frame of display image data arranged in a display array into four subframes, performs image processing on the image data of each subframe, and modulates the image data Each subframe is displayed in a time-sharing manner using the modulated light. Each example will be described below.

FIG. 1 is a block diagram showing the main part of the image display system of this embodiment. As a data source, a device that outputs an image signal of QXGA (2048 × 1536) is used. In FIG. 1, arrows indicate the flow of data .
With such a configuration, the first dividing circuit 1 divides the input image data (image signal) into odd and even lines for each scanning line. Further, the second dividing circuits 2 and 3 divide the divided image data of each scanning line into odd-numbered pixel data and even-numbered pixel data. Then, the divided image data is divided and stored in the frame memories 4 to 7 which are storage elements.
Both the first dividing circuit 1 and the second dividing circuits 2 and 3 can basically use a 1: 2 demultiplexer for each bit of input image data. Here, since each color uses 8-bit pixel data, eight 1: 2 demultiplexers are used for one color. 8-bit input data (input signal) is switched for each color by a signal for controlling switching.
FIG. 2 shows a specific example of the dividing circuit for one-bit input (INPUT).
Hereinafter, the operation will be described.
In FIG. 2, the demultiplexer 11 belongs to the first divided circuit 1, the demultiplexer 12 belongs to the second divided circuit 2, and the demultiplexer 13 belongs to the second divided circuit 3. The demultiplexer 11 is G11 = H (H means High level, the same applies hereinafter) with respect to the input of the control signal G11, and X1 = Y1 and G11 = L (L means Low level; the same applies hereinafter). Then, X1 = Y2. The relationship between one frame of data and the control signals G11, G21, and G22 is shown in FIG.

In FIG. 14, for example, 2n−1 = H means that the level is high when the pixel is odd, 2n = L means that it is low when the pixel is even, and 2m−1 is an odd number. The scanning line, 2m means an even scanning line. That is, the values (levels) of G11, G21, and G22 are uniquely determined by the position in the image frame. These G11, G21, and G22 can be created from horizontal and vertical synchronization signals and clock signals that are control signals for image signals. However, with this method, as the resolution increases and the operating frequency of the signal increases, the image data itself is distributed by the distributor, which causes problems such as waveform distortion and delay.
On the other hand, in the configuration shown in the block diagram of FIG. 3, a common address and data are arranged in the frame memories 4 to 7 and input and output are directly controlled, thereby supporting high-speed operation without data distortion. it can. As a memory element used for the frame memories 4 to 7, an element capable of controlling the signal input / output pins to be in a high impedance state is used. An example is SRAM. FIG. 15 shows the level of the control signal output from the control circuit 14 and the operation of the memory element SRAM. The main control signal controls writing / reading! Select one frame memory by controlling the WE and input / output impedance states! CS (see FIG. 15).
As shown in FIG. 3, image data to be displayed (referred to as display data) controlled by the input / output control circuit 15 is input to the four frame memories 4 to 7 through the common wiring 18, and the frame The data is also passed from the memories 4 to 7 to the output side via the common wiring 18.
On the other hand, the address signal is generated by the address decoder 17 based on the signal output from the address signal generation circuit 16 and supplied to the frame memories 4 to 7. Since the timing differs between writing and reading, the control circuit 14 switches between reading and writing (see FIG. 15).
In the configuration shown in FIG. 3, the control circuit 14, the input / output control circuit 15, the address signal generation circuit 16, the address decoder 17 and the like are used to change the address for each scanning line and each pixel position, as described in FIG. Such a pixel data array is realized.

In FIG. 3, the input / output control circuit 15 is input from the outside in order to prevent the display data from being input to the frame memories 4 to 7 and the output from the frame memories 4 to 7 from colliding with each other. When the display data is commonly input to the data signal lines of the frame memories 4 to 7 and is output from the frame memories 4 to 7 to the display unit, the output of the input / output control circuit 15 is set to a high impedance state.
As the address signal, a signal corresponding to writing / reading is generated by the address signal generation circuit 16 from a synchronization signal of display data, a clock signal, a control signal of the display unit, and the like, and is output from the address decoder 17 based on the signal.
! CE signal and! The WE signal is sent to the frame memory performing the write operation during the write operation! CE = L! WE = L and for other frame memories! A high impedance state is established by setting CE = H. Control signal! By switching the frame memory that sets the CE level to Low, display data can be written only to a required address of the required frame memory using a common address signal and data wiring. At the time of output, for each subframe data written in each of the frame memories 4 to 7, the frame memories 4 to 7 are sequentially switched and output at a subframe period. In FIG. 3, the data direction of writing / reading is controlled depending on whether the mode of each frame memory 4-7 is writing or reading. An example of the configuration is shown in FIG. As shown in the figure, the three-state buffers 21 and 22 can be combined. A truth table of the 3-state buffer 21 is shown in FIG. As is clear from FIG. 4 and FIG. When WE = L (write operation), the OE input becomes High, and the input from the input / output control circuit 15 (input to the 3-state buffer 21) is directly output to the frame memories 4 to 7 (output of the 3-state buffer 21). ) At this time, the 3-state buffer 22 heading from the frame memories 4 to 7 to the display unit is OE = L, and the output is in a high impedance state.
on the other hand,! When WE = H (reading operation), the OE input of the 3-state buffer 22 becomes High, so that the 3-state buffer 22 heading from the frame memories 4 to 7 to the display unit becomes input = output. At this time, the 3-state buffer 21 that supplies display data from the input / output control circuit 15 to the frame memories 4 to 7 is OE = L, and its output Y is in a high impedance state.
Thus, in the circuit shown in FIG. In accordance with the control of the WE signal, input / output can be switched with a simple configuration and a small number of wires.
In the configuration shown in FIG. 3, the operation of the frame memories 4 to 7 can be controlled only by switching the control signal, and the address signal line and the data signal line can be shared, so that the display data is switched directly. Compared with the method, the circuit scale can be reduced, and the cost can be reduced.

FIG. 5 is a block diagram of the configuration including the periphery of the circuit shown in FIG. 3. One frame of display data (display image data) stored in the frame buffer 8 is divided into four subframes, and the display data of each subframe is displayed. Is input to the light modulation element 20. In FIG. 5, the subframe dividing unit 9 is a circuit in which the control circuit 14, the input / output control circuit 15, the address signal generation circuit 16, the coder 17 and the like are collectively shown in FIG. It is controlled by a memory control signal output from the subframe dividing unit 9 and is divided and stored in the frame memories 4 to 7 for each subframe.
Also for reading, the subframes are sequentially output from the similarly controlled frame memories 4 to 7 for each subframe, and display data of one subframe is processed in parallel by a plurality of image processing circuits 10 installed in parallel. The display is realized by inputting the processed display data to the light modulation element 20. Note that image processing performed in the image processing circuit 10 includes, for example, image quality adjustment, γ adjustment, contrast adjustment, and the like. In addition, the distribution to the plurality of image processing circuits 10 is performed by, for example, addresses when reading from the frame memories 4 to 7.
As described above, according to this embodiment, one frame of data can be divided into display subframes used in the image display of the present invention, and a plurality of subframes can be displayed in image processing. Since the display data of one subframe is processed in parallel instead of processing data in parallel, the amount of processing data per image processing circuit is reduced, and as a result, low-speed components can be used. Therefore, cost reduction of the image processing circuit can be realized.

In this embodiment, a QXGA (2048 × 1536) image signal is used as a data source for one frame as in the first embodiment. However, one frame data is a subframe displayed from such a data source. For example, the data is divided into four parts in a different state from the data division, and the respective divided frame data are input in parallel from the four input ports. In this embodiment, data obtained by combining such divided input image data is handled as display data for one frame, and the display data is divided into four subframe data for display.
FIG. 6 shows an example of division of input image data by address. In FIG. 6, (a) shows the address of one frame of original image data, and (b) to (e) show the addresses of the image data of each divided frame (the size of the image is the actual image). Does not show the size of). That is, the horizontal direction (scanning line direction) is divided into two equal parts while holding the pixel array of the original image data shown in (a), and the vertical direction is divided into two equal parts while maintaining the order of the scanning lines.

FIG. 7 shows a configuration block diagram of a circuit for generating input image data divided into the divided frames. Hereinafter, the operation of generating input image data will be described with reference to FIG.
In the configuration of FIG. 7, the CPU 24 is used. The CPU 24 executes various processes by accessing a memory 27 that stores a program for executing processes and data of intermediate / final results via the first controller 25. . The second controller 26 writes data to the auxiliary storage device 28 such as a hard disk storage device, the I / O control unit 29 that controls the external input device 30 such as a switch, and the image control unit 31 that controls image data. Controls reading of instructions and data.
The image control unit 31 also controls the frame memory 32 and the four drawing engines 33 on the local bus 34. The frame memory 32 is a memory corresponding to one frame, and stores and arranges image data for one frame input from an image input device such as a scanner as necessary.
The four drawing engines 33 draw and generate image data of the four divided frames in response to a drawing command from the CPU 24. This drawing may be drawing for capturing image data in the frame memory 32, or may be drawing for generating a line drawing such as a circle or a straight line. A configuration including a local frame memory (not shown) associated with each rendering engine 33 is also possible. With such a configuration, rendering that is not limited by the local bus transfer speed under the control of the image control unit 31 is possible. .
Note that the image control unit 31 distributes the drawing command from the CPU 24 to the drawing engine 33 in charge of the corresponding address area. Each drawing engine 33 performs drawing in accordance with a drawing command from the CPU 24 in the address area that it is in charge of. As a result, it is possible to draw over a plurality of divided frames.
In this way, the input image data drawn by each drawing engine 33 is output to the subsequent apparatus in parallel for four divided frames.
A subsequent apparatus that receives the input image data includes a circuit group having the configuration shown in FIG. 5, for example, and the input image data is stored in the frame buffer 8 through four input ports (not shown). At that time, it is possible to identify which portion of the divided frame data in one frame is based on which input port is input, and to handle input image data input in four divided portions as display data of one frame. Thereafter, division into display subframes similar to that in the first embodiment is performed, and the result is output to the display unit.

FIG. 8 shows an operation flow for generating input image data. FIG. 8A is an operation flow for obtaining addresses divided into four, and FIG. 8B is an operation flow for generating image data in response to a drawing command from the CPU 24. Hereinafter, this operation flow will be described.
First, when the image control unit 31 receives the original image size from the CPU 24 (S1), it calculates an address area divided into four as shown in FIG. 6, for example (S2). Then, the image control unit 31 associates the calculated address area with the drawing engine 33 and stores the information in a register (S3).
Subsequently, upon receiving a drawing command from the CPU 24 (S11), the image control unit 31 extracts address information from the drawing command (S12), and performs drawing based on the information associated with the address information in step S3. The drawing engine 33 is obtained (S13). Then, a drawing command from the CPU 24 is passed to the corresponding drawing engine 33 (S14). Thus, the selected drawing engine 33 performs drawing in accordance with the drawing command issued by the CPU 24 and generates image data.
Thereafter, it is determined whether or not the execution of all the drawing commands has been completed (S15). If it has not been completed (N in S15), the process is repeated from step S12, and if completed (Y in S15), this The operation flow is terminated.
As described above, according to this embodiment, even when input image data is input in a pixel arrangement different from the pixel arrangement of the display subframe, it can be divided into display subframes. The same effect can be obtained. Further, on the side of generating input image data, an image can be created in parallel by a plurality of drawing engines or the like. For example, a drawing engine 33 having the ability to process ¼ pixel with respect to the number of pixels of one frame. Can be used to process an image with four times as many pixels, thus allowing processing by the drawing engine 33 at a lower operating speed.

In this embodiment, adjustment processing necessary for display, such as adjustment of brightness and contrast ratio, and gamma adjustment, is realized by an image processing circuit, and the light modulation element 20 performs gradation display according to the processing result. That is, the side that outputs the display data to the light modulation element 20 outputs image data according to the assumed gamma value of the light modulation element 20, or corrects the brightness of the entire screen according to the user's environment. It is. Further, in this embodiment, in view of the fact that such adjustment relating to the display quality of the screen is generally recognized as a problem of the display device by the user, the image processing circuit for performing the adjustment is provided on the display device main body. Prepare for.
As one process performed by such an image processing circuit, for example, gamma correction is performed, but a corresponding correction value is read according to the gradation information of each pixel. For example, the correction value corresponding to the gradation information of the pixel is read using a lookup table (hereinafter referred to as LUT). The LUT is a kind of storage means, and outputs a corrected value corresponding to a value indicating the gradation at each pixel position. As described above, when the LUT is used, the corresponding value can be output by inputting the gradation information of each pixel position, and high-speed processing is possible. However, in order to correspond to a plurality of conditions, In addition, a peripheral circuit for updating / switching the contents of the LUT is required.
In this embodiment, a display device is provided with a plurality of arithmetic circuits as such an image processing circuit, and correction is performed by performing parallel processing for each subframe by the arithmetic circuit.
The display device also includes a dial type external switch for gamma correction. The user can set the desired gamma value using this external switch, and the CPU that has acquired the digital value passes the value to the arithmetic circuit. The arithmetic circuit acquires image data having gradation information, acquires a gamma value using the gradation information, calculates display data corresponding to the gamma value, and outputs the display data.
In this embodiment, the brightness adjustment can also be compensated by adding an operation to each individual pixel. For example, gamma correction and brightness correction are both performed by the same arithmetic circuit. The arithmetic circuit is realized by using a dedicated one-chip microcomputer. In this case, the I / O port is used when inputting the condition to be changed. The update is performed by writing the condition input from the I / O port into an electric write / erase ROM (EEPROM) or a flash ROM.
Thus, according to this embodiment, image processing necessary for display, such as adjustment of brightness and contrast ratio, and gamma adjustment, can be processed in parallel for each subframe, so that image processing can adjust brightness and contrast ratio, and In the case of image processing necessary for display such as gamma adjustment, the same effect as that of the first embodiment can be obtained. In addition, the fact that the image processing circuit is provided in the display device to enable image processing in the display device is consistent with the fact that the user recognizes such an adjustment relating to the display quality of the screen as a problem of the display device. To do.

In this embodiment, OSD (On Screen Data: adding characters, symbols, etc. to a display image) is performed on the displayed subframe data. Note that characters and symbols used for OSD processing are written in advance in the storage means by the CPU. FIG. 9 shows a configuration block diagram of this embodiment. In this embodiment, the OSD processing means described in claim 5 is realized by the circuit having the configuration shown in FIG.
With this configuration, in this embodiment, the CPU 36 reads out fonts and symbols to be superimposed on the original image from the font ROM 37 and the symbol ROM 38, respectively, and develops them on the development RAM 39 by the RM controller 40 as necessary. Create an image. Then, the OSD image is superimposed on the image obtained from the original image on the memory. In other words, both data are added using the adder circuit 41 for each corresponding address.
The RAM controller 40 expands the OSD image data to an address corresponding to the subframe by controlling the operation of the expansion RAM 39 and its address based on the subframe address signal when expanding on the expansion RAM 39. . That is, after dividing into display sub-frames, only the sub-frame data at a position required for each sub-frame is used to superimpose OSD image data using the adder circuit 41. Further, a part of the OSD processing means as shown in FIG. 9 is provided by the number of subframes to enable parallel processing.
In the above description, it is assumed that the image processing circuit (see FIG. 5) is arranged at a position after the superimposition of the subframe data and the OSD image data. You may arrange. That is, superimposition is performed after image processing of the subframe data is performed. In such a configuration, when the brightness or the like is adjusted later, even if the screen is adjusted to an extremely bright or dark screen, the character information related to the OSD processing is affected by the image quality adjustment (in this case, the brightness adjustment). You do n’t have to.
Further, when outputting only a predetermined pattern or character string, OSD image data can be prepared by directly reading necessary image data from a ROM. In this case, of course, the OSD image data read directly from the ROM and the OSD image data obtained by developing the font pattern read from the font ROM 37 or the symbol ROM 38 as described above can be used in combination.
Thus, according to this embodiment, it is possible to reduce the processing capability of each processing circuit by performing the OSD processing for synthesizing characters and symbols on the image into subframes and performing parallel processing, thereby increasing the cost. A circuit can be configured without using high-speed components.

In this embodiment, pre-processing such as the above-described synthesis of a plurality of images and the synthesis of images and characters (if image quality adjustment is post-processing image processing, this pre-processing can be said to be image processing performed prior to image quality adjustment. ) Is realized by an image output device (for example, an information processing device such as a personal computer) different from the display device. On the image output apparatus, image synthesis, image synthesis, and the like are realized by control of a CPU that operates according to a program. The display device displays the display data received from the image output device by adjusting the image quality of the light modulation element. Hereinafter, an example in which the image output apparatus having the configuration shown in FIG. 10 is realized by an information processing apparatus will be described.
In this embodiment, the file names file1. When displaying bmp on the entire screen, the first controller 26 first develops image data from the auxiliary storage device 28 to the memory 27 via the second controller 26 in accordance with an instruction from the CPU 24. Furthermore, in order to display a different image on a part of the frame, an image stored in the auxiliary storage device 28 by an external input device (external input device capable of inputting coordinates, characters, etc., such as a mouse, a trackball, and a keyboard) 30. And specify the input position. Then, in response to an instruction from the CPU 24, the first controller 26 again reads the newly designated image data (file name file2.bmp) from the auxiliary storage device 28 and develops it on the memory 27 via the second controller 26.
Subsequently, the CPU 24 uses the conditions such as the coordinates input from the external input device 30 and the image displayed above when they are overlapped, and the image data at each pixel position among the two image data on the memory 27. Which image data is determined and extracted. Then, the resulting display data is transferred to the image control unit 31 for display. On the display device, file1. When an image of bmp is displayed and designation is made from the external input device 30, file2. A configuration in which a bmp image is displayed is also possible.
In the configuration shown in FIG. 10, in the above, the image creation process is realized by the drawing engine 33a having the overwriting display function. That is, file1. bmp and file2. The bmp is transferred and expanded to the frame memory 32 under the control of the image control unit 31, and then the drawing engine 33a obtains and draws which is displayed on the pixel at the designated position in accordance with an instruction from the CPU 24. . In this case, after instructing the processing contents to the image control unit 31, the CPU 24 is released from the processing / calculation for drawing, and can immediately execute other processing than drawing.
Information processing apparatuses such as personal computers often have various processing functions including pre-processing such as enlargement, reduction, and resolution conversion. This embodiment considers such a situation, and according to this embodiment, as described above, by using such an information processing device as an image output device, a redundant function is mounted on the display device. Therefore, it is possible to reduce the number of parts and the circuit scale of the entire system, and it is possible to reduce the parts cost and thus the product cost.

As a method for realizing light deflection, there is a method in which light modulated by a light modulation element is transmitted through a parallel plate, and the parallel plate is deflected by tilting it using a motor or a piezoelectric element. In this method, parts to be used are inexpensive and can be easily deflected. However, this method has a great disadvantage that a driving sound is generated during use. For this reason, in this embodiment, a ferroelectric liquid crystal aligned perpendicularly to the holding substrate is used as the light deflection element.
The display device is a projection display device that uses three optical systems for color separation and synthesis and three light modulation elements for RGB. As shown in FIG. 11, a lamp in which an ultrahigh pressure mercury lamp 41 is combined with a parabolic reflector is used as the light source. In addition, a polarization conversion element 43 that aligns polarized light in one direction together with the integrator 42 is provided so that the light modulation portion of the light modulation element 20 is illuminated almost uniformly.
With such a configuration, the light that has passed through the integrator 42 and the polarization conversion element 43 is changed in direction by the mirror 44, and in accordance with the wavelength bands (corresponding to red, green, and blue, respectively) by the two dichroic mirrors 45 and 46. Reflect or transmit.
The light separated into each color is reflected by a PBS (polarization beam splitter) 47 and enters the light modulation element 20. The relay lens 48 in the drawing is for adjusting the optical path length of blue only with respect to the optical paths indicating green and red. In this way, the light modulated by the light modulation element 20 (the modulated light has a 90-degree polarized light rotation) passes through the PBS 47 and enters the light deflection element 49. Then, after being deflected by the light polarization element 49, it is projected onto the screen via the projection lens 50.
In the above description, the light deflection element 49 is a ferroelectric liquid crystal aligned perpendicular to the glass substrate (longitudinal direction in FIG. 12) sandwiching the liquid crystal layer. By applying an electric field, the state of the liquid crystal molecules transitions, and incident light having an optical axis in a direction perpendicular to the glass substrate is deflected according to the state of the liquid crystal molecules. The response speed is fast due to the use of ferroelectric liquid crystal. Further, since the deflection is performed according to the state of the liquid crystal aligned perpendicular to the substrate, the controllability of the deflection amount is good and the deflection can be made to a required position. Since there are no moving parts by using liquid crystal, quietness can be realized.
FIG. 12 shows a cross-sectional view of the optical deflection element 49 with respect to the optical axis. As shown in the figure, a liquid crystal 51, a glass substrate 52, an alignment film 53, an electrode 54 for applying an electric field, and the like are provided. Incident light is shifted to first or second emission light depending on the state of the liquid crystal 51. Incident light and outgoing light are parallel. FIG. 13 shows the state of the liquid crystal. The two-direction shift shown in FIG. 13 is realized according to the orientation state as shown.
In this optical deflection element 49, one element realizes a horizontal or vertical shift. Therefore, in this embodiment, two elements whose shift directions are orthogonal to each other are used.
Thus, in this embodiment, by using the ferroelectric liquid crystal vertically aligned on the light deflecting element, the controllability by the electric signal can be improved and a good image can be obtained, and the deflection without generating the operation sound can be obtained. realizable. Further, FIG. 1 enables division into four subframes as described in the first embodiment.
The case where there are four subframes has been described above, but there may be a plurality of subframes, and the number of subframes is not limited to four.

1 is a configuration block diagram of a main part of an image display system showing a first embodiment of the present invention. 1 is a circuit configuration diagram of a main part of an image display system showing a first embodiment of the present invention. The other block diagram of the image display system main part showing the first embodiment of the present invention. The other circuit block diagram of the image display system principal part which shows the 1st Example of this invention. The other block diagram of the image display system main part showing the first embodiment of the present invention. Explanatory drawing of the principal part of an image display system which shows the 2nd Example of this invention. The block diagram of the configuration of the main part of the image display system showing a second embodiment of the present invention. The operation | movement flowchart of the image display system principal part which shows the 2nd Example of this invention. The block diagram of the main part of the image display system showing the fourth embodiment of the present invention. The block diagram of the configuration of the main part of the image display system showing the fifth embodiment of the present invention. The block diagram of the principal part of the image display system which shows the 6th Example of this invention. The block diagram of the optical deflection | deviation element which shows the 6th Example of this invention. Explanatory drawing of the optical deflection | deviation element which shows the 6th Example of this invention. 1 is a diagram for explaining the main part of an image processing system according to a first embodiment of the present invention. FIG. 5 is another relationship diagram for explaining the main part of the image processing system according to the first embodiment of the present invention. FIG. 5 is another relationship diagram for explaining the main part of the image processing system according to the first embodiment of the present invention.

DESCRIPTION OF SYMBOLS 1 1st division circuit 2 2nd division circuit 3 2nd division circuits 4-7 Frame memory 8 Frame buffer 9 Sub-frame division part 10 Image processing circuits 11-13 Demultiplexer 14 Control circuit 15 Input / output control circuit 16 Address signal generation circuit 17 Address decoder 20 Light modulation element 21, 22 3-state buffer 24 CPU
31 Image control unit 33 Drawing engine 37 Font ROM
39 Expansion RAM
41 addition circuit 49 light deflection element 51 liquid crystal 52 glass substrate 54 electrode

Claims (1)

Image data dividing means for dividing image data for one frame to be displayed in association with a plurality of subframes, and modulated light modulated by image data for each image data divided by the image data dividing means In an image display system in which each sub-frame is displayed in a time-sharing manner at a corresponding position of the frame by deflecting the light using an optical deflection element,
An image processing circuit that performs image processing of each subframe data for each subframe, and performs image processing for each subframe in parallel processing ;
A plurality of memories for holding the subframes;
An address decoder for providing a common address to the plurality of memories;
An input / output control circuit for controlling input / output of the subframes of the plurality of memories;
An image display system comprising:

Images