JP2006038996A - Image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display an image of high resolution by a low-cost pixel shifting method using the image transferred, by dividing one image used for high-resolution displaying, into a plurality of divided images. <P>SOLUTION: Each image information of divided images 1 to 4, into which one frame image is divided, is decomposed and arranged on pixel positions of corresponding subframes 1 to 4 respectively and subframe images 1 to 4 are formed. By performing time division display in a light modulating element using the subframe images 1 to 4, an image division method used for the high-resolution displaying is adjusted to the pixel shift method. Thereby, the image of high resolution is displayed by the low-cost pixel shifting method using the image transferred by dividing one image used for high resolution displaying, into the plurality of divided images. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image display apparatus capable of displaying a frame image having more than the number of pixels of a light modulation element by deflecting an irradiation direction of light modulated by the light modulation element with a light deflection element.

  According to Japanese Patent Laid-Open No. 2004-228867, a method for increasing the resolution by shifting an image is disclosed for interlaced display in which display is performed by alternately switching even-numbered and odd-numbered scanning lines. Interlace displays adjacent scanning lines alternately, so that each corresponding interlace image can be shifted and displayed to increase the resolution.

  According to Patent Documents 2, 3 and the like, a light modulation element (image display element) that spatially modulates illumination light based on image information and emits it as image light, and the light modulation element synchronized with the light modulation element. There has been proposed an image display device including an optical deflection element that deflects the optical path of image light incident from each of the pixels and increases the apparent number of pixels of the light modulation element for display (hereinafter referred to as appropriate). "Pixel shift method").

Japanese Patent No. 2939826 JP 2003-241163 A JP 2004-53994 A

  In recent years, the display capacity of image display devices has been increasing. For example, a liquid crystal display device of QUXGA-W (resolution 3840 × 2400) is commercially available. In such an image display device with high resolution, since the signal frequency is high, the screen (frame image) is generally divided and transferred in parallel as divided images. Actually, in a QXGA (resolution 2048 × 1536) liquid crystal display device, the screen is divided into four parts and transferred. As a screen dividing method in this case, there are, for example, a method of dividing into four in a square shape, a method of dividing into four vertically long strips, and the like.

  Here, the case where high resolution display like QUXGA-W is implement | achieved by the above-mentioned patent document system etc. is considered. For example, in order to display QUXGA-W (resolution 3840 × 2400) by interlacing as in Patent Document 1, it is necessary to use an element having a number of pixels of 3840 × 2400 as a light modulation element. This is the same number of elements as a commercially available QUXGA-W liquid crystal display device. On the other hand, according to the pixel shift method disclosed in Patent Documents 2 and 3 and the like, display with a resolution higher than the resolution (number of pixels) of the light modulation element is realized by lower frequency driving by time-division display of the subframe image. Is. Therefore, for example, when display is performed in four time-divided subframes, a pixel shift type light modulation element of QUXGA-W (resolution 3840 × 2400) is disclosed as 1920 × 1200 1 This can be realized with an element having a pixel number of / 4. Generally, the yield decreases as the number of pixels increases, and the manufacturing cost increases as the number of pixels increases and the product increases. It can be seen that it is extremely advantageous in terms of cost to increase the resolution by using a shift type light modulation element.

  However, in an image display device with higher resolution, it is common to divide a screen and transfer image information as a divided image as described above. The screen division method originally does not consider application to the pixel shift method, and the image information for each subframe image is dispersed and mixed in each divided image, so it matches the light modulation element of the pixel shift method do not do. Therefore, simply, a high-resolution display can be performed on a low-cost pixel shift image display device using an image transferred by dividing one screen used for high-resolution display into a plurality of divided images. There is a problem that cannot be done.

  An object of the present invention is to perform high-resolution display by a low-cost pixel shift method using an image transferred by dividing one screen used for high-resolution display into a plurality of divided images.

  The invention described in claim 1 includes a light modulation element that has a plurality of pixels and spatially modulates illumination light based on image information for each pixel and emits the light as image light, and is incident from each pixel of the light modulation element. A light deflection element that deflects the optical path of the incoming image light in synchronization with the spatial light modulation of the light modulation element, and sub-frame images corresponding to positions deflected by the light deflection element are time-divided to modulate the light An image display device that displays a frame image that is equal to or more than the number of pixels of the light modulation element by displaying on the element, and that receives an image input unit that receives a plurality of divided images obtained by dividing one frame image as an input image, Subframe image creating means for decomposing each piece of image information of the divided image received by the image input unit and arranging the image information on the pixel position of the corresponding subframe to create the subframe image. .

  According to a second aspect of the present invention, in the image display device according to the first aspect, the image input unit includes a first storage element that individually stores a plurality of divided images that are divided and input in parallel. The sub-frame image creation means reads out the image information of each of the divided images stored in the first storage element in an order corresponding to the pixel position on the original frame image, reads each corresponding sub-frame image Readout means for creating the sub-frame image by disposing it on the pixel position.

  According to a third aspect of the present invention, in the image display device according to the second aspect of the present invention, the image display device further includes a second storage element that stores the sub-frame image created by the reading unit.

  According to a fourth aspect of the present invention, in the image display device according to the first aspect, the sub-frame image creating means decomposes each piece of image information for each of the divided images and assigns a plurality of divided subs for corresponding sub-frame allocation. Divided subframe image creating means for creating a frame image; and synthesizing means for creating the subframe image by synthesizing the plurality of generated divided subframe images for the same subframe allocation.

  According to a fifth aspect of the present invention, in the image display device according to the fourth aspect, the synthesizing unit includes a third storage element that stores the plurality of divided subframe images created by the divided subframe image creating unit. The sub-frame images are read out and synthesized in the order corresponding to the positions of the divided images on the original frame image from the plurality of divided sub-frame images assigned to the same sub-frame stored in the third storage element. Reading means for generating

  According to a sixth aspect of the present invention, in the image display device according to the fifth aspect, the third storage element is a plurality of first-in first-out (FIFO) memories.

  According to a seventh aspect of the present invention, in the image display device according to any one of the first to sixth aspects, an image processing means for performing image processing on each of the divided images is provided before the subframe image creating means. Prepare.

  The invention according to claim 8 is the image display device according to claim 7, wherein the image processing means performs image processing individually in parallel for each of the plurality of divided images that are divided and input in parallel. Do.

  According to a ninth aspect of the present invention, in the image display device according to the seventh or eighth aspect, the image processing is resolution conversion processing.

  According to a tenth aspect of the present invention, in the image display device according to any one of the first to ninth aspects, the light deflection element sandwiches a liquid crystal composed of a chiral smectic C phase having homeotropic alignment with a translucent substrate. An element that includes a liquid crystal panel and deflects light by adjusting a voltage applied to the liquid crystal.

  According to the first aspect of the present invention, each image information of the divided image obtained by dividing one frame image into screens is decomposed and arranged on the pixel positions of the corresponding subframes to create subframe images. Since the image is displayed on the light modulation element in a time-division manner, the screen division method used for high-resolution display can be matched with the pixel shift method, and thus one screen used for high-resolution display is divided into a plurality of divisions. High resolution display can be performed by a low-cost pixel shift method using an image divided and transferred.

  According to the second aspect of the present invention, the divided image is temporarily stored in the first storage element, and the read operation is controlled so that each subframe reads the necessary image information from the first storage element in the required order. A subframe image can be easily created from the divided images simply by doing so.

  According to the third aspect of the present invention, since the created subframe image is stored in the second storage element, the layout processing for creating the subframe image and the time division display of the subframe image are performed. Asynchronous processing can be performed, and it is not necessary to perform layout processing at the timing required for display, and the circuit scale for layout processing in the creation unit can be reduced, which can be realized at low cost.

  According to the fourth aspect of the present invention, when a divided image is decomposed to create a sub-frame image, a divided sub-frame image is created once for each divided image, and the divided sub-frame images are synthesized. Thus, it is possible to create a subframe image by performing parallel processing on the divided images that are divided and input in parallel, and the operation speed of the circuit required for these processes can be reduced.

  According to the fifth aspect of the present invention, since the created divided subframe image is temporarily stored in the third storage element, the divided subframe image necessary for each subframe is divided from the third storage element into the divided image. A sub-frame image can be easily created from the divided images simply by controlling the reading operation so that the reading is performed in the order corresponding to the positions.

  According to the sixth aspect of the present invention, since the FIFO memory capable of asynchronously writing and outputting is used as the third memory element, the number of control signals can be reduced and further cost reduction can be realized.

  According to the seventh and ninth aspects of the present invention, after the image processing is performed on the divided image, the decomposition / arrangement processing for creating the sub-frame image is performed. Image processing such as resolution conversion for performing image processing can be performed easily and appropriately, the circuit scale of the image processing means can be reduced, and further cost reduction can be realized.

  According to the eighth aspect of the present invention, since image processing is performed individually and in parallel for each divided image, the image processing can be performed using a circuit, IC, or the like dedicated to image processing. There is no need to design a dedicated processing part.

  According to the tenth aspect of the present invention, since the liquid crystal composed of a chiral smectic C phase having homeotropic alignment is used as a component of the optical deflection element, the optical deflection element capable of controlling the deflection amount by the amount of voltage applied. Therefore, the deflection amount can be easily controlled, and the peripheral circuits necessary for the control can be greatly reduced.

  The best mode for carrying out the present invention will be described.

[First embodiment]
FIG. 1 is a conceptual diagram showing an overall configuration of an image display device 1 according to the present embodiment. As shown in FIG. 1, the light source 2 can use various illuminations that turn on / off white light or an arbitrary color light at high speed. For example, an LED lamp, a laser light source, or a device combining a white lamp light source with a shutter. The illumination device 3 is a device that uniformly irradiates the light modulation element 4 with the light emitted from the light source 2, and includes a diffusion plate 5, a condenser lens 6, and the like.

  The light modulation element 4 includes a plurality of pixels, is driven by the display drive circuit 13 to display an image based on image information, and spatially modulates the incident uniform illumination light of the illumination device 3 to be emitted as image light. For example, a transmissive liquid crystal light valve, a reflective liquid crystal light valve, or a DMD element can be used.

  The light emitted from the light source 2 under the control of the light source driving circuit 7 becomes illumination light made uniform by the diffusion plate 5, and critical illumination is performed on the light modulation element 4 by the condenser lens 6. Here, a transmissive liquid crystal light valve is used as an example of the light modulation element 4. The illumination light spatially modulated by the light modulation element 4 is enlarged by the projection lens 8 and projected onto the screen 9 as image light.

  The reduction optical element 10 reduces the display pixel of the light modulation element 4 and includes a microlens, a collimator lens, and the like. It is desirable that the reduction amount is 1 / integer of the pixel pitch.

  Here, the applied voltage is controlled by the light deflection voltage control circuit 12 with respect to the light deflection element 11 disposed behind the light modulation element 4 and the reduction optical element 10, so that the image light can be arbitrarily set in the pixel arrangement direction. Shifted by distance. As shown in FIG. 1, the pixel shift directions are the vertical direction of the paper surface and the vertical direction of the paper surface. The arrangement position of the light deflection element 11 is arranged at the defocus position of the pixel displayed by the light modulation element 4 so that the resolution of the display image is not deteriorated. The pixel shift amount by the light deflecting element 11 is desirably an integral number of the pixel pitch, similarly to the reduction amount by the reduction optical element 10, and when the shift amount and the reduction amount are equal, the shifted pixels do not overlap. . Therefore, the resolution is not lowered by the effect of pixel shift. In addition, when the shift amount and the reduction amount are different, the shifted pixels overlap each other or cause the resolution to be lowered due to widening between pixels. However, if there is no problem in the display image, the shift amount and the reduction amount are reduced. The amounts need not be equal. When performing image multiplication twice as much as the pixel arrangement direction, the pixel pitch is set to 1/2. When performing pixel multiplication of 3 times, the pixel pitch is set to 1/3. When the shift amount increases due to the configuration of the optical deflection voltage control circuit 12, the shift amount and the pixel reduction amount may be set to a distance of "integer multiple + 1 / integer" of the pixel pitch. In any case, the light modulation element 4 is driven by the image signal of the subframe corresponding to the pixel shift position, and an apparent pixel multiplication effect is obtained as shown in FIG. A high-definition and high-contrast image higher than the resolution can be displayed. In FIG. 2, the shift amount and the pixel pitch are indicated by arrows. Reference numeral 21 denotes one pixel displayed by the light modulation element 4, reference numeral 22 denotes one pixel incident on the light deflection element 11, and reference numeral 23 denotes a pixel that is apparently multiplied by the light deflection element 11.

  The image display control circuit 14 controls the light source drive circuit 7, the display drive circuit (light modulation element control circuit) 13, and the light deflection voltage control circuit 12 to synchronize the light modulation element 4 and the light deflection element 11.

  In addition, examples of the configuration of the optical deflection element for realizing such an operation are known from the above-described Patent Documents 2 and 3 and the like, and are exemplified in the embodiments described later, and thus detailed description thereof is omitted here. To do.

  Therefore, according to the image display device 1 of the present embodiment, basically, one screen is displayed by a pixel shift method in a time-division display of a plurality of subframe images, and has a high definition and good contrast that is higher than the resolution of the light modulation element 4. An image is displayed. A display method based on this time division will be described with reference to schematic diagrams shown in FIGS. Here, an example in which display is performed with a resolution that is four times as many pixels as the light modulation element 4 is used. Accordingly, the four pixels adjacent in the vertical and horizontal directions are displayed on the light modulation element 4 in a time-division manner in the clockwise direction, for example, as shown in FIG. 3, such as pixel 1 → pixel 2 → pixel 3 → pixel 4 → pixel 1. (This also applies to subframes.) As a result, 1 for displaying all pixels of one frame (one screen) simultaneously at the time of pixel 1, 2 for simultaneously displaying at the time of pixel 2, 3 for simultaneously displaying at the time of pixel 3, As shown in FIG. 4, when the pixel 4 is displayed at the same time, it is separated for each pixel in the scanning line (horizontal direction), and the same separation method is repeated by skipping one scanning line in the vertical direction. Will be. Considering a subframe image, a collection of pixel information indicated by 1 constitutes image information of subframe 1, and a collection of pixel information indicated by 2 constitutes image information of subframe 2. A collection of pixel information shown in FIG. 4 constitutes image information of subframe 3, and a collection of pixel information shown in 4 constitutes image information of subframe 4. By displaying the light modulation element 4 in a divided manner, the entire frame image is displayed with high definition.

  According to such a principle, for example, if the pixel shift type light modulation element 4 of the present embodiment is used for QUXGA-W (resolution 3840 × 2400), as described above, as the light modulation element 4, It can be seen that this can be realized with an element having a 1/4 pixel number of 1920 × 1200.

  Under such circumstances, in this embodiment, one frame image (one screen) is input as a plurality of divided images, for example, divided images 1 to 4 that are divided into four in a square shape as shown in FIG. So that you can deal with it. In this example, as described above, it is assumed that QUXGA-W is realized by the image display device 1 including the light modulation element 4 having 1920 × 1200 pixels. The number of pixels of 4 matches the number of pixels of one divided image.

  In the present embodiment, basically, a plurality of divided images obtained by dividing one frame image (one screen) as an input image are received, each piece of image information of the received divided images is decomposed, and corresponding subframes are respectively received. A sub-frame image is created by arranging the pixels on the pixel position, and the created sub-frame images are sequentially displayed on the light modulation element in a time-division manner. An example of a basic configuration for performing the processing related to the arrangement on the subframe from the decomposition of the divided images will be described with reference to a schematic block diagram shown in FIG. This portion is included in the image display control circuit 14, for example.

  First, an image input unit 31 that receives a plurality of divided images obtained by dividing one frame image (one screen) as an input image from an external host machine or the like is provided. The image input unit 31 has a control signal (vertical synchronization signal, horizontal synchronization signal, clock signal, etc.) indicating the position on the screen (position on the frame image) of the image signal and the pixels constituting the image with respect to the received information on the divided image. ). The image signal is stored in a FIFO (First In First Out) 33 as a memory included in the image input unit 31 under the control of the FIFO control unit 32 based on the control signal (FIFO 33 in FIG. 6). For the sake of convenience, the FIFO 33 is shown outside the image input unit 31). The FIFO has a function of outputting image signals in the input order, and performs writing / output asynchronously. The image information stored as one image in the FIFO 33 is decomposed for each pixel in accordance with a predetermined rule in the demultiplexer 34 under the control of the arrangement control unit 35, and each of the four subframes 1 to 4 (36a to 36a to 36a) The sub-frame images 1 to 4 are generated by placing the pixel on the pixel position 36d). Here, four FIFOs 1 to 4 (37a to 37d) are prepared for each of the subframes 1 to 4 (36a to 36d), and the subframe images 1 to 4 created under the control of the FIFO control unit 38 are Stored in the four FIFOs 1 to 4 (37a to 37d). The four subframe images 1 to 4 stored in the FIFOs 1 to 4 (37a to 37d) are sequentially read out in a time division manner by the multiplexer 39 in synchronization with the control signal for the light modulation element 4, and output to the light modulation element 4. As a result, the subframe images 1 to 4 are displayed on the light modulation element 4 in a time-sharing manner. Here, the demultiplexer 34 and the arrangement control unit 35 constitute subframe image creation means 40.

  Here, the circuit diagram shown in FIG. 7 respectively shows an example of the configuration of the demultiplexer 34 for decomposing the image information for each pixel according to a predetermined rule and arranging it on the subframe and the timing example of the control signal used. 8 and the timing chart shown in FIG. First, as shown in FIG. 8 and FIG. 9, the control signal 1 is a pixel unit signal that switches H / L at the rising edge of the clock signal (switches between H level and L level for each image data), control Signal 2 is a signal for each scanning line whose H / L is switched at the rising edge of a horizontal synchronizing signal (not shown) (the H level and the L level are switched for each scanning line). That is, the control signal 1 is a signal for decomposing the pixel 1 and the pixel 2 or the pixel 3 and the pixel 4 on the same scanning line, and the pixel 3 and the pixel 4 are the pixel 4 in the scanning line direction, H / L switching is set so that the pixels 3 are decomposed in the order. The control signal 2 is a signal for decomposing the pixels 1 and 2 and the pixels 3 and 4 in the vertical direction. The demultiplexer 34 is configured by a combination of a plurality of logic gate elements 41 that separate and output the image data input from the FIFO 33 as outputs 1 to 4 in units of pixels by the control signals 1 and 2. In this case, the outputs 1 to 4 are for subframes 1 to 4, respectively, and the subframe images 1 to 4 are created by arranging the image data on the corresponding pixel positions in the order of output. Is done.

  In FIG. 6, as the storage element, a combination using a memory controller for asynchronously writing / reading using DRAM and SDAM, an image processing memory called a multi-port RAM, and the like can be used. In this embodiment, a FIFO is used. By using the FIFO in this way, it is possible to reduce the number of control signals for controlling the pixel-by-pixel disassembly / arrangement and the asynchronous operation of the display using the subframes 1 to 4 in order, thereby reducing the area on the substrate used for wiring. In addition, it is possible to reduce the size and cost of the peripheral circuit used for control by reducing the circuit scale and the number of parts.

  Here, various control signals used here will be described in detail. First, since the FIFO 33 provided in the image input unit 31 can perform writing and reading asynchronously, as a control signal given from the image input unit 31 to the FIFO control unit 32, writing to the FIFO 33 is controlled. For example, a clock corresponding to a pixel, a reset signal for resetting a pointer for writing every frame and starting writing, a write enable signal for controlling writing / stopping, etc., and an input image signal The write operation to the FIFO 33 is controlled. The arrangement control unit 35 instructs the FIFO control unit 32 to output image data for one pixel to the FIFO 33. In accordance with this instruction, image data for one pixel is output from the FIFO 33, and from the pixel position (scan line position and pixel position on the scan line) in the frame image (one screen) to which the image data is input, The arrangement control unit 35 determines in which subframe the image data is included. The arrangement control unit 35 outputs control signals 1 and 2 for switching whether the demultiplexer 34 is input to the FIFOs 1 to 4 (37a to 37d) corresponding to the subframes 1 to 4, respectively. In parallel with this, clocks and write enable signals for writing to the corresponding FIFOs 1 to 4 (37a to 37d) are output to the FIFOs 1 to 4 (37a to 37d) via the FIFO control unit 38.

  On the other hand, the light modulation element 4 basically modulates the reflectance or transmittance of the corresponding pixel according to the input data by inputting image data for each subframe. In this case, a signal for controlling output / stop of one subframe image for the light modulation element 4 to display one frame to the light modulation element 4 is transmitted from the control unit 14 to the FIFO control unit 38 for the light modulation element 4. Is output. Similarly, a control signal for switching by the multiplexer 39 from which FIFO 1 to 4 (37a to 37d) the signal (subframe image) is displayed on the light modulation element 4 is transmitted from the control unit 14 to the light modulation element 4. 39. The switching operation of the multiplexer 39 is performed every time one subframe image is displayed.

  Therefore, basically, by dividing each image information by the demultiplexer 34 based on such a principle for each of the divided images 1 to 4 and arranging them on the pixel positions of the corresponding subframes 1 to 4, respectively. Each of the subframe images 1 to 4 can be created, and image display can be performed by a pixel shift method in which the subframe images 1 to 4 are displayed in a time division manner with respect to the input of the divided images 1 to 4. This point will be described with reference to a schematic diagram shown in FIG. First, even if the input divided image is divided, the image data for each pixel is arranged in the order in which the divided image is displayed as a single image. In FIG. 10, among these pixels, those belonging to subframe 1 displayed in time division are circled numerals 1, and similarly, those belonging to subframe 2 displayed in time division are circled numerals 2. In addition, a thing belonging to the subframe 3 displayed by time division is shown as a circled numeral 3, and a thing belonging to the subframe 4 displayed by time division is shown as a circled numeral 4. When performing display in time division, display is performed in the order of subframe 1 → subframe 2 → subframe 3 → subframe 4 → subframe 1... And uses the deflection of the optical deflection element 11 in synchronization with this display. The display position is shifted and displayed.

  Therefore, from the divided images 1 to 4 shown in FIG. 10, it can be seen that the pixels to be displayed on the same subframe image are dispersed and mixed in the divided images 1 to 4. Therefore, the subframe image 1 is created by collecting the image data of the pixels 1 belonging to the subframe 1 on the subframe 1 by the demultiplexer 34 sequentially from the divided images 1 to 4. Similarly, the subframe image 2 is created by collecting the image data of the pixels 2 belonging to the subframe 2 sequentially from the divided images 1 to 4 on the subframe 2 by the demultiplexer 34, and sequentially from the divided images 1 to 4. The subframe image 3 is created by collecting the image data of the pixels 3 belonging to the subframe 3 on the subframe 3 by the demultiplexer 34, and the image data of the pixels 4 belonging to the subframe 4 are sequentially obtained from the divided images 1 to 4. The sub-frame image 4 is created by collecting on the sub-frame 4 by the demultiplexer 34.

  A more practical configuration example of the present embodiment based on such a principle will be described with reference to FIG. First, according to the present embodiment, four image inputs each having individual FIFOs 33a to 33d as first storage elements that individually store four divided images 1 to 4 that are input in parallel by dividing one frame image. The image input unit 31 is configured by the units 31a to 31d. For each of the FIFOs 33a to 33d in the image input units 31a to 31d, the stored pieces of image information of the divided images 1 to 4 are decomposed in the order corresponding to the pixel positions on the original frame image before division. Then, four switching circuits 1 to 4 (51a to 51d) constituting reading means for creating frame images 1 to 4 by arranging them on the pixel positions of the corresponding subframes 1 to 4 are individually provided. ing. Each of the switching circuits 1 to 4 (51a to 51d) has a configuration similar to that of the subframe image creation means 40 including the above-described demultiplexer 34 and the like, and each of the FIFOs 33a to 33d according to a predetermined rule as described with reference to FIG. The respective pieces of image information of the respective divided images 1 to 4 are decomposed in the order corresponding to the pixel positions on the original frame image before division and are read out and arranged on the corresponding pixel positions of the subframes 1 to 4.

  Therefore, according to such a configuration example, the divided images 1 to 4 are temporarily stored individually in the FIFOs 33a to 33d, and the image information necessary for the subframes 1 to 4 is required from the FIFOs 33a to 33d. The subframe images 1 to 4 can be easily created from the divided images 1 to 4 simply by controlling the reading operation by the switching circuits 1 to 4 (51a to 51d) so as to read them in order. Moreover, the process of decomposing and arranging the divided images 1 to 4 into the subframes 1 to 4 can be performed in parallel for each of the divided images 1 to 4, and the operation speed can be reduced.

  In this case, as shown in FIG. 12, the subframe images 1 to 4 are stored in the FIFOs 1 to 4 (37a to 37d), which are the second storage elements, respectively, and the subframe images 1 to 4 are stored in the FIFO1 to the multiplexer 39 by the multiplexer 39. 4 (37a to 37d), if it is read out and output in a time division manner, an arrangement process for creating subframe images 1 to 4 from the divided images 1 to 4 and time division display of the subframe images 1 to 4 will be described. Can be performed asynchronously, it is not necessary to perform layout processing at the timing required for display, the circuit scale for the layout processing in the subframe image creation means can be reduced, and it can be realized at low cost. be able to.

[Second Embodiment]
This embodiment basically conforms to the first embodiment described above, but introduces the concept of divided subframes in pixel decomposition / arrangement processing. The divided subframe is for creating a subframe from the divided image. For example, the subframe 1 created from the divided images 1 to 4 as shown in FIG. 13A is shown in FIG. As shown in the figure, among the pixel data constituting this subframe 1, those included in the divided image 1 are divided into subframes 11, those included in the divided image 2 are divided into subframes 12, and divided images. 3 includes a divided subframe 14, and a divided image 4 includes a divided subframe 13. The divided subframe 11 includes a set of these divided subframes 11 to 14. Other subframe 2
The same applies to -4.

  Therefore, in the present embodiment, as shown in FIG. 14, the stored image information of the divided images 1 to 4 is stored in the FIFOs 33a to 33d in the image input units 31a to 31d. A plurality of divided sub-frames 11 to 14, 21 to 24, 31 to 34, and 41 to 44 (61a to 61p) for subframes 1 to 4 assigned by being decomposed in the order corresponding to the pixel positions on the frame image. Four switching circuits 1 to 4 (62a to 62d) constituting divided subframe image creating means arranged on the top and creating divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44 are individually provided. Is provided. Each of the switching circuits 1 to 4 (62a to 62d) has a configuration similar to that of the subframe image creation means 40 including the above-described demultiplexer 34 and the like. These divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44 are followed by these divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44. Are provided in the predetermined order for the same subframe assignments to generate subframe images 1 to 4 (63a to 63d).

  FIG. 15 to FIG. 18 show the correspondence relationships between the frame image before division, the divided images 1 to 4, the divided subframe images 11 to 14, 21 to 24, 31 to 34 and 41 to 44, and the subframe images 1 to 4 in this case. It is shown in the schematic diagram. Here, for simplicity, the number of pixels in one frame is 8 × 8, and the number of pixels of the light modulation element 4 is 4 × 4.

  According to the present embodiment, when the divided images 1 to 4 are decomposed to generate the subframe images 1 to 4, the divided subframe images 11 to 14, 21 to 24, and 31 are once divided in units of the divided images 1 to 4. 34, 41 to 44 are created and these divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44 are combined. Sub-frame images 1 to 4 can be created by performing parallel processing on the divided images 1 to 4 and the operation speed of the circuit required for these processes can be reduced.

[Third embodiment]
This embodiment basically conforms to the second embodiment described above, but in this embodiment, as shown in FIG. 19, the divisions created by the switching circuits 1 to 4 (62a to 62d). FIFOs 65a to 65p are provided as third storage elements for storing the sub-frame images 11 to 14, 21 to 24, 31 to 34 and 41 to 44, respectively. The necessary subframe images 1 to 4 are created by controlling the reading order of the divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44 stored in the FIFOs 65a to 65p. It is what I did.

  According to the present embodiment, since the FIFO memories 65a to 65o capable of asynchronous writing / output are used as the third storage element, the number of control signals can be reduced, and further cost reduction can be realized. Also, an arrangement process for creating divided subframe images 11 to 14, 21 to 24, 31 to 34, and 41 to 44 from the divided images 1 to 4, and these divided subframe images 11 to 14, 21 to 24, 31. Can be performed asynchronously with the time-division display of the subframe images 1 to 4 based on .about.34, 41 to 44, and it is not necessary to perform the arrangement processing at the timing necessary for display, and the arrangement processing in the subframe image creating means. Therefore, it is possible to reduce the circuit scale for the purpose and to realize at a low cost.

[Fourth embodiment]
In the present embodiment, for example, in the configuration of FIG. 11 described above, as shown in FIG. 20, image processing circuits 1 to 4 (71 a to 71 d) as image processing means are provided for each of the divided images 1 to 4. The switching circuits 1 to 4 (51a to 51d) are provided in the previous stage. In these image processing circuits 1 to 4 (71a to 71d), a dedicated image processing circuit is used for each of the divided images 1 to 4, and each of the divided images 1 to 4 that are divided and input in parallel is individually provided. Are configured to perform image processing. In the present embodiment, resolution conversion processing for detecting and interpolating the resolution of an input image is performed as image processing. More practically, an IC for resolution conversion is used as the image processing circuits 1 to 4 (71a to 71d).

  According to the present embodiment, after the image processing is performed on the divided images 1 to 4 by the image processing circuits 1 to 4 (71a to 71d), the decomposition / placement processing for creating the subframe images 1 to 4 is performed. Therefore, it is possible to easily and appropriately perform image processing such as resolution conversion in which image processing is performed using information on adjacent pixels, and the circuit scale of the image processing circuits 1 to 4 (71a to 71d) is reduced. Therefore, further cost reduction can be realized. Moreover, since image processing is performed individually and in parallel for each of the divided images 1 to 4, the speed required for processing can be reduced and the number of pixels to be processed can be reduced as compared with the case of processing the entire screen. Image processing can be performed using a circuit dedicated to image processing, an IC (dedicated IC having a specific function), or the like, and it is not necessary to design the image processing portion of the image display device exclusively.

[Fifth embodiment]
This embodiment shows an application example for color image display as the pixel shift type image display apparatus 1 to which the input image processing as described above is applied. FIG. 21 is an explanatory diagram for explaining the configuration of such an image display apparatus 101. First, reflection type Liquid Crystal on Silicon (hereinafter referred to as LCOS) is used for the light modulation elements 4R, 4G, and 4B for RGB colors. As the light source 102, a lamp in which an ultrahigh pressure mercury lamp was combined with a parabolic reflector was used. Using the integrator 103 having the function of making the light uniform and the polarization conversion element 104 having the function of aligning the polarization in one direction, the light modulation portions of the light modulation elements 4R, 4G, and 4B are illuminated almost uniformly. It is configured as follows. As an optical system for performing color separation, the light that has passed through the integrator 103 and the polarization conversion element 104 is reflected by the mirror 105 into a plurality of colors by the blue reflecting dichroic mirror 106 and the green reflecting dichroic mirror 107, in this case, R, G, B 3 The light of each color is separated into three light modulation elements 4R through a predetermined optical system, here three PBSs 108R, 108G, 108B, a mirror 109, and a relay lens 110 for adjusting the optical path length. , 4G, 4B. The three light modulation elements 4R, 4G, and 4B are driven by the light modulation element control circuit 13 based on the R, G, and B image information constituting the original image, which is a color image, and each subframe image is driven. Illumination light is spatially modulated based on image information (the modulated light is rotated by 90 ° polarization) and emitted as image light. The emitted image light of the three colors is superimposed on the image light of one color image via a predetermined optical system, here, three PBSs 108R, 108G, and 108B, and the dichroic prism 111 for synthesis, and the light deflection element 11 and is projected onto the screen via the projection lens 112 for display.

  Here, a configuration example of the light deflection element 11 that is vertically aligned using ferroelectric liquid crystal will be described with reference to FIG. The light deflection element 11 according to the present embodiment deflects the optical axis in the horizontal direction on the paper surface. That is, by applying a voltage to the electrode 154, the state of the liquid crystal molecules of the liquid crystal layer 151 of the panel in which the liquid crystal layer 151 is sandwiched between the glass substrate 153 is changed, and the vertical direction (horizontal direction on the paper surface) with respect to the substrate 153 ) Incident light is deflected according to the state of the liquid crystal molecules. The outgoing light is parallel to the incident light.

  Since the light deflecting element 11 uses a ferroelectric liquid crystal, specifically, a liquid crystal composed of a chiral smectic C phase having homeotropic alignment, the response speed is high. Further, since the deflection is performed in the state of liquid crystal aligned perpendicular to the substrate 153, the controllability of the deflection amount is good and the deflection can be made to a necessary position. Of course, quietness can be realized by using liquid crystal because there are no moving parts. In FIG. 22, reference numeral 154 denotes an electrode for applying a voltage, and 152 denotes an alignment film. Incident light is shifted to first and second emission light depending on the state of the liquid crystal.

  FIG. 23 shows the alignment state of the liquid crystal. The shift in the two directions shown in FIG. 22 is realized according to this orientation state. As shown in FIG. 21, a single element achieves a horizontal or vertical shift. Further, as described above, in order to deflect the pixels 1 to 4 in the four directions, the two light deflection elements 11 whose shift directions are orthogonal to each other are used.

  Here, as an image signal input to the light modulation elements 4R, 4G, and 4B, a DVI signal obtained by dividing one screen (frame image) into four in a square shape is used. The four DVI signals that are input each output an image signal and a control signal (horizontal / vertical synchronization signal and clock signal) at the receiver (image input unit 31). The data is written in the FIFO 33, and is divided into subframes by the demultiplexer 34 having one input and four outputs used for the distribution circuit in the output order, and the outputs (subframe images 1 to 4) of the demultiplexer 34 are also sequentially stored in the FIFO1 to FIFO4. Since the control circuit for displaying on the LCOS used for display uses FIFOs 1 to 4, the subframe images 1 to 4 necessary for pixel shift can be displayed asynchronously at a necessary timing. It was.

  According to the present embodiment, since the liquid crystal composed of a chiral smectic C phase having homeotropic alignment is used as a constituent element of the optical deflection element 11, the optical deflection element can control the deflection amount by the amount of voltage applied. The deflection amount can be easily controlled, and the peripheral circuits required for the control can be greatly reduced.

  In these embodiments, the example of application to the divided images 1 to 4 divided in a square shape has been described as the divided image. However, in the case of a divided image divided into strips, or further divided Even when the numbers are different, the same can be applied.

1 is a conceptual diagram illustrating an overall configuration of an image display device according to a first embodiment of the present invention. It is explanatory drawing explaining the pixel shift by the optical deflection | deviation element of an image display apparatus. It is a schematic diagram which shows the principle of the time division display order by a pixel shift system. It is a schematic diagram which shows the principle of the time division display order by the pixel shift system about the whole screen. It is explanatory drawing which shows the form of the division | segmentation of a divided image. It is a schematic block diagram which shows the example of a fundamental structure of this Embodiment. It is a logic circuit diagram which shows the structural example of a demultiplexer. It is a timing chart which shows an example timing of a control signal etc. when control signal 2 is H level. It is a timing chart which shows an example timing of a control signal etc. when control signal 2 is L level. It is a schematic diagram which shows the correspondence of a divided image and a sub-frame image. It is a schematic block diagram which shows the more practical example of a structure of this Embodiment. It is a schematic block diagram which shows the modification. It is explanatory drawing for demonstrating the concept of a division | segmentation sub-frame regarding 2nd embodiment of this invention. It is a schematic block diagram which shows the structural example of this Embodiment. It is a schematic diagram which shows the example of a frame image before a division | segmentation. It is a schematic diagram which shows the aspect of the divided images 1-4. It is a schematic diagram which shows the aspect of the division | segmentation sub-frame images 11-44. It is a schematic diagram which shows the aspect of the sub-frame images 1-4. It is a schematic block diagram which shows the structural example of 3rd embodiment of this invention. It is a schematic block diagram which shows the structural example of the 4th Embodiment of this invention. It is a conceptual diagram which shows the whole structure of the image display apparatus of the 5th Embodiment of this invention. It is a fundamental block diagram which shows the optical deflection | deviation element using a liquid crystal. It is explanatory drawing which shows the orientation state of a liquid crystal.

Explanation of symbols

4 Light modulation element 11 Light deflection element 31 Image input unit 33 First storage element 37 Second storage element 40 Subframe image creation means 51 Readout means 62 Divided subframe image creation means 64 Composition means 65 Third storage element, FIFO memory 66 reading means 71 image processing means

Claims (10)

A light modulation element that has a plurality of pixels and spatially modulates illumination light based on image information for each pixel and emits it as image light, and an optical path of image light incident from each pixel of the light modulation element A light deflection element that deflects in synchronization with the spatial light modulation of the light modulation element, and displays the subframe image corresponding to the position deflected by the light deflection element on the light modulation element in a time division manner. An image display device that displays a frame image of the number of pixels of a modulation element or more,
An image input unit for receiving a plurality of divided images obtained by dividing one frame image as an input image;
Subframe image creation means for decomposing each piece of image information of the divided image received by the image input unit and placing the image information on pixel positions of the corresponding subframes to create the subframe image;
An image display device comprising: The image input unit includes a first storage element that individually stores a plurality of divided images that are divided and input in parallel.
The sub-frame image creation means reads out the image information of each of the divided images stored in the first storage element in an order corresponding to the pixel position on the original frame image, reads each corresponding sub-frame image Readout means for creating the subframe image by disposing it on a pixel position,
The image display device according to claim 1.   The image display device according to claim 2, further comprising a second storage element that stores the sub-frame image created by the reading unit.   The sub-frame image creating means decomposes each piece of image information for each divided image and creates a plurality of divided sub-frame images for sub-frame allocation corresponding to each divided image, and a plurality of generated sub-frame image creating means The image display apparatus according to claim 1, further comprising: a combining unit configured to combine the divided subframe images for the same subframe allocation to create the subframe image.   The synthesizing means includes a third storage element that stores the plurality of divided subframe images created by the divided subframe image creating means, and a plurality of same subframe assignments stored in the third storage element. 5. A reading means for generating the sub-frame image by reading and synthesizing the divided sub-frame images in an order according to the position of the divided image on the original frame image. Image display device.   6. The image display apparatus according to claim 5, wherein the third storage element is a plurality of first-in first-out (FIFO) memories.   The image display device according to claim 1, further comprising an image processing unit that performs image processing on each of the divided images before the sub-frame image generation unit.   The image display device according to claim 7, wherein the image processing unit individually performs image processing in parallel on each of the plurality of divided images that are divided and input in parallel.   The image display device according to claim 7, wherein the image processing is resolution conversion processing. The optical deflection element is an element that includes a liquid crystal panel in which a liquid crystal composed of a chiral smectic C phase having homeotropic alignment is sandwiched between translucent substrates, and deflects light by adjusting a voltage applied to the liquid crystal. The image display device according to claim 1, wherein the image display device is a display device.

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