JP4423471B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply that supplies power from a DC power supply to a load via a transformer, and more particularly to a switching power supply that can suppress switching loss with a simple configuration by a soft switching (zero voltage switching) system.

  Conventionally, in a switching power supply device that supplies power from a DC power supply to a load via a transformer, various devices have been made to improve the power factor and the waveform (see Patent Document 1).

FIG. 18 is a circuit diagram showing a configuration of a conventional switching power supply device.
In FIG. 18, a rectifier circuit 12 including diode bridges D1 to D6 is connected to input terminals 10 and 11 to which an AC power supply is input. In the transformer 13 of the switching power supply device, the first winding N1, the third winding N3, and the fourth winding N4 are provided on the primary side of the common iron core, and the secondary side to which the load is connected is the second side. Two windings N2 are provided. A third winding N3, a first winding N1, a main semiconductor switch Q1, and a resistor R1 of the transformer 13 are disposed between the cathodes of the diodes D1 and D2 serving as output terminals of the rectifier circuit 12 and the ground point. They are sequentially connected in series, and a diode D11 is connected in antiparallel to the main semiconductor switch Q1. Further, one end of a smoothing capacitor C1 is connected to the connection point between the fourth winding N4 and the first winding N1 of the transformer 13, and the other end is grounded. Furthermore, one end of the inductance L1 is connected to the input terminals 10 and 11 via diodes D3 and D4, and the other end is connected to a connection point between the first winding N1 of the transformer 13 and the main semiconductor switch Q1. Yes.

  A series circuit of the fourth winding N4 of the transformer 13, the diode D8, and the auxiliary semiconductor switch Q2 is connected in parallel to the main semiconductor switch Q1. One end of a snubber capacitor Cs is connected between the anode of the diode D11 and the drain of the main semiconductor switch Q1, and the other end of the snubber capacitor Cs is connected to the source of the main semiconductor switch Q1, the cathode of the diode D11, and the resistor R1. Connected to the connection point. On the other hand, a series circuit of a diode D7 and a capacitor C2 is connected to the second winding N2 of the transformer 13. From both ends of the capacitor C2, a DC voltage obtained by rectifying and smoothing a voltage generated on the second winding N2 side of the transformer 13 is supplied to a load (not shown) via output terminals 14 and 15.

  The control circuit 16 performs on / off control of the two semiconductor switches Q1 and Q2 based on the DC voltage value (feedback voltage Vcomp) supplied to the load, thereby setting the DC voltage value supplied to the load to a desired magnitude. It is intended to be controlled. The control circuit 16 includes a pulse-by-pulse operation block B1 that generates a pulse-by-pulse signal Dpp that limits the on-width of the semiconductor switches Q1 and Q2 according to the load state, and a drive timing that determines the on-off timing of the semiconductor switches Q1 and Q2. Block B2, an overcurrent detection block B3 that regulates the operation against continued overcurrent, and further sets the regulation grace period tdla, a latch block B4 for latch stop, and gate signals of the semiconductor switches Q1 and Q2 Driver block B5, and two OR gates OR1 and OR2 that connect the drive timing block B2 and the latch block B4 to the driver block B5.

FIG. 19 is a timing chart showing operation waveforms of a conventional switching power supply device.
As shown in FIG. 19, when the clock signal Clk is input to the drive timing block B2 of the control circuit 16, the clock signal Clk becomes H at time Ta, and as shown in FIG. 19B, the auxiliary semiconductor switch Q2 Turns on. Next, at the time Tb when the fixed time t1 has elapsed, the main semiconductor switch Q1 is turned on as shown in FIG. Next, at time Tc when the predetermined time t2 has elapsed, the auxiliary semiconductor switch Q2 is turned off. Thereafter, at time Td, the clock signal Clk becomes L, and the main semiconductor switch Q1 is also turned off.

  Since the two semiconductor switches Q1 and Q2 are grounded via the resistor R1, respectively, when these semiconductor switches Q1 and Q2 are turned on, a predetermined current flows through the resistor R1. The voltage Vr1 across the resistor R1 generated at that time is input to the pulse-by-pulse operation block B1 of the control circuit 16.

  At this time, in the pulse-by-pulse operation block B1, when the predetermined voltage Vpp set as the reference value is exceeded or the comparison voltage based on the feedback voltage Vcomp from the secondary side of the transformer 13 is exceeded, the load state The on widths of the semiconductor switches Q1 and Q2 corresponding to the above are limited (pulse-by-pulse operation). That is, when the both-end voltage Vr1 becomes larger than the predetermined voltage Vpp or the feedback voltage Vcomp, whichever is smaller, the pulse-by-pulse signal Dpp shown in FIG. 19C is output to the drive timing block B2. In the drive timing block B2, normally, the semiconductor switches Q1 and Q2 are turned on at the timing set by the delay elements T1 and T2, and the drive signals GD1 and GD2 are transmitted through the OR gates OR1 and OR2 and the driver block B5, respectively. It is supplied to the gates of the switches Q1 and Q2. However, when the pulse-by-pulse signal Dpp is detected here, the drive signals GD1, GD2 to the two semiconductor switches Q1, Q2 are both stopped.

  Further, the voltage Vr1 across the resistor R1 is also input to the overcurrent detection block B3, and if there is an input exceeding the predetermined voltage Voc (where Voc ≦ Vpp) set as the overcurrent detection level in this overcurrent detection block B3. The overcurrent detection signal Doc shown in FIG. 19 (d) is generated. Then, the overcurrent detection signal Doc is repeatedly generated within a certain operation regulation time toc, and the latch signal Dlat is supplied as the set signal S to the latch block B4 when the overcurrent detection signal Doc continues for a certain regulation grace period tdla. When the output signal Q is output as the drive stop continuation signal Dflt in the latch block B4, the drive signals GD1 and GD2 are both stopped by the drive stop continuation signal Dflt, and the semiconductor block Q1 and Q2 are not turned off in the driver block B5. Can hold state.

  The signal input to the latch block B4 is not the overcurrent detection signal Doc but the latch signal Dlat. The overcurrent detection signal Doc is continuously at the H level during the fixed regulation grace period tdla. For the first time, the latch block B4 is latched. That is, the timing of the set signal S to the latch block B4 is delayed by the regulation grace period tdla to latch the latch block B4. Here, the purpose of setting the regulation grace period tdla in the first place is that the voltage Vr1 across the resistor R1 exceeds the overcurrent detection level (predetermined voltage Voc) over a certain time continuously or intermittently. In the current operation state, the power supply is protected by stopping and holding the output of the switching power supply device. In the single overcurrent operation, the output is limited by the pulse-by-pulse operation. However, a separate short-circuit detection block may be provided in order to stop and hold the output against a very large overcurrent such as a load short circuit.

  FIG. 20 is a timing chart showing operation waveforms of the entire conventional switching power supply device. Here, the switching control operation of the conventional switching power supply device will be described by dividing one cycle of the clock signal Clk shown in FIG.

  In the period I, as indicated by the Q1 on signal GD1 and the Q2 on signal GD2 in FIGS. 2B and 2C, the main semiconductor switch Q1 is off and the auxiliary semiconductor switch Q2 is on. A current path as shown in FIG. 21 is formed. Before turning on the main semiconductor switch Q1, the auxiliary semiconductor switch Q2 is turned on, and the electric charge of the snubber capacitor Cs is discharged through the fourth winding N4 of the transformer 13 (FIG. 20 (f)). The fourth winding N4 is excited with the polarity of the arrow shown in FIG. 21 because the snubber capacitor Cs is used as the power source here.

At this time, since the first winding N1 and the fourth winding N4 of the transformer 13 constitute one winding of the transformer 13, the first winding N1 also has a back electromotive force with the polarity shown in FIG. The voltage Vn1 is generated, the exciting current In1 flows, and the electric charge of the snubber capacitor Cs is regenerated to the electrolytic capacitor C1 through the first winding N1. About this excitation current (regenerative current) In4,
(Number of turns of N4) × In4 = (Number of turns of N1) × In1
The relationship holds. The period during which the exciting current In4 flows is determined by the leakage inductance of the fourth winding N4 and the first winding N1 and the snubber capacitor Cs.

  In the period II, a current path as shown in FIG. 22 is formed in the switching power supply device. When the voltage of the snubber capacitor Cs becomes zero, the main semiconductor switch Q1 is turned on, and the main semiconductor switch Q1 enters a zero voltage / zero current switching state. At this time, the voltage of the electrolytic capacitor C1 is applied to the first winding N1, and the second winding N2, the third winding N3, and the fourth winding N4 of the transformer 13 are respectively shown in FIG. Back electromotive voltages Vn2, Vn3, and Vn4 are generated at the polarities of the arrows. Therefore, the excitation current In4 of the auxiliary semiconductor switch Q2 decreases due to the back electromotive voltage Vn4. When the exciting current In4 becomes zero, the auxiliary semiconductor switch Q2 is turned off, and the auxiliary semiconductor switch Q2 enters a zero voltage / zero current switching state. Since the excitation current In4 is stored as the excitation energy of the transformer 13 in the period I, when the main semiconductor switch Q1 is turned on, the excitation current In1 flows with an initial value corresponding to the excitation energy.

  In the period III, a current path as shown in FIG. 23 is formed in the switching power supply device. When the main semiconductor switch Q1 is turned off, the excitation current In1 flows into the snubber capacitor Cs, so that the main semiconductor switch Q1 is switched to zero voltage, and the excitation energy stored in the transformer 13 is released from the second winding N2. When the sum of the voltage Vn3 generated in the third winding N3 and the voltage applied between the input terminals 10 and 11 becomes larger than the voltage Vc1 across the electrolytic capacitor C1 (input voltage + Vn3> Vc1), the third winding N3 Current flows through At this time, a voltage (Vc1 + Vn1) is applied to the main semiconductor switch Q1, and a voltage (Vc1 + Vn1 + Vn4) is applied to the auxiliary semiconductor switch Q2.

  During this period III, vibration is generated by the leakage inductance of the snubber capacitor Cs and the first winding N1, and the oscillating current In1 flows through the first winding N1. For this reason, the oscillating currents In2 and In3 also flow through the second winding N2 and the third winding N3 of the transformer 13 due to the influence of the oscillating current In1. In addition, a current can flow through the inductance L1 regardless of the voltage Vc1 across the electrolytic capacitor C1. In the figure, Q2 breakdown voltage is the breakdown voltage (breakdown voltage) of the auxiliary semiconductor switch Q2.

In the period IV, a current path as shown in FIG. 24 is formed in the switching power supply device. When the discharge of the excitation energy stored in the transformer 13 from the second winding N2 and the third winding N3 of the transformer 13 is completed, resonance starts with the snubber capacitor Cs and the excitation reactor of the first winding N1.
JP 2003-70249 A (paragraph numbers [0010] to [0037])

FIG. 25 is a timing chart showing operation waveforms at the time of avalanche rush in the conventional switching power supply device.
In the above-described switching power supply device, in the normal operation shown in FIG. 20, immediately after the auxiliary semiconductor switch Q2 is turned on, the closed loop formed of the series circuit of the fourth winding N4 of the transformer 13, the diode D8, and the auxiliary semiconductor switch Q2 is used. After the current is consumed, the main semiconductor switch Q1 is turned on.

  However, when the load has a very low impedance, a short-circuit current flows through the load. That is, when the main semiconductor switch Q1 is turned on when the excitation current In4 is positive as shown in FIG. 25 while the auxiliary semiconductor switch Q2 is turned on and the current is flowing in the closed loop, the pulse-by-pulse operation is performed immediately thereafter. Thus, the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2 are simultaneously turned off, and at that moment, a jumping voltage is applied to the auxiliary semiconductor switch Q2 by the back electromotive voltage Vn4 generated in the fourth winding N4.

  Therefore, the drain-source voltage Vds2 of the auxiliary semiconductor switch Q2 exceeds the breakdown voltage, and in the worst case, the semiconductor switch has an avalanche operation.

  The present invention has been made in view of such a point, and even when the load is very low impedance so that the voltage applied to the auxiliary semiconductor switch may suddenly rise, the overcurrent detection is performed. By holding the auxiliary semiconductor switch in the OFF state, the voltage applied to the auxiliary semiconductor switch can be suppressed, and even if the drain-source voltage of the semiconductor switch is the highest, the drain-source voltage of the auxiliary semiconductor switch is broken down. It is an object of the present invention to provide a switching power supply device that does not reach an avalanche operation beyond a voltage.

  In the present invention, in order to solve the above problem, in a switching power supply that supplies power from a DC power supply to a load via a transformer, a main semiconductor switch connected in series to the first winding of the transformer; A snubber capacitor connected in parallel to the semiconductor switch, an auxiliary semiconductor switch that discharges the charge of the snubber capacitor by turning on before the main semiconductor switch is turned on, and an overcurrent flowing through the load is detected A control circuit for switching the main semiconductor switch and the auxiliary semiconductor switch to an OFF state and controlling the supply of power to the load to be stopped when the overcurrent is continuously detected beyond a predetermined regulation grace period; The control circuit generates an overcurrent detection signal when the overcurrent is detected, thereby generating a predetermined value. Switching power supply apparatus is provided, characterized in that only the movement limiting time so as to hold the off-state of the auxiliary semiconductor switch.

  According to the present invention, it is possible to suppress the voltage applied to the auxiliary semiconductor switch when the load has a very low impedance, such as when the load is short-circuited or started. Therefore, the selection range of MOSFETs used as semiconductor switches in the switching power supply device is widened. For example, MOSFETs with low breakdown voltage can be used. Further, since the on-resistance is lowered, the loss can be improved. In addition, even if the drain-source voltage of the semiconductor switch is the highest, the auxiliary semiconductor switch can be prevented from reaching avalanche operation, so a simple power supply circuit can be configured without adding a protective element, and the mounting area can be reduced. There are also effects such as reduction.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a switching power supply device according to the first embodiment of the present invention.

  In FIG. 1, a rectifier circuit 12 including diode bridges D1 to D6 is connected to input terminals 10 and 11 to which AC power is input, as in the switching power supply device of FIG. Between the output terminal of the rectifier circuit 12 (the cathodes of the diodes D1 and D2) and the ground point, the third winding N3, the first winding N1, the main semiconductor switch Q1, and the resistor R1 of the transformer 13 are sequentially connected in series. The diode D11 is connected in antiparallel to the main semiconductor switch Q1, and the snubber capacitor Cs is connected in parallel. The fourth circuit N4 of the transformer 13, the diode D8, and the auxiliary semiconductor switch Q2 are connected in series. Are connected in parallel. One end of a smoothing capacitor C1 is connected to the connection point between the fourth winding N4 and the first winding N1 of the transformer 13, and the other end is grounded. In addition, one end of an inductance L1 is connected to the input terminals 10 and 11 via diodes D3 and D4, and the other end is connected to a connection point between the first winding N1 of the transformer 13 and the main semiconductor switch Q1. Yes.

  Similarly to the conventional device described with reference to FIG. 18, the source of the main semiconductor switch Q1 and the source of the auxiliary semiconductor switch Q2 include one end of the resistor R1, the pulse-by-pulse operation block B1 of the control circuit 16, and the overcurrent detection. Block B3 is connected. The difference from the conventional apparatus of FIG. 18 is that in the control circuit 16, the overcurrent detection block B3 is connected not only to the latch block B4 but also to the drive timing block B2.

  That is, an AND gate G1 is provided on the input side of the drive timing block B2, and the pulse-by-pulse signal Dpp and the clock signal Clk from the pulse-by-pulse operation block B1 are input thereto. The output of the AND gate G1 is input to the AND gates G2 and G3 and the delay elements T1 and T2, respectively, and the delay signal Dt1 from the delay element T1 is input to the AND gate G2 and the delay element T2, respectively. The delay signal Dt2 from the delay element T2 is inverted and input to the AND gate G3. The overcurrent detection signal Doc of the overcurrent detection block B3 is further inverted and input to the AND gate G3. Drive signals GD1 and GD2 which are inverted outputs of the AND gates G2 and G3 are supplied to the driver block B5 via the OR gates OR1 and OR2, respectively.

  The driver block B5 of the control circuit 16 comprises semiconductor switches Q11, Q12 and Q13, Q14 (CMOS inverters) of different conductivity type MOSFETs, and the driver block B5 drives the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2. B5 and drive timing block B2 are connected. Note that MOSFETs are used for the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2.

FIG. 2 is a timing diagram showing signal waveforms in the pulse-by-pulse operation block.
FIG. 4A shows the feedback voltage Vcomp input to the pulse-by-pulse operation block B1, and FIG. 4B shows the predetermined voltage Vpp set in the pulse-by-pulse operation block B1. In this pulse-by-pulse operation block B1, the pulse-by-pulse operation is executed with the voltage Vcomp being the first comparison voltage and the predetermined voltage Vpp being the second comparison voltage with respect to the voltage Vr1 across the resistor R1. That is, at the timing when the both-end voltage Vr1 input to the pulse-by-pulse operation block B1 becomes larger than the first comparison voltage Vcomp or becomes larger than the predetermined voltage Vpp as the second comparison voltage, the pulse-by-pulse signal Dpp is Output.

FIG. 3 is a timing diagram showing signal waveforms in the drive timing block.
FIG. 2A shows a clock signal Clk having a constant period and a constant duty. Here, since the delay signals Dt1 and Dt2 are output at the timings shown in (c) and (d) at the timing when the pulse-by-pulse signal Dpp shown in (b) is not generated, the clock signal Clk The drive signal GD2 rises at the timing when becomes H level ((f) in the figure), and the drive signal GD1 rises after t1 ((e) in the figure). Further, after the elapse of t2, the drive signal GD2 becomes L level, and the drive signal GD1 also becomes L level at the timing when the clock signal Clk becomes L level.

  When the pulse-by-pulse signal Dpp is generated at the timing shown in FIG. 3B, the drive timing block B2 operates to switch the drive signals GD1 and GD2 to the off state.

FIG. 4 is a timing chart showing signal waveforms in the overcurrent detection block.
FIG. 5A shows the voltage Vr1 across the resistor R1 input to the overcurrent detection block B3. FIG. 4B shows an overcurrent detection signal generated in synchronization with the voltage Vr1 across the resistor R1. Doc is shown. In this overcurrent detection block B3, a predetermined operation restriction time toc is set, and when the re-input of the both-end voltage Vr1 is not detected within this operation restriction time toc, the overcurrent detection signal Doc returns to the L level. If the re-input is repeated at the operation restriction time toc, the latch signal Dlat is output as shown in FIG. With this latch signal Dlat, the operation stop state in which the semiconductor switches Q1 and Q2 are not turned on can be held by forming the drive stop continuation signal Dflt in the latch block B4 described next.

FIG. 5 is a timing chart showing signal waveforms in the latch block.
FIG. 4A shows the latch signal Dlat supplied as the set signal S to the latch block B4, and FIG. 4B shows the reset signal R held at the H level. Here, as shown in FIG. 6C, once the set signal S has the H level latch signal Dlat, the drive stop continuation signal Dflt, which is the output signal Q, is fixed at the H level. The drive stop continuation signal Dflt fixed at the H level is set to the L level when the L level is subsequently input as the reset signal R or when the power supply of the latch block B4 falls below the latch holding voltage (Vlat). Return. In the switching power supply device, one of the procedures is selected according to the purpose of the power supply function.

Next, the operation of the switching power supply device configured as described above will be described.
FIG. 6 is a timing chart showing operation waveforms of the switching power supply device of FIG.
During the steady operation, as already described in the conventional device of FIG. 20, the auxiliary semiconductor switch Q2 is turned on → (t1 elapsed) → main semiconductor switch Q1 is turned on → (t2 elapsed) → auxiliary semiconductor switch Q2 is turned off → main semiconductor switch Q1. A turn-off procedure is performed.

  Further, in the pulse-by-pulse operation block B1, as shown in the signal waveform diagram of FIG. 2, when the voltage Vr1 across the resistor R1 becomes greater than or equal to the predetermined voltage Vpp or the feedback voltage Vcomp, the value shown in FIG. A pulse-by-pulse signal Dpp shown in (c) is output. At that time, if the gate signal of either the main semiconductor switch Q1 or the auxiliary semiconductor switch Q2 is on (H level), as shown in FIGS. 6A and 6B, the drive signal GD1 , GD2 are forcibly set to L level to turn off the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2. In addition, since the overcurrent detection signal Doc shown in FIG. 6D is continued for the set operation regulation time toc after the overcurrent is detected, the voltage applied to the auxiliary semiconductor switch Q2 can be suppressed, Even when the source-to-source voltage increases most, the auxiliary semiconductor switch Q2 can be prevented from reaching an avalanche operation.

FIG. 7 is a timing chart showing operation waveforms of the entire switching power supply device of FIG.
Here, as shown in FIG. 5G, an overcurrent is detected when the both-end voltage Vr1 is equal to or higher than a predetermined voltage Voc that is an overcurrent detection level, and an overcurrent detection signal Doc is output for a set operation regulation time toc. Is done. That is, the auxiliary semiconductor switch Q2 is not turned on only during that period. As a result, the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 can be suppressed, and even when the drain-source voltage rises most, the auxiliary semiconductor switch Q2 can be prevented from reaching an avalanche operation.

  As described above, in the switching power supply according to the first embodiment, when the overcurrent is detected in the control circuit 16, the overcurrent detection signal Doc is generated, so that the auxiliary semiconductor switch Q2 is operated for the predetermined operation regulation time toc. Was kept off. Therefore, the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 can be suppressed, and even when the drain-source voltage rises most, it can be prevented that the avalanche operation is reached.

(Second Embodiment)
FIG. 8 is a circuit diagram showing a configuration of a control circuit in the switching power supply device according to the second embodiment of the present invention.

  Although not shown here, the rectifier circuit 12 including the diode bridges D1 to D6 is connected to the input terminals 10 and 11 to which the AC power is input, similarly to the switching power supply device in the first embodiment. Between the output terminal of the rectifier circuit 12 (the cathodes of the diodes D1 and D2) and the ground point, the third winding N3, the first winding N1, the main semiconductor switch Q1, and the resistor R1 of the transformer 13 are sequentially connected in series. The diode D11 is connected in antiparallel to the main semiconductor switch Q1. One end of a smoothing capacitor C1 is connected to the connection point between the fourth winding N4 and the first winding N1 of the transformer 13, and the other end is grounded. In addition, one end of an inductance L1 is connected to the input terminals 10 and 11 via diodes D3 and D4, and the other end is connected to a connection point between the first winding N1 of the transformer 13 and the main semiconductor switch Q1. Yes.

  The control circuit 16 of FIG. 8 is different from the first embodiment in that a start-time stop block B6 is connected to the drive timing block B2 in addition to the conventional device described in FIG. That is, an output voltage Vout to a load connected to the output terminals 14 and 15 is fed back to the start stop block B6, and the start stop signal Dst detected here is provided on the output side of the drive timing block B2. Inverted and input to the AND gate G3.

FIG. 9 is a timing chart showing signal waveforms in the stop block at startup.
The startup stop block B6 is configured to generate the startup stop signal Dst shown in FIG. 5B until the rated voltage is reached during startup when the output voltage Vout gradually rises from zero. Has been.

FIG. 10 is a timing chart showing operation waveforms of the switching power supply device of FIG. FIG. 11 is a timing chart showing operation waveforms of the entire switching power supply device of FIG.
During the steady operation, as described with reference to FIG. 20 in the conventional apparatus, the auxiliary semiconductor switch Q2 is turned on → (t1 elapsed) → main semiconductor switch Q1 is turned on → (t2 elapsed) → auxiliary semiconductor switch Q2 is turned off → main semiconductor switch Q1 is turned off. The procedure is executed. Further, the pulse-by-pulse operation in the pulse-by-pulse operation block B1 and the overcurrent detection in the overcurrent detection block B3 are also conventional.

  As shown in FIG. 10 and FIG. 11, the auxiliary semiconductor switch Q2 is not turned on during the period when the startup stop signal Dst is output. As shown in FIG. 11, the switching power supply as a whole can suppress the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 when the load at the time of startup is very low impedance. Even when the voltage rises most, the auxiliary semiconductor switch Q2 is prevented from reaching an avalanche operation.

  As described above, in the switching power supply according to the second embodiment, the auxiliary semiconductor switch Q2 can be kept in the off state at the start-up time when the load has a very low impedance. The transient voltage applied between the drain and source of Q2 can be suppressed, and even when the drain-source voltage rises most, the avalanche operation can be prevented.

(Third embodiment)
FIG. 12 is a circuit diagram showing a configuration of a control circuit in the switching power supply device according to the third embodiment of the present invention.

  In the control circuit 16 shown in FIG. 12, in the control circuit 16 of the switching power supply device shown in the first embodiment, a startup stop block B6 is further connected to the drive timing block B2. That is, the start-time stop signal Dst of the start-time stop block B6 and the overcurrent detection signal Doc of the overcurrent detection block B3 are respectively input to the AND gate G4 of the drive timing block B2, and the inverted logic output thereof is the AND gate G3. Has been entered.

FIG. 13 is a timing chart showing operation waveforms of the switching power supply device of FIG. FIG. 14 is a timing chart showing operation waveforms of the entire switching power supply device of FIG.
During the steady operation, as described in FIG. 20 in the conventional apparatus, the auxiliary semiconductor switch Q2 is turned on → (t1 elapsed) → the main semiconductor switch Q1 is turned on → (t2 elapsed) → the auxiliary semiconductor switch Q2 is turned off → the main semiconductor switch Q1 is turned off. The procedure is executed. Further, the pulse-by-pulse operation in the pulse-by-pulse operation block B1 and the overcurrent detection in the overcurrent detection block B3 are also conventional.

  As shown in the schematic waveform in FIG. 13, the auxiliary semiconductor switch Q2 is not turned on during the period when the start-time stop signal is output and the overcurrent detection signal is output. As shown in FIG. 14, the entire switching power supply operation is a period during which the start-time stop signal Dst is output, and when the both-end voltage Vr1 is equal to or higher than a predetermined voltage Voc that is an overcurrent detection level, The overcurrent detection signal Doc is output for the set operation regulation time toc. That is, the auxiliary semiconductor switch Q2 is not turned on only during that period. As a result, the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 can be suppressed, and even when the drain-source voltage rises most, the auxiliary semiconductor switch Q2 can be prevented from reaching an avalanche operation.

  As described above, in the switching power supply according to the third embodiment, the auxiliary semiconductor switch Q2 can be kept in the OFF state at the start-up time when the load has a very low impedance. By generating an overcurrent detection signal Doc when a current is detected, the auxiliary semiconductor switch Q2 is kept off for a predetermined operation regulation time toc. Therefore, by turning off the auxiliary semiconductor switch Q2, the voltage applied thereto can be suppressed, and even when the drain-source voltage rises most, the avalanche operation can be prevented.

(Fourth embodiment)
FIG. 15 is a circuit diagram showing a configuration of a control circuit in the switching power supply device according to the fourth embodiment of the present invention.

  In the control circuit 16 shown in the figure, the pulse-by-pulse signal Dpp of the pulse-by-pulse operation block B1 is supplied not only to the AND gate G1 of the drive timing block B2, but also to the delay element T2.

FIG. 16 is a timing chart showing operation waveforms of the switching power supply device of FIG.
During the steady operation, as described with reference to FIG. 20 in the conventional apparatus, the auxiliary semiconductor switch Q2 is turned on → (t1 elapsed) → main semiconductor switch Q1 is turned on → (t2 elapsed) → auxiliary semiconductor switch Q2 is turned off → main semiconductor switch Q1 is turned off. The procedure is executed. Further, the overcurrent detection operation in the overcurrent detection block B3 is the same as the conventional one.

  In the pulse-by-pulse operation in the pulse-by-pulse operation block B1, the voltage Vr1 across the resistor R1 exceeds a predetermined voltage Vpp set as a reference value, or a comparison based on the feedback voltage Vcomp from the secondary side of the transformer 13 When the voltage is exceeded, a pulse-by-pulse signal Dpp is output, and if either the main semiconductor switch Q1 or the auxiliary semiconductor switch Q2 is turned on (H level), it is forcibly turned off (L level). Thus, the main semiconductor switch Q1 or the auxiliary semiconductor switch Q2 is turned off. This pulse-by-pulse operation is as described in the conventional apparatus. However, as shown in the schematic waveform in FIG. 16, when the pulse-by-pulse signal Dpp is output before the auxiliary semiconductor switch Q2 is turned off and the on-time of the main semiconductor switch Q1 becomes less than t2, at that time Since the drive signals GD1 and GD2 to the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2 are turned off (L level), the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2 are turned off, and the auxiliary semiconductor switch Q2 is turned off only for a desired period. Continue to maintain state.

FIG. 17 is a timing chart showing operation waveforms of the entire switching power supply device of FIG.
As the operation of the entire switching power supply device, as shown in FIG. 5G, the voltage Vr1 across the resistor R1 becomes larger than the first comparison voltage Vcomp or a predetermined voltage Vpp which is the second comparison voltage. If the above is satisfied, the pulse-by-pulse signal Dpp is output, and when the on-time of the main semiconductor switch Q1 becomes less than t2, the auxiliary semiconductor switch Q2 is turned on until the auxiliary semiconductor switch Q2 is turned on next. Held off. As a result, the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 can be suppressed, and even when the drain-source voltage rises most, the auxiliary semiconductor switch Q2 can be prevented from reaching an avalanche operation.

  As described above, in the switching power supply according to the fourth embodiment, when the main semiconductor switch Q1 is switched to the off state at the same time as the auxiliary semiconductor switch Q2 in less than a predetermined on period by detecting an overcurrent, Next, the auxiliary semiconductor switch Q2 is kept off for a predetermined period until the main semiconductor switch Q1 is turned off.

  Therefore, when the main semiconductor switch Q1 and the auxiliary semiconductor switch Q2 are turned off by the pulse-by-pulse signal Dpp before the auxiliary semiconductor switch Q2 in steady operation is turned off, the off state of the auxiliary semiconductor switch Q2 is maintained for a desired period. As a result, the voltage applied between the drain and source of the auxiliary semiconductor switch Q2 can be suppressed, and even when the drain-source voltage rises most, the avalanche operation can be prevented.

1 is a circuit diagram showing a configuration of a switching power supply device according to a first embodiment of the present invention. It is a timing diagram which shows the signal waveform in a pulse-by-pulse operation block. It is a timing diagram which shows the signal waveform in a drive timing block. It is a timing diagram which shows the signal waveform in an overcurrent detection block. It is a timing diagram which shows the signal waveform in a latch block. FIG. 2 is a timing chart showing operation waveforms of the switching power supply device of FIG. 1. FIG. 2 is a timing chart showing operation waveforms of the entire switching power supply device of FIG. 1. It is a circuit diagram which shows the structure of the control circuit in the switching power supply apparatus which concerns on the 2nd Embodiment of this invention. It is a timing diagram which shows the signal waveform in the stop block at the time of starting. FIG. 9 is a timing chart showing operation waveforms of the switching power supply device of FIG. 8. FIG. 9 is a timing chart showing operation waveforms of the entire switching power supply device of FIG. 8. It is a circuit diagram which shows the structure of the control circuit in the switching power supply device which concerns on the 3rd Embodiment of this invention. FIG. 13 is a timing chart showing operation waveforms of the switching power supply device of FIG. 12. FIG. 13 is a timing chart showing operation waveforms of the entire switching power supply device of FIG. 12. It is a circuit diagram which shows the structure of the control circuit in the switching power supply apparatus which concerns on the 4th Embodiment of this invention. FIG. 16 is a timing chart showing operation waveforms of the switching power supply device of FIG. 15. FIG. 16 is a timing chart showing operation waveforms of the entire switching power supply device of FIG. 15. It is a circuit diagram which shows the structure of the conventional switching power supply apparatus. It is a timing diagram which shows the operation | movement waveform of the conventional switching power supply device. It is a timing diagram which shows the operation | movement waveform of the whole conventional switching power supply device. It is operation | movement explanatory drawing in the period I in the conventional switching power supply apparatus. It is operation | movement explanatory drawing in the period II in the conventional switching power supply device. It is operation | movement explanatory drawing in the period III in the conventional switching power supply apparatus. It is operation | movement explanatory drawing in the period IV in the conventional switching power supply apparatus. It is a timing diagram which shows the operation | movement waveform at the time of avalanche rush in the conventional switching power supply device.

Explanation of symbols

10, 11 Input terminal 12 Rectifier circuit 13 Transformer 14, 15 Output terminal 16 Control circuit B1 Pulse-by-pulse operation block B2 Drive timing block B3 Overcurrent detection block B4 Latch block B5 Driver block B6 Stop block at startup C1, C2 Capacitor Cs Snubber capacitor D1 to D8, D11, D12 Diode L1 Inductance N1 to N4 Winding (1st winding to 4th winding)
Q1 Main semiconductor switch Q2 Auxiliary semiconductor switch Q11 to Q14 Semiconductor switch R1 Resistance

Claims (4)

In a switching power supply that supplies power from a DC power supply to a load via a transformer,
A main semiconductor switch connected in series to the first winding of the transformer;
A snubber capacitor connected in parallel to the main semiconductor switch;
An auxiliary semiconductor switch that discharges the electric charge of the snubber capacitor by turning on the main semiconductor switch before turning on;
When an overcurrent flowing through the load is detected, the main semiconductor switch and the auxiliary semiconductor switch are switched to an off state, and when the overcurrent is continuously detected beyond a predetermined regulation grace period, power to the load is switched to A control circuit for controlling the supply to stop;
With
The switching power supply device according to claim 1, wherein the control circuit maintains an off state of the auxiliary semiconductor switch for a predetermined operation regulation time by generating an overcurrent detection signal when the overcurrent is detected. In a switching power supply that supplies power from a DC power supply to a load via a transformer,
A main semiconductor switch connected in series to the first winding of the transformer;
A snubber capacitor connected in parallel to the main semiconductor switch;
An auxiliary semiconductor switch that discharges the charge of the snubber capacitor by turning on the main semiconductor switch before turning on;
When an overcurrent flowing through the load is detected, the main semiconductor switch and the auxiliary semiconductor switch are switched to an OFF state, and when the overcurrent is continuously detected over a predetermined regulation grace period, power to the load is switched to A control circuit for controlling the supply to stop;
With
The switching power supply device according to claim 1, wherein the control circuit maintains the off state of the auxiliary semiconductor switch until the voltage of the load reaches a predetermined level at the start of power supply.   3. The control circuit according to claim 2, further comprising: generating an overcurrent detection signal when the overcurrent is detected, thereby maintaining the off state of the auxiliary semiconductor switch for a predetermined operation regulation time. The switching power supply device described. In a switching power supply that supplies power from a DC power supply to a load via a transformer,
A main semiconductor switch connected in series to the first winding of the transformer;
A snubber capacitor connected in parallel to the main semiconductor switch;
An auxiliary semiconductor switch that discharges the charge of the snubber capacitor by turning on the main semiconductor switch before turning on;
When an overcurrent flowing through the load is detected, the main semiconductor switch and the auxiliary semiconductor switch are switched to an OFF state, and when the overcurrent is continuously detected over a predetermined regulation grace period, power to the load is switched to A control circuit for controlling the supply to stop;
With
In the control circuit, when the main semiconductor switch is switched to an OFF state simultaneously with the auxiliary semiconductor switch in less than a predetermined ON period due to the detection of the overcurrent, a predetermined period until the main semiconductor switch is turned OFF next A switching power supply device characterized in that the off state of the auxiliary semiconductor switch is maintained only for a period.

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