JP4421280B2 - Data processing apparatus and data processing method - Google Patents

Description

  The present invention relates to a data processing apparatus and a data processing method, and more particularly, to a data processing apparatus and a data processing method for classifying input data according to a predetermined rule, and outputting the data after shaping the data based on the classification result.

  For example, in the technical field that handles variable-length packet data used for TCP / IP, etc., so-called shaping processing is performed in which each packet data is classified for each destination and processed into a format suitable for transmission for each destination. Is done. That is, for example, as shown in FIG. 1, a process is performed in which the switch 120 distributes packet data that arrives in a high-speed serial format (for example, the state shown in FIG. 2A) for each of a plurality of transmission destinations. Such processing is normally performed after the received high-speed serial data is once converted into low-speed parallel data. In this case, since the packet data has a variable length, the parallelizing unit 110 not only performs simple serial / parallel conversion, but also uses parallel data obtained by serial / parallel conversion as it is as shown in FIG. A so-called shaping process is performed for conversion into a format that can be separated for each destination for each clock.

  This shaping process is a process for collecting data of the same destination for each clock for sending data. That is, in the state of FIG. 2B, only the same destination data is always present at the same time. In FIG. 2, uppercase alphabets A, B, C, D, etc. indicate destinations, and lowercase alphabets a, b, c, d, etc. are sent to destinations A, B, C, D, respectively. Indicates the data to be output. Each downward arrow at the top of FIG. 2B indicates each data processing cycle defined by the reference clock.

  In this case, for example, as shown in FIG. 3, after data conversion by the serial / parallel converter 111, the data is once stored in a memory 114 such as a RAM and then shaped. Before and after the memory 114, a write processing unit 112 and a read processing unit 115 are provided. In this configuration, the shaping process is performed by the write processing unit 112 for the memory 114.

  In this case, for example, as shown in FIG. 4B, if there is only one packet destination in one cycle, as shown in FIG. 4B, as shown in FIG. ) As it is. That is, in this case, only the data a having the destination A is included in the second cycle of the parallelized data shown in FIG. 4B, so that it is stored in the second storage area of the memory 114. On the other hand, if the destination of a packet existing in one cycle is divided into two as in the third cycle shown in FIG. 4 (b), it is divided into two areas of the memory as shown in FIG. 4 (c). Store. That is, in this case, the data a having the destination A and the data b having the destination B are mixed in the third cycle of the parallelized data shown in FIG. Are stored in the third and fourth storage areas, respectively.

By dividing and storing in this way, the reading side 115 of the memory 114 only needs to read the data stored in the memory sequentially, so that a very simple configuration can be adopted. Note that the cause of the phenomenon as described above, that is, the phenomenon that data having different destinations coexist in the same cycle is caused by the variable length of the packet data. That is, as shown in FIG. 2A and FIG. 4A, each data packet, that is, data a having destination A, data b having destination B, data c having destination C, etc. It has a packet length. For this reason, when this is simply parallelized, if the above shaping process is not performed, as shown in FIG. 4 (b), depending on the processing cycle, data having different destinations may exist in the same cycle.
JP 2003-174475 A

  For example, when short packets such as data c, d, and e having destinations C, D, and E in the example shown in FIG. 4 arrive continuously, division of writing as shown in FIG. Storage processing will occur frequently. As a result, an extra time is required for the writing process, and an event may occur in which the writing process to the memory 114 is longer than the arrival time of the actual data. That is, in the example shown in FIG. 4, it takes 12 cycles to store packet data that arrives in 10 cycles.

  Usually, in order to avoid such a situation, as shown in FIG. 3, a buffer 113 having a certain capacity for holding excess data that could not be written is provided on the writing side. However, even when the buffer 113 is provided in this way, if short packets arrive continuously, the buffer 113 may overflow in a short period of time. In order to completely avoid such a situation, it is theoretically necessary to make the storage capacity of the buffer 113 infinite. However, this is impossible, so when the buffer 113 having a finite storage capacity is provided, as a result However, when short packets arrive continuously, there is a possibility of causing packet loss without being able to cope with it.

  In the present invention, in order to solve the above problem, the first storage means for storing the input data and the input data stored in the first storage means are read out and classified according to a predetermined rule, and sequentially for each classification. Second storage means for writing in a predetermined storage unit is provided, and the first storage means has a larger storage capacity than the second storage means.

  As described above, in the present invention, the capacity of the first storage means for storing input data first is made larger than that of the second storage means provided between the shaping processing unit. As a result, the input data is temporarily stored in the first storage means having a relatively large capacity. Therefore, it is possible to effectively reduce the possibility of packet loss at the data reception stage.

  In addition, since the data stored in the first storage means is sequentially read out and written in different storage units of the second storage means for each predetermined classification, the subsequent shaping process can be made more efficient. As a result, even if processing delay occurs due to frequent occurrence of short packets as described above at the stage of shaping the data once stored in the first storage means through the second storage means, packet loss occurs due to it. This possibility can be effectively reduced.

  Furthermore, when the shaping process cannot catch up with the data input due to frequent occurrences of short packets and the like, an overflow of the second storage means is likely to occur, the reading from the first storage means is temporarily interrupted, and the shaping process during that time In the stage where the storage capacity of the second storage means has been increased as the process proceeds, the data last written to the second storage means is traced back to the reading position when it was read from the first storage means. It is possible to resume reading from the first storage means. As a result, occurrence of packet loss can be prevented more effectively.

  Even in this case, since the storage capacity of the first storage means is relatively large as described above, the first storage means can serve as a buffer. In other words, when reading from the first storage means is interrupted as described above, no new free space can be generated in the first storage means. Therefore, the first storage means consumes its free space unilaterally by writing input data, and as a result, its free space gradually decreases. However, by setting the capacity of the first storage means to be large in advance, even if such a situation occurs that the free capacity is consumed unilaterally, the capacity of the first storage means will eventually be exhausted. It is possible to effectively secure the time until the occurrence.

  According to the embodiment of the present invention, in a packet data exchange device having a function of temporarily storing packet data in a buffer, shaping it according to destination, and outputting it, a large capacity memory is provided as a buffer in the first stage, By using a two-stage configuration in which a small-capacity buffer composed of a flip-flop or the like is provided at the second stage, packet loss can be effectively prevented.

  The meaning of the term “packet loss” is as follows. That is, for example, in the configuration of FIG. 3, when the received packet data parallelized by the serial / parallel converter 111 is written to the large-scale memory 114 by the writing unit 112, the reading unit 115 causes a delay in shaping processing at that time. Assume that the reading speed from the memory 114 cannot keep up. In such a case, the free data capacity of the memory 114 gradually becomes insufficient, and as a result, the received data packet that cannot be written is temporarily stored in the buffer 113. However, when the above-mentioned state of insufficient free space in the memory 114 is not solved, the buffer 113 itself that temporarily stores received packet data that could not be written to the memory 114 is short of free space. Can occur. In such a case, for example, in order to protect the data already stored in the memory 114 and the buffer 113, it may be necessary to discard the newly received packet data in the writing unit 112. A phenomenon in which received packet data is discarded due to such a cause is referred to as packet loss.

  The above description is only an example. In addition to this, there is insufficient free space in the buffer memory provided in the middle due to a mismatch between the reception speed of packet data and the subsequent processing speed. There may be various situations in which some data must be discarded. The phenomenon in which packet data is discarded due to these situations can be collectively referred to as packet loss.

  In the embodiment of the present invention, in the packet data exchange apparatus having the packet shaping function, the past read position of the first-stage memory is stored in advance, and the read-out is performed according to the time when the second-stage buffer is likely to overflow. The packet loss is prevented in advance by stopping reading and restarting reading back to this reading position.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 5 is a block diagram of a data processing apparatus according to an embodiment of the present invention. The apparatus configuration shown in FIG. 5 has, for example, the above-described functions of parallelizing received packets in the high-speed serial state (110), shaping them according to their destinations (120), and further serializing and sending each destination (130). In the packet data exchange apparatus, it can be applied as means 110 for parallelizing packet data received in a serial format.

  The data processing apparatus shown in FIG. 5 includes a serial / parallel converter 11, a large-scale memory (RAM) 13, a writing unit 12 that writes parallelized packet data to the memory 13, and a read that reads packet data from the memory 13. And a read address holding unit 14 for holding and storing a read address in the memory 13 when data is read from the memory 13 by the reading unit 15.

  The data processing apparatus shown in FIG. 5 further includes a small buffer 16 having a plurality of storage areas for storing packet data read from the memory 13 by the reading unit 15 for each destination. Each of the small buffers 16 may be configured by an independent storage device for each of the storage areas to be written, or by using a means for dividing and managing one storage device, the plurality of storage areas are apparently a plurality of independent storage devices. You may implement | achieve as a structure utilized as a storage device, ie, a storage surface.

  The data processing apparatus shown in FIG. 5 further includes a read shaping unit 17 that reads data from the storage surface of each small buffer 16 and performs a shaping process for facilitating the sequential transmission for each destination as described above.

  FIG. 6 is a diagram for explaining how the packet data parallelized by the serial / parallel conversion unit 11 is written in the memory 13 by the writing unit 12. The data shown in FIG. 6A is similar to the data shown in FIG. That is, in this case, when writing to the memory 13, the divided storage for each destination as described with reference to FIG. 4C is not performed, and the parallelized data for 10 cycles is directly written in the storage area for 10 words. Therefore, in the state written in the memory 13, for example, in each of the third, fifth, and sixth words, data having different destinations are mixed in one word.

  By writing to the memory 13 in this way, the processing speed is not substantially delayed at the time of writing, and unlike the case of FIG. 4C, the storage capacity of the memory 13 can be used to the maximum. . Therefore, when the memory 13 is viewed as a buffer, the function can be effectively utilized.

  As described above, in the embodiment of the present invention, the packet data shaping process (17) is performed on the reading side rather than the writing side of the memory 13, and the buffer 16 formed of a small-size flip-flop is provided for further packet shaping. ing. Further, the data after the parallel conversion is written in the memory 13 as it is, and is read out as it is (15). In this case, each storage surface constituting the small-scale buffer 16 provided on the reading side has a capacity enough to store data read from the memory 13 once (one cycle) at maximum.

  Here, as will be described later with reference to FIG. 7, if all the data read from the memory 13 for each word on the reading side of the memory 13 belong to the same packet, that is, have the same destination, there are a plurality of storage surfaces. All are stored in the surface of one buffer 16. On the other hand, if the data read out for each word spans a plurality of packets, that is, has a plurality of different destinations, the data is divided into the storage surfaces of the plurality of buffers 16 and stored. The read shaping unit 17 determines the information of the data stored in the buffer 16, performs processing such as combining packet data stored in the surfaces of the plurality of buffers 16, shapes the packet data, and then performs downstream processing. To the side.

  In this case, as compared with such shaping processing by the reading shaping unit 17, the situation in which the data read from the memory 13 is appropriately divided and stored in each buffer 16 as described above (processing speed mismatch). ) May occur. In that case, there is a possibility that the small-scale buffer 16 may be depleted. In the worst case, data that has already been read from the memory 13 at that time cannot be written to the buffer 16, and the data may eventually disappear. Conceivable. In the embodiment of the present invention, in order to cope with such a situation, the read position of the memory 13 is stored in the read memory address holding unit 14. Then, as will be described later with reference to FIG. 8, when there is a risk of overflow of the buffer 16, reading from the memory 13 is temporarily stopped, and the free capacity of the buffer 16, that is, the free buffer ( 16) After the number of planes reaches a predetermined number, the data last written in the buffer 16 goes back to the address read from the memory 13 and starts reading from that position. As a result, even if the buffer 16 overflows and data that has already been read disappears, they are read again by retroactively reading the read address, so that packet loss can be reliably prevented.

  A packet shaping method using the reading unit 15 and the small buffer 16 in the data processing apparatus according to the embodiment of the present invention shown in FIG. 5 will be described with FIG. Assume that the memory 13 stores four parallel data for six cycles as shown in the upper left of FIG. Note that “C” as the first character of data indicates packet header information (control word), and “D” indicates packet payload information (data word). Those having the same number attached to them indicate data of the same packet. In the same figure, older stored data is shown in order from the left end.

  First, the reading unit 15 of the memory 13 reads the header 1 word C1 and the payload 3 word D1 (step S1). Since the destination of this data (subscript number: 1) is one and cannot be divided, it is held as it is on the storage surface (B0) of the 0th buffer 16 (step S2). Thereafter, the reading side of the buffer 16, that is, the reading shaping unit 17 recognizes that the data is stored in the buffer 16 in this way. However, if the payload is output in units of 4 words in addition to the header 1 word as long as it is not at the end of the packet as the data output format, the read shaping unit 17 does not satisfy the above condition at this point, so the data from the buffer 16 Does not output data.

  Next, the payload 4 word D1 is read by the reading unit 15 (step S3). Also in this case, since the destination (subscript number: 1) is one and cannot be divided, it is held as it is on the surface (B1) of the first buffer 16 (step S4). At this time, the read shaping unit 17 obtains a total of 4 words as a payload by combining the data of the buffer B0 (0th storage surface) and the buffer B1 (1st storage surface), and can output this as one unit. Judgment is made and the data are combined and output to the subsequent stage (step S5).

  Further, as a result of reading data from the memory 13 (step S6), the data of the same packet as the previously read packet is read as 1 word D1, and the header 1 word C2 and payload 2 word D2 of the new packet are read out. Become. However, since this data group belongs to separate packets with suffix numbers 1 and 2, the next word of the packet goes to the second side (B2) of the buffer, and the new packet header + payload total 3 words are buffered No. 3 (B3) is stored respectively (step S7).

  Similarly, the shaping unit 17 determines that the data can be output up to the end of the packet by combining the data of the first buffer (B1) and the second buffer (B2). Output (step S8). Thereafter, the data is read from the memory 13 and divided and stored in the buffer 16 in such a flow, and the reading from the buffer 16 and the shaping are further performed. This process is continued as long as data exists in the memory 13 (steps S9 to S19).

  On the other hand, in this shaping process, as shown in the example of FIG. 7, while reading from the memory 13 is 6 cycles, there may be a phenomenon that the shaping and output process requires a processing process of 7 cycles or more. Therefore, when such a phenomenon continues, there is a possibility that the small-sized buffer 16 having a plurality of faces is exhausted. In this case, a situation such as packet data loss will be caused.

  In order to prevent this, the surface number of the buffer 16 to which the data read from the memory 13 is to be divided and held (that is, the buffer numbers B0, B1, B2, B3,. The buffer surface number is compared and collated, and when the difference value is smaller than a predetermined value, it is determined that the number of free surfaces in the small-scale buffer is being exhausted.

  However, even when reading from the memory 13 is interrupted when the buffer 16 is detected to be depleted by such a configuration, due to the characteristics of the RAM used for the memory 13, several cycles have already been reached when the depletion is detected. It is considered that the data has been read from the memory 13. In that case, those data cannot be written into the buffer 16 due to the above depletion, and disappear. In order to prevent this, it is possible to prepare the number of surfaces of the buffer 16 with a margin sufficient to accommodate the data that has not yet been written to the buffer 16 at the time of detection of depletion. However, this naturally increases the circuit scale.

  Therefore, the address holding unit 14 always holds the position of the read pointer of the memory 13 when the data divided and stored in the buffer 16 is read. When it is predicted that the buffer 16 is depleted, data that has already been read but is not yet stored in the buffer 16 is temporarily discarded. Then, when the depletion is resolved as the shaping process proceeds, the read pointer of the memory 13 is returned to the held position and reading is resumed from there.

  Such a configuration will be described below with reference to a time chart of FIG. 8 together with a specific operation example.

  8A shows a change in the address currently read from the memory 13, FIG. 8B shows a memory read enable signal waveform, FIG. 8C shows data read from the memory 13, and FIG. Similarly, a value indicating the data read from the memory 13 is shifted by one cycle, and (e) shows the address in the memory 13 when the data already written in the buffer 16 is read from the memory 13. (F) shows the surface number of the buffer 16 in which the data read from the memory 13 is written, and (g) shows the buffer 16 referred to by the read shaping unit 17 for reading and shaping the data. Indicates the face number. FIG. 8H shows how data is stored in each surface of the buffer 16.

  As shown in the figure, the data “b” started to be read at time t0 by the address “B” of the memory 13 is read as data to be divided into the buffer 16 at time t1 after two cycles, and the buffers 9 and 10 are read. (FIG. 8 (h)). As a result, the surface number of the buffer 16 serving as the next data storage destination is changed to “11” (FIG. 8F). Here, as an example, the total number of surfaces of the buffer 16 is 16.

  At this time, the surface number of the buffer 16 referred to as the shaping target is “0” (FIG. 8G), and it is determined that the number of free surfaces is small. That is, in this case, out of the total number of buffer surfaces 16 (0 to 15), the writing surface is “11” and the reading surface is “0” (equivalent to “16” when considered as a ring buffer). 16-11 = 5. In this case, as an example, when the difference value is 5 or less, it is determined that the number of empty buffer planes is insufficient. As a result, in this case, since the difference is 5, it is determined that the number of free buffers is insufficient. As a result, the memory read enable signal (FIG. 8B) is invalidated, and data reading from the memory 13 is stopped.

  However, at this time (time t1), the read operation from the address “C, D, E” of the memory 13 is completed (FIG. 8A). In addition, it is expected that the data “c, d, e” (FIG. 8C) read out by this cannot be accommodated in the buffer 16. Therefore, the data “c, d, e” is once discarded, while the last effective read address “B” is held in the address holding unit 14 (FIG. 8E). That is, here, the address “B” read from the memory 13 for the data “b” last written in the buffer 16 is determined as the last effective address.

  Then, after the detection of the shortage of the buffer free space in the buffer 16 is resolved at time t2, the reading is resumed from the next address “C” obtained by incrementing “B” held as the last effective address. To do. As a result, it is possible to prevent data loss due to insufficient free space in the buffer 16.

  The detection of the lack of the buffer free space number is performed as follows. That is, at time t2, the reference surface of the buffer 16 (FIG. 8G) is incremented from 0 to 2 (equivalent to 17 in the same logic as above), and the difference from the storage surface 11 of the buffer 16 is It has increased to 6. Since this exceeds the threshold value of 5, it can be determined that the shortage of the number of free buffers is resolved.

  As a result of the determination that the number of empty planes is insufficient, the read enable signal (FIG. 8B) is validated at time t3, and reading from the memory 13 is resumed as described above. As a result, the data “c, d, e” is read again from the address “C, D, E” in the memory 13 (FIG. 8C), and these are sequentially transferred to the buffers 11, 12,. 13 and so on.

  In this way, the reading of data from the memory 13 is stopped by detecting the lack of free space in the buffer 16, and the data stored last in the buffer 16 at that stage holds the reading position from which the data was read from the memory 13. When the buffer free space shortage is resolved, reading is resumed from the held reading position of the memory 13. As a result, data loss can be reliably prevented even when the free space of the buffer 16 is insufficient.

  The flow of the write and read operations to the buffer 16 described with reference to FIG. 7 and the flow of the read operation from the memory 13 described with reference to FIG.

  FIG. 9 shows the flow of a write operation to the buffer 16. In the figure, the value of the write pointer N is initialized to 0 in step S21, and it is determined whether or not there is data to be read out in the memory 13 in step S22. If there is data to be read, it is determined in step S23 whether there is free space in the buffer 16 or not. As a result, if there is no free space, the data read from the memory 13 is discarded (step S24). However, when it is determined that the buffer 16 has insufficient free space as described above with reference to FIG. 8, the read position at which the data written in the buffer 16 at the end is read from the memory 13 is held, and then the empty space is stored. Reading is resumed by going back to the reading position again when the capacity shortage state is resolved. For this reason, the data discarded in step S24 is also read again and written into the buffer 16. As a result, no actual data loss occurs.

  Next, in step S25, the number of segments of data for one cycle read from the memory 13 is determined. Specifically, it is determined whether the data has one or two destinations. As a result, if the number of segments is 1, that is, the destination is one place, all the data is written to one surface (number N) of the buffer 16 in step S26. Then, the write pointer N is incremented (step S27). On the other hand, if the determination in step S25 is “2 segments” or “has two destinations”, the data is written in two planes (numbers: N, N + 1) for each segment or by destination in step S28. . As a result, the write pointer is incremented by “2” in this case (step S29). Thereafter, the process returns to step S22, and the above operation is repeated.

  Next, the operation of reading the data written in the buffer 16 in this way will be described with reference to FIG.

  In step S31, the read pointer N is incremented to 0, and in step S32, it is determined whether there is data to be read on the N side of the buffer 16. As a result, if there is data to be read, it is determined in step S33 whether the data held on the N-plane of the buffer 16 is the last data of the segment. That is, the destination of the data is compared with the destination of the next data held in the buffer surface, and if the data is different, it can be determined that the data on the N surface is the last data of the segment. If the determination result is Yes, the data is read as it is and sent to the shaping unit 17 (step S35), and the read pointer N is incremented (step S36).

  On the other hand, if the determination result in step S33 is No, it is determined in step S34 whether the amount of the data is equal to or greater than a certain amount. If the result is less than a certain amount, the process proceeds to step S37 without outputting the data as it is. That is, in the example of FIG. 7, as long as it is not the end of the packet as described above, it is set to output 4 words of payload as a unit in addition to the header, so the amount written in the buffer B0 in step S2 of FIG. The payload is 3 words and this condition is not met. Therefore, it is not output.

  In step S37, it is determined whether or not a certain amount of data is obtained by adding the data held on the N side of the buffer 16 and the data held on the next N + 1 side. If the result is Yes, the N + 1 plane data is added in step S39 and output as the fixed amount (step S39). In other words, in the example of FIG. 7, in step S5, a part of the data on the B1 side is added to the data on the B0 side, and the data is output as the prescribed data amount (payload: 4 words).

  Next, in step S40, it is determined whether or not there is unoutput data on the N + 1 surface of the buffer. If there is, the surface number N + 1 is assigned to the read pointer N (step S42) and the operations after step S32. repeat. On the other hand, if the result of step S40 is No, the next face number N + 2 is substituted for the read pointer N in step S41 (step S41), and the operations after step S32 are repeated.

  Next, a data reading operation from the memory 13 will be described with reference to FIG.

  In step S51, the read pointer is initialized, and it is determined whether or not there is data to be read in the memory 13 (step S52). If the result is “Yes”, it is determined in step S53 whether or not reading is currently stopped. That is, as described above, since it is determined that reading is stopped when it is determined that the free space of the buffer 16 is insufficient, this point is determined.

  Next, if the result of the determination is Yes, it is determined in step S54 whether or not the free space in the buffer 16 has been recovered. If it has been recovered, the read stop state is canceled in step S55, and step S57 is determined. Proceed to On the other hand, if the determination result in step S53 is No, whether or not there is a shortage of free space in the buffer 16 as a result of the data read from the read pointer N being written in the buffer 16 in step S56. Predictive judgment. If the determination result is Yes, the data stored in the area of the memory 13 indicated by the current read pointer N is not read, and the value of the read pointer N is changed to the value of the next read pointer N in step S59. In step S60, the reading stop state is set, and the operations in and after step S52 are repeated.

  On the other hand, if the decision result in the step S56 is No, the data stored in the area of the memory 13 indicated by the current read pointer N is read in a step S57, and the read pointer is incremented in a step S58. The subsequent operations are repeated.

  The data reading from the memory 13 described with reference to FIG. 11 and the writing operation to the buffer 16 described with reference to FIG. 9 are performed by the reading unit 15 shown in FIG. 5, and the reading operation from the buffer 16 described with reference to FIG. Performed in part 17.

  As described above, according to the embodiment of the present invention, the shaping after the parallelization of the packet data is performed in the former stage of the large-capacity memory, whereas the shaping operation is performed in the latter stage of the large-capacity memory (13). Instead, by providing a small buffer (16) with a multi-face configuration, it is possible to effectively prevent packet data from being lost and to ensure normal communication.

The present invention includes configurations shown in the following supplementary notes.
(Appendix 1)
First storage means for storing input data;
The second storage means reads out the input data stored in the first storage means, classifies it according to a predetermined rule, and sequentially writes it into a predetermined storage unit for each classification,
A data processing apparatus, wherein the first storage means has a larger storage capacity than the second storage means.
(Appendix 2)
When it is determined that the storage capacity of the second storage means is insufficient, reading from the first storage means is stopped, and after the shortage state is resolved, the data is finally written to the second storage means before the stop. The data processing apparatus according to appendix 1, wherein the data read from the first storage means is resumed from the read position where the read data is read from the first storage means.
(Appendix 3)
When writing data to the second storage means, the data is written in a predetermined order with respect to the plurality of storage units, and the determination of the lack of storage capacity of the second storage means is performed by the first storage means. The number of storage units into which the data read from the data is written and the number of storage units from which the data written in this way is read out for a predetermined process are determined depending on the difference. Item 4. The data processing device according to any one of Items 1 to 3.
(Appendix 4)
Storing input data in a first storage means;
Reading out the input data stored in the first storage means, classifying it according to a predetermined rule, and sequentially writing it into a predetermined storage unit of the second storage means for each classification,
A data processing method, wherein the first storage means has a larger storage capacity than the second storage means.
(Appendix 5)
Further, when it is determined that the storage capacity of the second storage means is insufficient, reading from the first storage means is stopped, and after the shortage is resolved, the second storage means is finally connected to the second storage means before the stop. The data processing method according to appendix 4, wherein the written data is traced back to the reading position where the data is read from the first storage means, and the reading from the first storage means is resumed.
(Appendix 6)
When writing data to the second storage means, the data is written in a predetermined order with respect to the plurality of storage units, and the determination of the lack of storage capacity of the second storage means is performed by the first storage means. Note that the number of storage units into which the data read from is written and the number of storage units from which the data written in this way is read out for a predetermined process are determined according to the difference in size. 6. The data processing method according to 4 or 5.

It is a block diagram of the conventional packet data exchange apparatus. 2 is a time chart for explaining serial / parallel conversion of packet data and a shaping operation for each destination in the configuration shown in FIG. 1. It is a block diagram of the conventional packet shaping process part contained in the structure shown in FIG. It is a figure for demonstrating the conventional packet shaping system (The storing procedure to the memory at the time of shaping in the front | former stage of a memory) by the structure shown in FIG. 1 is a block diagram of a data processing apparatus according to an embodiment of the present invention. FIG. 6 is a diagram for explaining packet shaping (a storing procedure in a memory when shaping is performed at a later stage of the memory) according to the configuration of FIG. 5. FIG. 6 is a diagram for explaining a specific operation example of a division shaping process in the latter stage of the memory having the configuration of FIG. 5. 6 is a processing time chart when a small-scale buffer is depleted according to the configuration of FIG. 6 is a flowchart of a write operation for the buffer shown in FIG. 5. 6 is a flowchart of a read operation from the buffer shown in FIG. 6 is a flowchart of a read operation from the memory shown in FIG.

Explanation of symbols

12 writing unit 13 memory 14 reading address holding unit 15 reading unit 16 buffer 17 reading shaping unit

Claims (4)

Reading means for reading data from the first storage means and dividing the read data into a plurality of storage units of the second storage means;
Reads data held by being divided into a plurality of storage units of the second storage means, and among the data held by being divided into the plurality of storage units, the same destination held in the plurality of storage units Read shaping means that performs shaping that combines data ,
The number of the storage unit of the plurality of storage units of the second storage unit, in which the reading unit divides and holds the data read from the first storage unit, and the read shaping unit shapes the data. The number of the one storage unit is compared with the number of the other storage unit by comparing the number of the other storage unit among the plurality of storage units of the second storage unit that holds the target data. The data processing apparatus according to claim 1, wherein when the difference from the number is smaller than a predetermined value, the reading unit stops reading data from the first storage unit. When the first data for one cycle read from the first storage means is the same destination data, the reading means stores the read first data for one cycle in the second held in the first primary storage unit of the plurality of storage units storing means, second data next read one cycle from said first storage means is a data of the same destination, When the destination data is the same as the first data, the second data is different from the first storage unit among the plurality of storage units of the second storage means. 2 in one storage unit,
When the data for one cycle read from the first storage means is data of a plurality of different destinations, the plurality of data of different destinations for the one cycle are stored in the plurality of data of the second storage means. the data processing apparatus according to claim 1, characterized in that holding by respectively divided into a plurality of storage units of the storage unit. A read step of reading data from the first storage means and dividing the read data into a plurality of storage units of the second storage means;
The same destination stored in the plurality of storage units among the data stored in the plurality of storage units is read out by reading the data stored in the plurality of storage units of the second storage unit And a read shaping stage for shaping the data in combination ,
The number of storage units of the plurality of storage units of the second storage means that divides and holds the data read from the first storage means at the read stage and the shaping at the read shaping stage. The number of the one storage unit and the other storage unit are compared with the number of the other storage unit among the plurality of storage units of the second storage unit in which the target data is held A data processing method characterized by stopping reading of data from the first storage means in the reading step when the difference from the number is smaller than a predetermined value. In the reading step, when the first data for one cycle read from the first storage means is the same destination data, the first data for the one cycle read is stored in the second data. held in the first primary storage unit of the plurality of storage units storing means, second data next read one cycle from said first storage means is a data of the same destination, When the destination data is the same as the first data, the second data is different from the first storage unit among the plurality of storage units of the second storage means. 2 in one storage unit,
When the data read from the first storage means in one cycle of the predetermined cycle is data of a plurality of different destinations, the data of the plurality of different destinations are stored in the plurality of data of the second storage means. the data processing method according to claim 3, characterized in that holding by respectively divided into a plurality of storage units of the storage unit.

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