KR100344025B1 - HDLC router using multi-queue and control method therefor - Google Patents

Abstract

The present invention is applied to a system having a variable size of packet data, HDLC router using multiple queues to improve the efficiency of the memory and to improve the packet data transmission speed in the HDLC router performing signal processing by converting serial packet data in parallel And a method of controlling the same. The present invention divides the memory into multiple queues and converts the serial data into parallel data and writes and reads the data into parallel data, and divides the memory into multiple queues and divides the queue size into the minimum packet size used in the system. By managing the inside of the queue by cell unit, many data can be stored in the queue according to the packet size, improving the efficiency of memory usage and increasing the flexibility of memory management.

Description

HDLC router using multi-queue and control method therefor}

The present invention relates to a serial data communication High Level Data Link Control (HDLC) router, and more particularly, when the HDLC router converts serial data into parallel data and writes to and reads from the memory. The present invention relates to an HDLC router using multiple queues and a control method thereof, which manages multiple queues to efficiently use memory when the size of packet data is variable.

In general, HDLC routers in serial data communication convert serial data in parallel and process the data in parallel. In this case, the parallel packet data is stored in memory. This memory is divided into queues so that one packet is stored in one queue. So the queue of memory is allocated the same size as the packet with the largest size among the packets used in the system.

Therefore, in the case of a system having a variable size of a packet stored in the memory, when the packet size is much smaller than the queue size, there is a problem that the use efficiency of the memory is much lowered. In addition, since a large number of packets cannot be stored in the memory, there is a problem that the transmission speed of the packets also decreases.

Therefore, the present invention has been proposed to solve the conventional problems as described above, the object of the present invention is

When converting serial data to parallel data and writing to and reading from memory in HDLC routers applied to systems with variable packet data sizes, divide this memory into multiple queues and set the queue size to the minimum packet size used by the system. By managing the inside of the queue by cell unit, many data can be stored in the queue according to the packet size to improve the efficiency of memory usage and increase the flexibility of memory management. To provide.

HDLC router using multiple queues according to the present invention to achieve the above object,

A data writing unit which senses the beginning and the end of packet data input in a serial form, converts the data into parallel data, and writes the data into a memory according to a write cell address and a write queue address;

A write cell address generator and a read cell address generator that operate when a start of packet data is detected to generate an address in units of cells and to generate a carry signal when the cell address reaches a set queue size;

A write queue address generator generating a queue address in accordance with a carry signal generated by the write cell address generator;

A read queue address generator generating a queue unit address according to a carry signal generated by the read cell address generator;

A memory for storing packet data, the queue having multiple sizes set to the size of the minimum packet in the system;

The technical configuration is characterized by a data reading section which reads the size of packet data from the designated queue in the memory and reads packet data as much as the packet data size from the corresponding queue according to the read cell address and the read queue address.

HDLC router control method using multiple queues according to the present invention to achieve the above object,

Detecting a start of a packet when serial packet data is input;

Converting the input packet data into a parallel form, adding a size of the packet data, storing the corresponding packet data in a corresponding cell in the memory, and checking whether all the cells of the corresponding queue are full;

A third step of increasing a write queue address and detecting an end of the packet data when all cells of the corresponding queue are full as a result of the checking;

If the end of the packet data is not detected, the process proceeds to the second step. If the end of the packet data is detected, the size of the packet data is stored in a designated cell of the designated queue of the memory, and the write queue address is increased. Waiting for the next packet data write in the queue;

A fifth step of reading the packet data size from the designated cell of the designated queue of the memory and reading and transmitting the packet data by the packet data size from the corresponding queue of the memory according to the read queue address and the read cell address; Performance is characterized by its methodological configuration.

1 is a block diagram of an HDLC router block using multiple queues according to the present invention;

2 is a flowchart illustrating a method for controlling an HDLC router using multiple queues according to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: data writing unit 20: writing cell address generating unit

30: write cure dress generator 40: memory

50: data reading section 60: reading cell address generating section

70: read queue address generator

Hereinafter, an HDLC router using a multi-queue according to the present invention and a control method thereof will be described in detail with reference to the accompanying drawings.

1 shows an HDLC router block configuration using multiple queues according to the present invention.

As shown, the data write unit 10 which detects the start and end of the packet data input in serial form, converts the data into parallel data, and writes the data to the memory 40 according to the write cell address and the write queue address. )Wow; A write cell address generator 20 and a read cell address generator that operate when a start of packet data is detected to generate an address in a cell unit, and generate a carry signal when the cell address reaches a set queue size. 60); A write queue address generator 30 generating a queue address in accordance with a carry signal generated by the write cell address generator 20; A read queue address generator 70 generating a queue unit address according to a carry signal generated by the read cell address generator 60; A memory 40 configured to store a plurality of queues each having a size set to a size of a minimum packet in the system; The data reading unit 50 reads the size of the packet data from the designated queue in the memory 40 and reads the packet data by the packet data size from the corresponding queue according to the read cell address and the read queue address.

2 is a flowchart illustrating a method of controlling an HDLC router using multiple queues according to the present invention.

A first step (ST11, ST12) of detecting the start of a packet when serial packet data is input; A second step (ST13-ST16) of adding the size of the packet data, converting the input packet data into a parallel form, storing the corresponding packet data in a corresponding cell in the memory, and checking whether all the cells of the corresponding queue are full; A third step (ST17, ST18) of increasing the write queue address and detecting the end of the packet data if all cells of the corresponding queue are full as a result of the check; If the end of the packet data is not detected, the process proceeds to the second step (ST13-ST16). If the end of the packet data is detected, the size of the packet data is stored in a designated cell of the designated queue of the memory. A fourth step (ST19, ST20) of increasing the address to wait for writing of the next packet data in the next queue; A fifth step of reading the packet data size from a designated cell of a designated queue of the memory, and reading and transmitting the packet data as much as the packet data size from the corresponding queue of the memory according to a read queue address and a read cell address; do.

The memory 40 has a plurality of queues whose size is set to the minimum packet size in the system, and the queue consists of a plurality of cells.

The read queue address is increased by one when the read cell address reaches the maximum size value of the queue, and the read cell address is generated in the cyclic mode by the number of cells forming one queue.

The HDLC router and its control method using multiple queues according to the present invention as described above are as follows.

When serial data is input, the data writing unit 10 first detects the start of a packet, and when there is a packet input, the data writing unit 10 sorts the serial data in parallel and counts the number of data each time one unit (Byte / Word / Long Word / ..) ends. Add to this (ST11, ST12, ST13, ST14). If the start of packet input is not detected, the state remains in the waiting state (ST13).

The parallel data sorted data is stored in the memory, and the storage order is from the second cell (cell 1) of the first queue of the memory 40. This is because the first cell (cell 0) is later stored the final packet size.

After storing the data, the write cell address is increased (ST15), and it is checked whether the first queue is full (ST16). As a result, if not occupied, the process proceeds to ST14 and stores the packet data converted in parallel in the corresponding cell of the first queue.

However, when the first queue is full, the write cell address generation unit 20 generates a carry signal, and the write queue address generation unit 30 increases the write queue address by one to indicate the next queue. (ST17). The write cell address is an address indicating the number of cells constituting one queue, and is cyclically counted from 0 to the maximum number of cells.

On the other hand, the data writing unit 10 detects the end of the packet (ST18). If the end of the packet is not detected, the process proceeds to ST14. The size of is stored in the first cell (cell 0) of the first queue (ST19). When one packet data is written to the corresponding queue of the memory 40, the write queue address generator 30 increases the write queue address by 1 so that the next write operation in the queue can be performed. ST20).

In this way, if the variable packet data in the multiple queue of the memory 40 is converted in parallel and stored, the data reading unit 50 reads the packet data from the corresponding queue of the memory 40. Read the packet data size to read from the first cell (cell 0) of the queue.

The signal is then processed by reading data from the next cell.

In the same manner as the write to memory process, the read cell address generator 60 reads data while increasing the read cell address. The read cell address generation unit 60 generates a carry signal when the value of the read cell address reaches a maximum value, that is, a set queue size. Accordingly, the read queue address generator 70 increases the read queue address by one.

The above operation is continued until the packet data size read from the first cell of the first queue and the amount of packet data read from the queue are matched. If the comparison value is matched, the read operation is interrupted, and the read queue address generator 60 increases the value of the read queue address by one and waits in the next queue.

As described above, the HDLC router and its control method using the multi-queue of the present invention, when converting the serial data into parallel data to write and read in the memory in the HDLC router applied to a system having a variable packet data size By dividing this memory into multiple queues, setting the queue size to the minimum packet size used by the system, and managing the inside of the queue cell by cell, it is possible to store a lot of data in the queue according to the packet size, improving the efficiency of memory usage. To increase the flexibility of memory management.

In addition, by effectively using the memory for a variable sized packet in the system, a small sized memory can be used, and by checking the size of the packet separately, it is possible to check the packet error that may occur during data processing. It is effective to prevent inflow.

In addition, the same amount of memory (RAM) can hold a larger amount of serial data, which can increase the transfer speed.

Claims (4)

In an HDLC router applied to a system having a variable packet length, A data writing unit which senses the beginning and the end of packet data input in a serial form, converts the data into parallel data, and writes the data into a memory according to a write cell address and a write queue address; A write cell address generator and a read cell address generator that operate when a start of packet data is detected to generate an address in units of cells and to generate a carry signal when the cell address reaches a set queue size; A write queue address generator generating a queue address in accordance with a carry signal generated by the write cell address generator; A read queue address generator generating a queue unit address according to a carry signal generated by the read cell address generator; A memory for storing packet data, the queue having multiple sizes set to the size of the minimum packet in the system; And a data reading unit configured to read the packet data size from the designated queue in the memory and read the packet data by the packet data size according to the read cell address and the read queue address. . In the control method of the HDLC router applied to a system having a variable packet length, Detecting a start of a packet when serial packet data is input; Converting the input packet data into a parallel form, adding a size of the packet data, storing the corresponding packet data in a corresponding cell in the memory, and checking whether all the cells of the corresponding queue are full; A third step of increasing a write queue address and detecting an end of the packet data when all cells of the corresponding queue are full as a result of the checking; If the end of the packet data is not detected, the process proceeds to the second step. If the end of the packet data is detected, the size of the packet data is stored in a designated cell of the designated queue of the memory, and the write queue address is increased. Waiting for the next packet data write in the queue; A fifth step of reading the packet data size from the designated cell of the designated queue of the memory and reading and transmitting the packet data by the packet data size from the corresponding queue of the memory according to the read queue address and the read cell address; HDLC router control method using multiple queues characterized by performance. The method of claim 2, wherein the memory, And a plurality of queues having a size set to a minimum packet size in the system, wherein the queue comprises a plurality of cells. The method of claim 2, The read queue address is increased by one when the read cell address becomes the maximum size value of the queue, and the read cell address is generated in a cyclic mode by the number of cells forming one queue. How to control HDLC router using queue.