JP4420119B2 - Receiver circuit - Google Patents

Description

The present invention relates to a receiving circuit.

  2. Description of the Related Art Conventionally, a smart entry system is known that performs ID authentication when a user who has a smart key portable device approaches a car and unlocks the car door when it is confirmed that the user is a legitimate user. (Patent Document 1).

  In this smart entry system, the vehicle-mounted device transmits an ASK modulated signal in the LF band. When the user holding the portable device approaches the car, the antenna unit of the portable device detects the electric field of this signal, and when the receiving unit of the portable device receives the request signal from the in-vehicle device, the transmitting unit of the portable device receives the ID code. Send. When the ID codes match, the car door is unlocked and the like.

  However, in this smart entry system, the receiving unit of the portable device needs to always perform the detection operation of the signal from the in-vehicle device, so that the battery of the portable device is greatly consumed and a situation such as battery exhaustion is likely to occur. Therefore, there is a problem that the demand for lower power consumption in the receiver of the portable device is severe.

  In addition, a reception circuit for a radio signal or the like is provided with an amplification circuit for amplifying the reception signal. In order to improve the S / N ratio, it is desirable to provide a bandpass filter that selectively extracts only the frequency component of the desired signal.

  However, in the conventional receiving circuits, a band pass filter is provided separately from the amplifier circuit. For this reason, two circuit elements, that is, an amplifier circuit and a band-pass filter are required, and there is a problem that the circuit becomes large and power consumption becomes large.

  If the received signal has a small amplitude, it is desirable to cascade a plurality of amplifier circuits in order to increase the amplification factor.

However, when a plurality of amplifier circuits are connected in cascade and there is an imbalance in amplification in each amplifier circuit, there is a problem that the operating point of the amplified signal shifts and a stable amplification operation cannot be realized.
JP 2006-37493 A

  According to some aspects of the present invention, it is possible to provide a receiving circuit capable of realizing low power consumption.

  According to another aspect of the present invention, it is possible to provide an amplifier circuit that can realize a reduction in circuit scale and power consumption.

  According to another aspect of the present invention, an amplifier circuit that can realize a stable amplification operation can be provided.

  The present invention has a frequency characteristic of an attenuator that receives a received signal and performs attenuation of the received signal, a DC level shifter that performs DC level shift of the signal after attenuation, and a band-pass filter, and is a signal after DC level shift And a control circuit for controlling the attenuation amount of the attenuator based on the output signal of the amplifying unit, the control circuit according to the amplitude of the output signal of the amplifying unit This is related to a receiving circuit that controls the attenuation amount of the attenuator so that the amplitude of the output signal of the amplifying unit is constant even when the amplitude of the received signal is changed by changing the filter characteristic of.

  According to the present invention, the attenuation amount of the received signal is controlled by the attenuator, the DC level is shifted by the DC level shifter, and the signal is amplified by the amplifying unit. The control circuit changes the filter characteristic of the attenuator based on the amplitude of the output signal of the amplifying unit, controls the attenuation amount of the attenuator, and keeps the amplitude of the output signal of the amplifying unit constant. In this way, it is not necessary to provide the automatic gain adjustment function to the amplification unit itself, so that the configuration of the amplification unit can be simplified and low power consumption can be realized. Further, since it is only necessary to control the attenuation amount of the attenuator, the circuit configuration of the attenuator can be simplified, and further reduction in power consumption can be realized.

  In the present invention, the attenuator has a high-pass filter characteristic, and the control circuit changes the cut-off frequency of the high-pass filter according to the amplitude of the output signal of the amplifying unit. The amount of attenuation may be controlled.

  In this way, the attenuation amount of the attenuator can be controlled only by changing the cut-off frequency of the high-pass filter according to the amplitude of the output signal of the amplifying unit, so that the attenuator can be configured with a simple circuit element.

  In the present invention, the control circuit increases the cutoff frequency of the high-pass filter as the amplitude of the output signal of the amplifying unit increases, thereby increasing the amount of attenuation in the frequency band of the carrier wave of the received signal. Control may be performed.

  In this way, it is possible to attenuate the signal amplitude of the carrier wave that is passed by the band pass filter of the amplifying unit by the high pass filter of the attenuator, thereby realizing proper attenuation control by the attenuator.

  In the present invention, the control circuit includes a charging capacitor provided between a charging node and a first power source, and a charging transistor provided between the charging node and a second power source, Comparing the amplitude of the output signal of the amplifier and a reference voltage, charging the charging capacitor by the charging transistor based on the comparison result, and outputting the voltage of the charging node to the attenuator as a control voltage May be.

  In this way, a control voltage corresponding to the amplitude of the output signal of the amplifying unit can be generated at the charging node, and the attenuation amount of the attenuator can be controlled using this control voltage.

  In the present invention, the control circuit may include a discharging transistor that is provided between the charging node and the first power source and that supplies a constant current to the first power source side.

  By doing so, it is possible to prevent a situation in which the attenuation amount of the attenuator is set to a large value due to a noise signal or the like.

  In the present invention, the discharge period set by the constant current flowing through the discharge transistor and the capacitance of the charging capacitor may be longer than the transfer period of the first logic level of the ASK-modulated received signal. Good.

  In this way, proper data transfer during the data transfer period can be realized.

  According to the present invention, the attenuator is provided between an attenuation capacitor provided between an input node of the received signal and an output node of the attenuator, and between the output node and the first power source, and its gate. May include an attenuation transistor to which a control voltage from the control circuit is input.

  In this way, the attenuation can be controlled simply by providing an attenuation capacitor and an attenuation transistor, so that the attenuator circuit can be simplified and the power consumption can be reduced.

  In the present invention, the attenuator may include a pull-down transistor provided between the output node and the first power supply.

  In this way, since the potential of the output node can be pulled down, noise resistance can be improved.

  In the present invention, the amplifying unit includes at least one amplifying circuit, and the amplifying circuit includes a first operational amplifier in which an input signal from the DC level shifter is input to a first input terminal, and a first operational amplifier. A voltage follower-connected second operational amplifier in which the output of the first operational amplifier is input to one input terminal, and the output is input to the second input terminal and the second input terminal of the first operational amplifier; And a gain setting unit for setting the gain of the amplifier circuit.

  In this way, it is possible to realize a band-pass filter characteristic in which, for example, the gain at the center frequency is set by the gain setting unit, and the DC level is cut by feedback from the second operational amplifier.

  According to the present invention, a first operational amplifier to which an input signal is input is input to the first input terminal, and an output of the first operational amplifier is input to the first input terminal, and the output is the second operational amplifier. A voltage follower-connected second operational amplifier that is input to the input terminal and the second input terminal of the first operational amplifier; and a gain setting unit that sets a gain of an amplifier circuit. When the first bias current flowing is IB1 and the second bias current flowing through the second operational amplifier is IB2, the amplifier circuit having the bandpass filter frequency characteristics is set by setting IB1> IB2. Involved.

  According to the present invention, the output of the first operational amplifier is fed back to the second input terminal of the first operational amplifier via the second operational amplifier connected to the voltage follower. The first and second bias currents IB1 and IB2 of the first and second operational amplifiers have a relation of IB1> IB2, whereby the first operational amplifier is set as a high-speed operational amplifier, and the second operational amplifier is Set to a low-speed operational amplifier. Therefore, the amplifying circuit can have the band-pass filter characteristic set by the characteristic of the first operational amplifier and the attenuation characteristic on the low frequency side set by the characteristic of the second operational amplifier. become. Therefore, the amplifier circuit can be provided with both a bandpass filter function and an amplification function, and the circuit can be reduced in size and power consumption.

  In the present invention, the cut-off frequency on the low frequency side of the bandpass filter is set by the output impedance of the second operational amplifier and the load capacitance of the output node of the second operational amplifier, and the high frequency of the bandpass filter. The cutoff frequency on the frequency side may be set by the output impedance of the first operational amplifier and the load capacitance of the output node of the first operational amplifier.

  In this way, by adjusting the output impedance and load capacitance of the second operational amplifier, the cut-off frequency on the low frequency side of the bandpass filter is set, and the output impedance and load capacitance of the first operational amplifier are adjusted. Thus, it becomes possible to set the cut-off frequency on the high frequency side of the bandpass filter.

  In the present invention, the gain setting unit includes a first capacitor provided between the output of the first operational amplifier and the second input terminal of the first operational amplifier, and the output of the second operational amplifier. And a second capacitor provided between the first power source and the first power source.

  In this way, for example, the gain of the amplifier circuit at the center frequency of the bandpass filter can be set by the capacitance ratio of the first and second capacitors.

  In the present invention, when the offset voltage of the first operational amplifier is VOF1 and the offset voltage of the second operational amplifier is VOF2, VOF1> VOF2 may be set.

  In this way, it is possible to minimize the offset voltage of the amplifier circuit, and it is possible to achieve both prevention of operating point shift and low power consumption.

  In the present invention, the gate length of the differential pair transistor constituting the first operational amplifier is L1, the gate width is W1, the gate length of the differential pair transistor constituting the second operational amplifier is L2, and the gate width is When W2 is set, L1 × W1 <L2 × W2 may be set.

  In this way, the relationship of VOF1> VOF2 can be established in the offset voltage by setting the gate length and gate width of the differential pair transistor.

  According to the present invention, a first operational amplifier to which an input signal is input is input to the first input terminal, and an output of the first operational amplifier is input to the first input terminal, and the output is the second operational amplifier. A voltage follower-connected second operational amplifier that is input to the input terminal and the second input terminal of the first operational amplifier; and a gain setting unit that sets a gain of an amplifier circuit. The present invention relates to an amplifier circuit composed of rail-to-rail operational amplifiers.

  According to the present invention, the output of the first operational amplifier is fed back to the second input terminal of the first operational amplifier via the second operational amplifier connected to the voltage follower. The second operational amplifier is composed of a rail-to-rail operational amplifier. In this way, the second operational amplifier can amplify the signal in a balanced manner on both the upper side and the lower side centering on the operating point of the small signal amplitude. As a result, the unbalance of the feedback of the signal from the output of the first operational amplifier to the inverting input terminal can be reduced, and a situation such as a shift of the operating point can be prevented.

  In the present invention, the second operational amplifier includes a first current mirror circuit, a first differential pair transistor, a first differential section having a first current source transistor, and a second current mirror. A circuit, a second differential pair transistor, a second differential unit having a second current source transistor, an output unit to which an output of the first differential unit is input, and the first difference A first node, which is a drain node of one transistor of the first differential pair transistor of the moving part, and a first power supply, and the gate of the second differential part is provided at the gate of the first differential pair transistor; A first node to which a third node which is a drain node of one transistor of the two differential pair transistors is connected, and a second node which is a drain node of the other transistor of the first differential pair transistor And the first power supply A second transistor connected to a fourth node, which is a drain node of the other transistor of the second differential pair transistor, and is connected to the gate of the second differential pair transistor; The gate of the one transistor and the gate of the other transistor of the second differential pair transistor are connected in common, and the gate of the other transistor of the first differential pair transistor and the second differential pair. The gates of the one of the transistors may be connected in common.

  In this way, even when the voltage of the input signal to the second operational amplifier becomes higher or lower, the signal can be amplified by one of the first and second differential units, It is possible to prevent the dead band from being generated above or below the power supply voltage range. As a result, the signal can be amplified in a balanced manner on both the upper side and the lower side around the operating point.

  In the present invention, the first operational amplifier is configured by a differential unit, the second operational amplifier is configured by first and second differential units, and the output of the differential unit of the first operational amplifier is The first operational amplifier is connected to the first input terminals of the first and second differential sections of the second operational amplifier, and the output of the first differential section and the output of the second differential section are connected in common. In addition, the outputs of the first and second differential units may be connected to second input terminals of the first and second differential units.

  In this case, since the first operational amplifier can be configured by the differential unit and the second operational amplifier can be configured by the first and second differential units, the circuit scale can be reduced and power consumption can be reduced. In addition, the first and second differential sections can amplify the signal in a balanced manner on both the upper side and the lower side with the operating point as the center, thereby reducing the unbalance of the feedback of the signal from the output of the first operational amplifier to the inverting input terminal. .

  In the present invention, the differential section of the first operational amplifier has a current mirror circuit, and the input signal is input to the gate of one transistor, and the first and second differentials are input to the gate of the other transistor. A differential pair transistor to which an output of a first section is connected; and a current source transistor that supplies a bias current flowing through the current mirror circuit and the differential pair transistor, the first differential section of the second operational amplifier Is configured such that the output of the differential unit is connected to the gate of one N-type transistor and the first and second gates of the other N-type transistor are connected to the first current mirror circuit configured by a P-type transistor. The first differential pair transistor to which the output of the differential section is connected, and the bias current flowing through the first current mirror circuit and the first differential pair transistor Including a first current source transistor configured by an N-type transistor, wherein the second differential section of the second operational amplifier includes a second current mirror circuit configured by an N-type transistor, A second differential pair transistor in which the output of the differential unit is connected to the gate of the P-type transistor, and the output of the first and second differential units is connected to the gate of the other P-type transistor; A bias current flowing through the second current mirror circuit and the second differential pair transistor may be supplied, and a second current source transistor configured by a P-type transistor may be included.

  In this way, a rail-to-rail operational amplifier using the first and second differential units can be realized with a simple circuit configuration, and power consumption can be easily reduced.

  In the present invention, the differential pair transistor of the differential section, the first differential pair transistor of the first differential section, and the second current mirror circuit of the second differential section are: The second differential pair transistor of the second differential section is arranged along the first direction and the second differential pair transistor of the second differential section is the second direction when the direction perpendicular to the first direction is the second direction. It may be arranged on the second direction side of the current mirror circuit.

  If the transistors are arranged in this way, the differential unit and the first and second differential units can be arranged compactly along the first direction.

  In the present invention, the output line of the differential section is wired along the first direction from the differential pair transistor toward the second current mirror circuit, and from the second current mirror circuit to the second current mirror circuit. Wiring may be performed along the second direction toward the second differential pair transistor.

  In this way, the output lines of the differential section can be wired without waste along the first direction and the second direction.

  In the present invention, the gain setting unit includes a first capacitor provided between the output of the first operational amplifier and the second input terminal of the first operational amplifier, and the output of the second operational amplifier. A second capacitor provided between the first power source and the first power source, wherein the direction opposite to the first direction is a third direction and the direction opposite to the second direction is a fourth direction. The output line of the differential section is wired along the third direction from the second differential pair transistor toward the first capacitor, and is connected to one end of the first capacitor. A connection line from the other end of the first capacitor may be wired along the fourth direction from the first capacitor toward the differential pair transistor of the differential unit.

  In this way, the output line can be wired without waste, and the parasitic capacitance of the output line can be reduced, so that the speed of the first operational amplifier can be increased.

  Further, in the present invention, when the direction opposite to the second direction is a fourth direction, the current source transistor of the differential unit is disposed on the fourth direction side of the differential pair transistor, The first current source transistor of the first differential section may be disposed on the fourth direction side of the first differential pair transistor.

  In this way, it is possible to arrange the current source transistor of the differential section and the first current source transistor of the first differential section by effectively utilizing the empty area in the fourth direction of the differential pair transistor, A compact layout can be realized.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Reception Circuit FIG. 1 shows a configuration example of the reception circuit of this embodiment. Note that the receiving circuit of the present embodiment is not limited to the configuration of FIG. 1, and various modifications such as omitting some of the components or adding other components are possible.

  The receiving circuit of FIG. 1 includes an attenuator 40, a DC level shifter 50, an amplifying unit 60, and a control circuit 70. A demodulation circuit 90 can also be included.

  A reception signal IN from the antenna unit 10 configured by a coil (LC resonance circuit) or the like is input to the attenuator 40. The attenuator 40 (filter circuit) attenuates the reception signal IN. Taking the smart entry system as an example, an ASK (Amplitude Shift keying) modulated reception signal IN of LF (Low Frequency) band that changes the amplitude of the carrier wave corresponding to the input digital signal is input to the attenuator 40. Then, the attenuator 40 attenuates the amplitude of the received signal IN in the LF band of, for example, 120 to 140 KHz that has been ASK modulated (amplitude modulated) based on the control voltage VC (control signal) from the control circuit 70.

  The attenuator 40 includes an attenuation capacitor CA1 provided between the input node NA0 of the received signal IN and the output node NA1 of the attenuator 40, and the output node NA1 and VSS (first power supply in a broad sense). It includes an N-type transistor TA1 for attenuation to which the control voltage VC from the control circuit 70 is input. The attenuator 40 has, for example, a high-pass filter frequency characteristic. That is, a high-pass filter is configured by the capacitance of the capacitor CA1 and the on-resistance of the transistor TA1. The attenuation may be controlled by giving the attenuator 40 the characteristics of a low-pass filter and controlling the cutoff frequency of the low-pass filter.

  The DC level shifter 50 performs DC level shift of the signal VS1 after attenuation, and outputs a signal VS2 after DC level shift. That is, the DC level shifter 50 performs level shift conversion so that the DC level of the signal VS2 is set at the operation point (amplification center) of the small signal amplification of the amplification unit 60. This DC level shifter 50 is provided between VSS (first power supply) and its output node NA2, and has an N-type transistor TB1 to which the signal VS1 from the attenuator 40 is input at its gate and VDD (second power supply). Power source) and its output node NA2.

  The amplifying unit 60 amplifies the signal VS2 after the DC level shift, and outputs the amplified signal VS6. The amplifying unit 60 has a frequency characteristic of a band pass filter, for example. Specifically, it has a band-pass filter characteristic having a center frequency in the frequency band (for example, 120 to 140 KHz) of the carrier wave (desired signal) of the received signal IN.

  The demodulation circuit 90 performs a demodulation process based on the signal VS6 from the amplification unit 60. That is, demodulation processing is performed in order to obtain an input digital signal from the ASK modulated signal.

  The control circuit 70 changes the attenuation amount of the attenuator 40 according to the amplitude (amplitude magnitude) of the output signal VS6 of the amplification unit 60. For example, the amplitude of the signal VS6 is detected, and automatic gain adjustment is performed to change the attenuation amount of the attenuator 40 based on the amplitude detection result.

  Specifically, by changing the filter characteristic (cut-off frequency) of the attenuator 40, the amplitude of the output signal VS6 of the amplifying unit 60 is constant (including almost constant) even when the amplitude of the received signal IN varies. Thus, the attenuation amount of the attenuator 40 is controlled. For example, when the attenuator 40 has a high-pass filter characteristic, the control circuit 70 controls the attenuation amount in the attenuator 40 by changing the cutoff frequency of the high-pass filter based on the amplitude (amplitude detection result) of the signal VS6. To do. For example, as the amplitude of the output signal VS6 of the amplification unit 60 increases, the cutoff frequency of the high-pass filter is increased to increase the attenuation amount of the received signal in the frequency band of the carrier wave.

  That is, in the smart entry system, since the signal from the in-vehicle device is wirelessly transmitted to the smart key portable device (electronic device), the amplitude of the received signal is, for example, 1 mV depending on the distance between the in-vehicle device and the portable device. It fluctuates significantly as several hundred mV. Therefore, even when the amplitude of the received signal fluctuates, it is necessary to automatically adjust the gain so that the amplitude of the output signal VS6 of the amplification unit 60 becomes constant. By performing such automatic gain adjustment, a signal VS6 having a constant amplitude is input to the demodulation circuit 90, and the demodulation processing in the demodulation circuit 90 is facilitated.

  In this case, as a method of the comparative example, a method of automatically adjusting the gain (amplification factor) of the amplification unit 60 to make the amplitude of the signal VS6 constant can be considered.

  However, according to the method of this comparative example, it is necessary to provide the amplifying unit 60 with an automatic gain adjustment function, and the circuit configuration of the amplifying unit 60 becomes complicated, or the bias current flowing through the operational amplifier constituting the amplifying unit 60 increases. It becomes difficult to realize low power consumption. In particular, in the smart entry system, since the portable device needs to constantly receive a transmission signal from the in-vehicle device, an increase in current consumption in the amplification unit 60 cannot be ignored.

  In this regard, in the present embodiment, automatic gain adjustment is realized by adjusting the attenuation amount in the attenuator 40. Therefore, the amplification unit 60 itself does not have to have an automatic gain adjustment function, so that the design of the operational amplifier constituting the amplification unit 60 can be simplified. Therefore, the bias current flowing through the operational amplifier of the amplification unit 60 can be easily reduced, the power consumption of the receiving circuit can be greatly reduced, and an optimum receiving circuit for a smart entry system or the like can be provided.

  That is, in FIG. 1, when the amplitude of the received signal IN is minimum (for example, 1 mV), the attenuation amount at the attenuator 40 is minimum, and appropriate signal amplification can be performed with the signal amplitude at that time and the current consumption is minimized. As a result, the operational amplifier of the amplifier 60 is optimally designed. As the amplitude of the reception signal IN increases, the attenuation amount of the attenuator 40 also increases. When the amplitude of the reception signal IN is maximum (for example, several hundred mV), the attenuation amount becomes maximum. Accordingly, even when the amplitude of the received signal IN is maximum, a signal having substantially the same amplitude as that when the amplitude is minimum is input to the amplification unit 60. Therefore, the operational amplifier optimally designed assuming that the amplitude is minimum It is possible to perform signal amplification using the.

  In the present embodiment, the amplifying unit 60 has a band-pass filter characteristic as indicated by A1 in FIG. Specifically, the frequency band of the carrier wave fd is set as the center frequency, the cut-off frequency on the low frequency side is set to fc1, and the cut-off frequency on the high frequency side is set to fc2 .

  If the amplifying unit 60 has such bandpass filter characteristics, the frequency component of the carrier wave (desired signal) can be passed and the frequency component of the unnecessary signal can be removed. As a result, an unnecessary signal such as a noise signal can be removed by the band-pass filter characteristics of the amplifying unit 60, so that the S / N ratio can be improved, and a stable operation of the demodulation circuit 90 at the subsequent stage can be realized. In addition, since the DC component can be cut, so-called DC offset free can be easily realized.

  On the other hand, the attenuator 40 has a high-pass filter characteristic as indicated by A2 in FIG. The control circuit 70 controls the attenuation amount of the attenuator 40 by changing the cutoff frequency fc of the high-pass filter based on the amplitude detection result.

  Specifically, for example, when the amplitude of the received signal IN is small, the cutoff frequency fc of the attenuator 40 is as indicated by A3 in FIG. 2, and the high-pass filter characteristic is as indicated by A4.

  That is, if the capacitance of the capacitor CA1 of the attenuator 40 is CA and the on-resistance of the transistor TA1 is RA, the cutoff frequency of the attenuator 40 is fc = 1 / (2π × CA × RA). When the amplitude of the reception signal IN is small, the control voltage VC from the control circuit 70 is low (for example, VC = 0V), so that the on-resistance RA of the transistor TA1 to which VC is input is increased. Therefore, the cut-off frequency fc = 1 / (2π × CA × RA) becomes small, and fc <fd as indicated by A3 in FIG. When fc <fd, the gain of the high-pass filter at the carrier frequency fd is, for example, 1, so that the attenuation of the attenuator 40 becomes small (substantially becomes zero).

  On the other hand, when the amplitude of the received signal IN increases, the cut-off frequency fc of the attenuator 40 becomes as indicated by A5 in FIG. 2, and the high-pass filter characteristic becomes as indicated by A6. That is, when the amplitude of the reception signal IN increases, the control voltage VC from the control circuit 70 increases (for example, VC = VDD), and the on-resistance RA of the transistor TA1 decreases. Accordingly, the cut-off frequency fc = 1 / (2π × CA × RA) is increased, and fc> fd as indicated by A5 in FIG. When fc> fd, the high-pass filter gain at the frequency fd is smaller than 1, and the attenuation of the attenuator 40 increases. Therefore, even when the amplitude of the reception signal IN varies, a signal having a substantially constant amplitude is input to the amplifying unit 60.

  In FIG. 1, since the attenuator 40 includes the capacitor CA1 and the transistor TA1, an increase in circuit scale can be minimized. Further, since an operational amplifier or the like is not used for adjusting the attenuation, an increase in power consumption can be suppressed to a minimum. Therefore, coupled with power saving in the amplification unit 60, the power consumption of the receiving circuit can be greatly reduced.

2. Detailed Configuration Example FIG. 3 shows a detailed configuration example of the receiving circuit. FIG. 3 shows an example of the configuration of the receiving circuit, and the receiving circuit of the present invention is not limited to the configuration of FIG. 3. For example, the attenuator 40, the DC level shifter 50, the amplifying unit 60, and the control circuit 70 are shown in FIG. May adopt different configurations.

  The attenuator 40 includes a pull-down transistor TA2 in addition to the capacitor CA1 and the transistor TA1. The pull-down transistor TA2 is provided between the output node NA1 of the attenuator 40 and VSS (first power supply), and pulls down the output node NA1. Specifically, the N-type pull-down transistor TA2 receives a bias voltage BA1 at its gate and causes a constant current to flow to the VSS side. The current supply capability is lower than that of the attenuation transistor TA1. For example, the pull-down transistor TA2 has a W / L (gate width / gate length) of, for example, about 1/10 to 1/50 of the attenuation transistor TA1.

  When such a pull-down transistor TA2 is provided, the node NA1 can be pulled down to, for example, 0 V (VSS) when the distance between the in-vehicle device and the portable device is large and the reception signal IN is not input. That is, since the attenuator 40 is provided with the DC cut capacitor CA1, the node NA1 is in a floating state when the reception signal IN has not arrived. Therefore, if the pull-down transistor TA2 is not provided, the potential of the node NA1 is not stable, and noise resistance may be deteriorated.

  In this regard, in FIG. 3, a pull-down transistor TA2 is provided. Therefore, even when the reception signal IN has not arrived and the control voltage VC is 0 V, for example, the potential of the node NA1 is pulled down and stabilized, so that noise resistance can be improved.

  The DC level shifter 50 includes an N-type transistor TB1 that receives a signal VS1 at its gate and a P-type transistor TB2 that receives a bias voltage BB1 at its gate. This transistor TB2 functions as the current source IS1 in FIG. Note that a resistor or the like functioning as a current source may be provided instead of the transistor TB2.

  The amplifying unit 60 includes a plurality of amplifying circuits 61 and 62 connected in cascade. Specifically, the amplifier circuit 61 amplifies the output signal VS2 from the DC level shifter 50, and outputs the amplified signal VS4 to the amplifier circuit 62. The amplifier circuit 62 amplifies the output signal VS4 from the amplifier circuit 61, and outputs the amplified signal VS6 to the demodulation circuit 90 and the control circuit 70. Note that the amplifier 60 may be provided with only one amplifier circuit, or may be provided with three or more cascaded amplifier circuits.

  The amplifier circuit 61 includes first and second operational amplifiers OPC1 and OPC2. Further, capacitors CC1 and CC2 functioning as a gain setting unit for setting the gain of the amplifier circuit 61 are included.

  The operational amplifier OPC1 receives the input signal VS2 from the DC level shifter 50 at its non-inverting input terminal (first input terminal in a broad sense). In the operational amplifier OPC2, the output of the operational amplifier OPC1 is input to the non-inverting input terminal (first input terminal), and the output is the inverting input terminal (second input terminal in a broad sense) and the inverting input terminal of the operational amplifier OPC1 ( 2nd input terminal). That is, the OPC 2 is a voltage follower-connected operational amplifier. Since the configuration of the amplifier circuit 62 is the same as that of the amplifier circuit 61, the description thereof is omitted. Further, the operational amplifier OPC2 can be modified to have a gain adjustment function.

  The reference voltage generation circuit 80 generates and outputs a reference voltage VREF.

  The control circuit 70 is provided between a charging capacitor CD1 provided between the charging node NC and VSS (first power supply), and between the charging node NC and VDD (second power supply in a broad sense). A charging transistor TD1 is included. A comparison circuit 72 (charge control circuit) included in the control circuit 70 performs a comparison process between the output signal VS6 of the amplifier 60 and the reference voltage VREF, and controls charging of the charging capacitor CD1 by the charging transistor TD1 based on the comparison result. To do. As a result, the voltage at the charging node NC is output to the attenuator 40 as the control voltage VC.

  FIG. 4 shows an example of a signal waveform for explaining the operation of the receiving circuit. As shown in B1 of FIG. 4, in the burst period TB, a burst signal having a given number of pulses is received as a reception signal IN from the in-vehicle device. The burst period TB corresponds to a preamble period, and a burst signal not subjected to ASK modulation is received in the burst period TB. Automatic gain adjustment of the reception signal IN is performed within the burst period TB.

  As shown in B2 of FIG. 4, in the transfer periods T0 and T1 following the burst period TB, an ASK-modulated signal corresponding to the logic levels 0 and 1 of the digital signal is transmitted. The lengths of the periods T0 and T1 are different (for example, T0 <T1), and by detecting the length of this period, it is detected which digital signal of logic level 0 or 1 is transmitted from the in-vehicle device. it can. Although T0 <T1 in FIG. 4, T0> T1 may be used.

  In B3 of FIG. 4, the received signal IN is a signal centered on 0V. As shown in B4, the DC level shifter 50 shifts the DC level of the received signal IN to the voltage level (VM) at the operating point (amplification center) of the small signal amplification of the amplifier 60. Then, as indicated by B5, the amplifier circuit 61 of the amplifier 60 amplifies the signal VS2 after the DC level shift, and outputs the amplified signal VS4. As indicated by B6, the amplifier circuit 62 amplifies the signal VS4 and outputs the amplified signal VS6.

  When the amplitude of the output signal VS6 of the amplifying unit 60 is larger than the reference voltage VREF from the reference voltage generation circuit 80, the output signal of the comparator included in the comparison circuit 72 changes and the signal VS7 becomes L level. Specifically, every time the amplitude of the pulse output of the signal VS6 exceeds the reference voltage VREF, the signal VS7 becomes L level, and the P-type transistor TD1 is turned on. Then, charging to the charging capacitor CD1 is performed via the charging transistor TD1, and the control voltage VC increases as indicated by B7 in FIG. This reduces the on-resistance of the attenuation transistor TA1.

  For example, assuming that the capacitance of the attenuation capacitor CA1 is CA and the on-resistance of the transistor TA1 is RA, the transfer function of the attenuator 40 is expressed by the following equation.

S = VS1 / IN = jω × CA × RA / (1 + jω × CA × RA) (1)
Accordingly, the cut-off frequency fc of the high-pass filter of the attenuator 40 is expressed by the following equation.

fc = 1 / (2π × CA × RA) (2)
The on-resistance RA of the transistor TA1 is expressed by the following equation.

RA = 1 / {μ × Cox × (W / L) × Vgs} (3)
Here, μ is the mobility of the transistor, Cox is the gate capacitance, W and L are the gate width and gate length of the transistor, and Vgs is the gate-source voltage.

  As apparent from the above equation (3), when the control voltage VC increases, Vgs increases, and the on-resistance RA decreases. As apparent from the above equation (2), when the on-resistance RA decreases, the cutoff frequency fc of the high-pass filter increases as indicated by A5 and A6 in FIG. As a result, the amount of attenuation at the attenuator 40 increases, and automatic gain adjustment by the attenuator 40 is realized.

  When automatic gain adjustment is performed in this way, the amplitude of the output signal VS6 of the amplifying unit 60 becomes substantially constant within the burst period TB as indicated by B8 in FIG. Since the amplitude of the signal VS6 becomes constant in this way, the demodulation circuit 90 that has received the signal VS6 can stably demodulate the ASK-modulated signal in the periods T0 and T1 after the burst period TB.

  The control circuit 70 includes a discharging transistor TD2 that is provided between the charging node NC and VSS (first power supply) and flows a constant current to the VSS side. The discharging transistor TD2 is, for example, a transistor having a lower current supply capability than the charging transistor TD1. For example, the W / L (gate width / gate length) of the discharge transistor TD2 is smaller than the W / L of TD1.

  More specifically, the discharge period set by the constant current flowing through the discharge transistor TD2 and the capacitance of the charging capacitor CD1 is the logic level 1 (first logic level in a broad sense) of the received signal that is ASK modulated. It is longer than the transfer period T1. That is, the bias voltage BD1 is input to the gate of the discharging transistor TD2, and thereby a constant current flows. The discharge period by the discharge transistor TD2 is set by the magnitude of this constant current and the capacitance of the charging capacitor CD1. The constant current flowing through the discharge transistor TD2 is set such that the discharge period is sufficiently longer than the transfer period T1 of the logic level 1 (for example, a period of 10 times or more of T1). Specifically, the magnitude of the bias voltage BD1 and the W / L of the discharging transistor TD2 are set.

  That is, the amplitude of the reception signal IN decreases as the distance between the in-vehicle device and the portable device increases, so that the reception circuit of this embodiment can detect the reception signal IN with a small amplitude so that the circuit constants of the reception circuit can be detected. Is set. Therefore, the noise signal is also detected as the reception signal IN, and there is a risk that the control voltage VC will increase. When the control voltage VC increases due to the noise signal and the on-resistance of the attenuation transistor TA1 decreases, the attenuation amount of the attenuator 40 is set to a large value before the original reception signal IN is input. Then, the amount of attenuation does not return from there, and there is a possibility that proper attenuation control cannot be realized.

  In this regard, in FIG. 3, a small constant current always flows to the VSS side by the discharging transistor TD2. Therefore, even if the potential of the control voltage VC increases due to the noise signal, the potential is returned to the VSS side by the discharging transistor TD2. As a result, the on-resistance of the transistor TA1 is reduced due to the noise signal, and it is possible to prevent the attenuation amount of the attenuator 40 from being set to a large value before the original reception signal IN is input.

  At this time, the discharge period by the discharge transistor TD2 is set to be sufficiently longer than the transfer period T1 of the logic level 1, which is the longer transfer period. Therefore, in the original data transfer period, the discharge by the discharge transistor TD2 can be almost ignored and proper data transfer can be realized.

  In FIG. 3, a wake-up transistor TD3 is also provided. The N-type transistor TD3 has a gate to which a control voltage VC is input, a source connected to VSS, and a wakeup signal WAKE output to the drain. Therefore, when the control voltage VC rises and becomes larger than the threshold voltage of the transistor TD3, for example, the wakeup signal WAKE becomes active (changes from H level to L level). As a result, the burst signal in the burst period TB is detected and notified to the receiving circuit and other circuits of the integrated circuit device including the receiving circuit that the wake-up should be performed.

  Further, in FIG. 3, a reset transistor TD9 is also provided. This N-type transistor TD9 has a reset signal input to its gate and a source connected to VSS. When the reset signal becomes H level (active), the charging node NC is reset to the VSS level.

3. Demodulator Circuit FIG. 5 shows a configuration example of the demodulator circuit 90, and FIG. 6 shows a signal waveform example for explaining its operation. The demodulation circuit 90 includes a reference voltage generation circuit 92, comparators CPF1 and CPF2 (comparison circuit), and a charge pump circuit 94 (SCF circuit).

  When the output signal VS6 from the amplifying unit 60 is input as indicated by D1 in FIG. 6, the comparator CPF1 compares the voltage level of the signal VS6 with the first reference voltage VREF1 from the reference voltage generation circuit 92. Do. As a result, the binarized clock signal VS11 is output from the comparator CPF1 as indicated by D2, and this clock signal VS11 is input to the charge pump circuit 94. Then, the charge pump circuit 94 performs a charge pump operation using a pumping capacitor and a backup capacitor (not shown) based on the clock signal VS11. As a result, the voltage level of the signal VS12 increases as indicated by D3 in FIG. Then, the comparator OPF2 performs a comparison process between the voltage level of the signal VS12 and the second reference voltage VREF2 from the reference voltage generation circuit 92. Then, a demodulated signal VS13 that is H level (active) when the voltage level of the signal VS12 exceeds VREF2 is output. Thereby, the demodulation of the signal from the vehicle-mounted device is realized.

  Note that the demodulation circuit 90 of FIG. 5 is an example, and the demodulation circuit 90 of the present invention is not limited to the configuration of FIG. For example, various modifications such as employing a method of detecting the envelope of the signal VS6 are possible.

4). Amplifier Circuit FIG. 7 shows a configuration example of the amplifier circuit 61 of the present embodiment. The amplifier circuit 61 of the present embodiment is not limited to the configuration shown in FIG. 7, and various modifications such as omitting some of the components or adding other components are possible. The amplifier circuit of this embodiment can also be applied to circuits other than the receiving circuit shown in FIG.

  The amplifier circuit 61 of the present embodiment includes a first operational amplifier OPC1 and a second operational amplifier OPC2. Moreover, the gain setting part 63 can be included.

  Here, the input signal VS2 is input to the non-inverting input terminal (first input terminal) of the first operational amplifier OPC1. In the second operational amplifier OPC2, the output (VS4) of the operational amplifier OPC1 is input to the non-inverting input terminal (first input terminal), and the output (VS3) is the inverting input terminal (second input terminal) and the operational amplifier. The signal is input to the inverting input terminal (second input terminal) of OPC1. That is, the OPC 2 is a voltage follower-connected operational amplifier.

  The gain setting unit 63 sets the gain of the amplifier circuit 61, and includes first and second capacitors CC1 and CC2. Specifically, the first capacitor CC1 is provided between the output of the operational amplifier OPC1 and the inverting input terminal (second input terminal) of the OPC1. The second capacitor CC2 is provided between the output of the operational amplifier OPC2 and VSS (first power supply in a broad sense). The configuration of the gain setting unit 63 is not limited to that shown in FIG. 7, and various modifications such as changing the connection relationship and changing circuit elements are possible.

  In this embodiment, for example, a high-speed operational amplifier is used as the operational amplifier OPC1, and a low-speed operational amplifier is used as the operational amplifier OPC2. Specifically, for example, the bias current flowing through the operational amplifier OPC1 is made larger than the bias current flowing through the operational amplifier OPC2, or the gate length of the transistors constituting the operational amplifier OPC1 is reduced. For example, when the first bias current flowing through the operational amplifier OPC1 is IB1 and the second bias current flowing through the operational amplifier OPC2 is IB2, IB1> IB2. For example, the bias current IB2 is set to about 1/10 to 1/40 of IB1. That is, a high-speed operational amplifier that operates even in a high frequency band is employed as the operational amplifier OPC1, and a low-speed operational amplifier that operates only in a low frequency band is employed as the operational amplifier OPC2. By doing so, it is possible to give the amplifier circuit 61 the frequency characteristics of a bandpass filter.

  For example, in FIG. 8, E1 represents the bandpass filter characteristic of the amplifier circuit 61, and E2 represents the lowpass filter characteristic of the operational amplifier OPC2. The operational amplifier OPC2 is a low-speed operational amplifier with a small bias current IB2, and has a low-pass filter characteristic as indicated by E2. Therefore, the operational amplifier OPC2 functions as a voltage follower-connected operational amplifier whose gain is G2 = 1 in a frequency band lower than the cut-off frequency fc3, but as a voltage follower-connected operational amplifier in a frequency band sufficiently higher than fc3. Stops functioning.

  In a frequency band lower than the cut-off frequency fc3, the OPC2 functions as a voltage follower-connected operational amplifier. Therefore, the output signal VS4 of the operational amplifier OPC1 is fed back to the inverting input terminal of the OPC1 as the input signal VS3 via the operational amplifier OPC2 connected to the voltage follower. Therefore, eventually, OPC1 also functions as a voltage follower-connected operational amplifier, and the gain G1 of the amplifier circuit 61 is set to approximately 1.

  When the signal frequency increases and the gain G2 of the operational amplifier OPC2 decreases as shown by E3 in FIG. 8, the OPC2 gradually stops functioning as a voltage follower-connected operational amplifier. As a result, the gain G1 of the amplifier circuit 61 gradually increases as indicated by E4.

  When the signal frequency becomes sufficiently higher than the cut-off frequency fc3 of the operational amplifier OPC2, the OPC2 does not function as a voltage follower-connected operational amplifier at all, and the OPC2 becomes as if it does not exist. Then, the amplifier circuit 61 is equivalent to a circuit composed of the operational amplifier OPC1 and the capacitors CC1 and CC2. Therefore, if the capacitors CC1 and CC2 have capacitances C1 and C2, the gain of the amplifier circuit 61 is set to G1 = C1 / C2. That is, the gain at the bandpass peak frequency fd (desired signal, carrier frequency) indicated by E5 in FIG. 8 is set to G1 = C1 / C2. When the signal frequency becomes higher than the frequency fd, the gain G1 of the amplifier circuit 61 gradually decreases as indicated by E6. In this manner, bandpass filter characteristics indicated by E4, E5, and E6 are set.

  That is, as indicated by F1 in FIG. 9, the cut-off frequency fc1 on the low frequency side of the bandpass filter of the amplifier circuit 61 is set by the output impedance ROUT2 of the operational amplifier OPC2 and the load capacitance COUT2 of the output node NA3 of OPC2. That is, the attenuation characteristic of the low-pass filter of the operational amplifier OPC2 indicated by E3 in FIG. 8 is determined by the output impedance ROUT2 of the OPC2 and the load capacitance COUT2 of the node NA3. The attenuation characteristic of the bandpass filter of the amplifier circuit 61 indicated by E4 is determined by the attenuation characteristic of the lowpass filter of the operational amplifier OPC2 indicated by E3. Therefore, the cut-off frequency fc1 on the low frequency side of the bandpass filter is determined by the output impedance ROUT2 of the operational amplifier OPC2 and the load capacitance COUT2.

  Note that the output impedance ROUT2 (current supply capability) of the operational amplifier OPC2 is determined by the bias current of the OPC2, the gate length of the transistors constituting the OPC2, and the like. For example, the output impedance ROUT2 decreases as the bias current increases or the gate length decreases.

  The load capacitance COUT2 of the node NA3 is determined by the capacitances of the capacitors CC1 and CC2, the gate capacitance of the inverting input terminal of the operational amplifier OPC1, the drain capacitance of the transistor of the operational amplifier OPC2 itself, the parasitic capacitance of the wiring of the node NA3, and the like.

  On the other hand, as indicated by F2 in FIG. 9, the cut-off frequency fc2 on the high frequency side of the bandpass filter is set by the output impedance ROUT1 of the operational amplifier OPC1 and the load capacitance COUT1 of the output node NA4 of OPC1. That is, the attenuation characteristic of the low-pass filter indicated by E7 in FIG. 8 is an attenuation characteristic determined by the output impedance ROUT1 of the operational amplifier OPC1 and the load capacitance COUT1 of the node NA4. The attenuation characteristic of the bandpass filter of the amplifier circuit 61 indicated by E6 is determined by the attenuation characteristic of the lowpass filter of the operational amplifier OPC1 indicated by E7. Therefore, the cut-off frequency fc2 on the high frequency side of the bandpass filter is determined by the output impedance ROUT1 of the operational amplifier OPC1 and the load capacitance COUT1 of the node NA4.

  Note that the output impedance ROUT1 of the operational amplifier OPC1 is determined by the bias current of the OPC1, the gate length of the transistors constituting the OPC1, and the like. The load capacitance COUT1 of the node NA4 is determined by the capacitance of the capacitor CC1, the gate capacitance of the non-inverting input terminal of the operational amplifier OPC2, the drain capacitance of the transistor of the operational amplifier OPC1 itself, the parasitic capacitance of the wiring of the node NA4, and the like.

  As described above, in this embodiment, a high-speed operational amplifier with a large bias current is used as the operational amplifier OPC1, and a low-speed operational amplifier with a small bias current is used as the operational amplifier OPC2. Therefore, a bandpass filter as shown in FIG. The characteristics can be realized. As a result, only signals in the frequency fd band of the desired signal (carrier wave) can be passed and signals in other frequency bands such as noise signals can be removed, so the S / N ratio and the like can be improved. The amplifier circuit 61 can have both an amplification function and a band-pass filter function. Therefore, since it is not necessary to provide a bandpass filter separately from the amplifier circuit 61, the circuit can be reduced in size and the power consumption can be reduced by reducing circuit elements.

5). Rail-to-Rail Operational Amplifier In this embodiment, a rail-to-rail operational amplifier can be adopted as the operational amplifier OPC2 of the amplifier circuit 61 as shown in FIG. However, in this embodiment, an operational amplifier other than the rail-to-rail type may be employed as the operational amplifier OPC2.

  For example, in FIG. 11, the output signal VS4 of the operational amplifier OPC1 is a signal having a given amplitude centered on the operating point of small signal amplification. If the operational amplifier OPC2 to which the output signal VS4 is input is not a rail-to-rail operational amplifier, dead zones are formed above and below the power supply range of VSS to VDD. In these dead zone regions, proper signal amplification by the operational amplifier OPC2 becomes impossible.

  On the other hand, as described with reference to FIG. 8, in the low frequency band such as the DC band, the operational amplifier OPC2 operates as a voltage follower-connected operational amplifier and feeds back the output signal VS4 of the operational amplifier OPC1 to the inverting input terminal of OPC1. Therefore, in order to stabilize the voltage level at the operating point of the output signal VS4, it is necessary to appropriately perform signal feedback by the operational amplifier OPC2 in the DC band.

  However, if the operational amplifier OPC2 is not a rail-to-rail operational amplifier, the feedback of the signal to the inverting input terminal of the operational amplifier OPC1 by the operational amplifier OPC2 is not properly performed in the dead zone region shown in FIG. For this reason, the operating point of the output signal VS4 is shifted to the VDD side or the VSS side, and proper small amplitude signal amplification cannot be realized.

  Further, as shown in FIG. 12, in order to obtain a high amplification factor, a plurality of amplifier circuits 61-1 and 61-2 may be cascade-connected. However, when such cascade connection is performed, the shift amount of the operating point further increases. As a result, the operating point enters the dead zone region and cannot be restored.

  In this respect, in this embodiment, a rail-to-rail operational amplifier is used as the operational amplifier OPC2. Therefore, the signal can be amplified in a balanced manner on both the upper side and the lower side around the operating point. As a result, the feedback imbalance of the signal from the output of the operational amplifier OPC1 to the inverting input terminal of the OPC1 can be reduced, and the phenomenon that the center level of the signal VS4 is shifted can be prevented. Thus, stable signal amplification can be realized even when a plurality of amplifier circuits 61-1 and 61-2 are cascade-connected as shown in FIG. In addition, it is possible to prevent a situation in which the center level of the output signal to the subsequent circuit of the amplifier circuit (for example, a demodulator circuit described later) is shifted and the processing of the subsequent circuit becomes difficult.

6). First Configuration Example FIG. 13 shows a first configuration example of a rail-to-rail operational amplifier OPC2. The operational amplifier OPC2 includes first and second differential units 102 and 104, an output unit 106, and first and second transistors TG11 and TG12.

  The first differential section 102 includes a first current mirror circuit composed of transistors TG1 and TG2, first differential pair transistors TG3 and TG4, and a first current source transistor TG5. Here, TG1 and TG2 are P-type transistors, and TG3, TG4, and TG5 are N-type transistors.

  The second differential unit 104 includes a second current mirror circuit composed of transistors TG6 and TG7, second differential pair transistors TG8 and TG9, and a second current source transistor TG10. Here, TG6 and TG7 are N-type transistors, and TG8, TG9, and TG10 are P-type transistors. The transistors TG13 and TG14 are circuits that generate a bias voltage for the transistor TG10.

  The output of the differential unit 102 is input to the output unit 106. Specifically, the output unit 106 includes a P-type transistor TG15 whose output is connected to the gate thereof, and an N-type transistor TG16 whose bias voltage BS5 is connected to its gate.

  The first transistor TG11 is provided between the first node NG1 and VSS (first power supply). Here, the first node NG1 is a drain node of one transistor TG3 of the first differential pair transistor of the first differential section 102. The node NG1 is connected to the gate of the transistor TG15 of the output unit 106. The transistor TG11 has the gate connected to the third node NG3. Here, the node NG3 is a drain node of one transistor TG9 of the second differential pair transistor of the second differential section 104.

  The second transistor TG12 is provided between the second node NG2 and VSS. Here, the second node NG2 is a drain node of the other transistor TG4 of the first differential pair transistor. The transistor TG12 has a gate connected to the fourth node NG4. Here, the node NG4 is a drain node of the other transistor TG8 of the second differential pair transistor.

  In FIG. 13, the gate of one transistor TG3 of the first differential pair transistor and the gate of the other transistor TG8 of the second differential pair transistor are connected in common. That is, the signal VS4 is input to these gates. The gate of the other transistor TG4 of the first differential pair transistor and the gate of one transistor TG9 of the second differential pair transistor are connected in common. That is, the output signal VS3 of the output unit 106 is input to these gates.

  In FIG. 13, even if the voltage of the signal VS4 is lowered and the N-type transistor TG3 of the differential unit 102 is turned off, the P-type transistor TG8 of the differential unit 104 is turned on. It is possible to amplify the signal VS4. Therefore, it is possible to prevent the dead zone from being formed below the power supply voltage range.

  In FIG. 13, even if the voltage of the signal VS4 is increased and the P-type transistor TG8 of the differential unit 104 is turned off, the P-type transistor TG3 of the differential unit 102 is turned on. Can be used to amplify the signal VS4. Therefore, it is possible to prevent the dead zone from being formed above the power supply voltage range.

  As described above, according to the configuration of FIG. 13, it is possible to prevent the formation of the dead zone at the lower side and the upper side of the power supply voltage range, and to realize a rail-to-rail operational amplifier. Therefore, the signal can be amplified in a balanced manner on both the upper side and the lower side around the operating point. As a result, the unbalance of the feedback of the signal from the output of the operational amplifier OPC1 to the inverting input terminal of the OPC1 can be reduced, and the situation where the operating point shifts can be prevented.

7). Second Configuration Example FIG. 14 shows a second configuration example of a rail-to-rail operational amplifier OPC2 and a configuration example of the operational amplifier OPC1.

  In FIG. 14, the operational amplifier OPC1 includes a differential unit (differential stage) and does not include an output unit (output stage). The operational amplifier OPC2 includes first and second differential units 66 and 68, and each differential unit does not include an output unit.

  The outputs (NA4, VS4) of the differential section 64 of the operational amplifier OPC1 are connected to the non-inverting input terminals (first input terminals) of the differential sections 66 and 68 of the operational amplifier OPC2. Specifically, for example, it is connected to the gate of one transistor of a differential pair transistor. The outputs of the differential section 66 and the output of the differential section 68 are connected in common, and the outputs (NA3, VS3) of the differential sections 66 and 68 are connected to the inverting input terminals (second output of the differential sections 66 and 68). Input terminal). Specifically, it is connected to the gate of the other transistor different from one of the differential pair transistors.

  As described above, the operational amplifiers OPC1 and OPC2 can be reduced in power consumption by adopting operational amplifiers including only the differential units 64, 66, and 68 without providing an output unit.

  That is, in the first configuration example of FIG. 13, since current flows through the output unit 106 and the first and second transistors TG11 and TG12, the consumption current of the operational amplifier increases by the amount of the current. In this regard, if the output unit or the like is not provided as shown in FIG. 14, the current flowing through the output unit or the like can be saved, and the power consumption can be reduced.

  In particular, in FIG. 14, by reducing the bias current IB2 flowing through the differential units 66 and 68 as much as possible, the attenuation characteristic of the low-pass filter of the operational amplifier OPC2 as shown by E3 in FIG. The attenuation characteristic of the band-pass filter of the amplifier circuit 61 is realized. That is, since the frequency characteristic of the bandpass filter is realized by eliminating the presence of the voltage follower-connected operational amplifier OPC2 in the high frequency band, the bias current flowing through the differential units 66 and 68 is limited to, for example, several nA. And very small. Therefore, even if the outputs of the differential units 66 and 68 are short-circuited, the through current generated thereby is about several nA and can be ignored.

  On the other hand, in FIG. 14, the bias current IB1 flowing through the differential section 64 is made larger than the bias current IB2 flowing through the differential sections 66 and 68, so that the low-pass filter of the operational amplifier OPC1 shown by E7 in FIG. Attenuation characteristics are realized, thereby realizing the attenuation characteristics of the band-pass filter of the amplifier circuit 61 as shown by E6. Therefore, since the bias current IB1 is large, the load capacity of the output can be sufficiently driven without providing the output section in the differential section 64.

  Therefore, according to the configuration of FIG. 14, the amplifier circuit 61 can be provided with both an amplification function and a band-pass filter function, and it is possible to realize low power consumption.

  FIG. 15 shows a more detailed configuration example of the differential units 64, 66, and 68. Note that the differential units 64, 66, and 68 are not limited to the configuration shown in FIG. 15, and various modifications such as omitting some of the components or adding other components are possible.

  As shown in FIG. 15, the differential section 64 of the operational amplifier OPC1 includes a current mirror circuit configured by transistors TC1 and TC2. Further, an input signal VS2 is input to the gate of one transistor TC3, and the outputs (NA3) of the first and second differential units 66 and 68 are connected to the gate of the other transistor TC4. Differential pair transistors TC3 and TC4 including. Further, a current mirror circuit (TC1, TC2) and a current source transistor TC5 for supplying a bias current flowing through the differential pair transistors TC3, TC4 are included.

  In FIG. 15, TC1 and TC2 are P-type transistors, and TC3, TC4, and TC5 are N-type transistors. A bias voltage BC1 is input to the gate of the transistor TC5.

  The first differential section 66 of the operational amplifier OPC2 includes a first current mirror circuit configured by P-type transistors TC6 and TC7. The output (NA4) of the differential unit 64 is connected to the gate of one N-type transistor TC8, and the outputs (NA3) of the first and second differential units 66 and 68 are connected to the gate of the other N-type transistor TC9. The first differential pair transistors TC8 and TC9 are connected. The first current mirror circuit (TC6, TC7) and the first differential pair transistors TC8, TC9 are supplied with a bias current flowing through the first current mirror circuit (TC6, TC7), and includes a first current source transistor TC10 configured by an N-type transistor.

  The second differential section 68 of the operational amplifier OPC2 includes a second current mirror circuit configured by N-type transistors TC11 and TC12. The output (NA4) of the differential section 64 is connected to the gate of one P-type transistor TC14, and the outputs (NA3) of the first and second differential sections 66 and 68 are connected to the gate of the other P-type transistor TC13. It includes a second differential pair transistor TC13, TC14 connected. Further, a bias current flowing through the second current mirror circuit (TC11, TC12) and the second differential pair transistors TC13, TC14 is supplied, and a second current source transistor TC15 configured by a P-type transistor is included.

  According to FIG. 15, a rail-to-rail operational amplifier can be configured by the differential units 66 and 68.

  That is, the signal VS4 output to the node NA4 has its small signal amplification operating point (amplification center) set to 0.8 to 1.0 V, for example. Therefore, if only the differential unit 66 is provided in the operational amplifier OPC2, the N-type transistor TC8 of the differential unit 66 is turned off in the voltage range below the operating point, and a dead zone region is formed below the power supply voltage range. There is a risk that.

  In this regard, in FIG. 15, a differential unit 68 is provided in addition to the differential unit 66. Therefore, even if the voltage at the node NA4 is lowered, the P-type transistor TC14 of the differential unit 68 is turned on, and thus the signal VS4 can be amplified using the differential unit 68. Therefore, it is possible to prevent the dead zone from being formed below the power supply voltage range.

  On the other hand, if only the differential unit 68 is provided in the operational amplifier OPC2, the P-type transistor TC14 of the differential unit 68 is turned off in the voltage range above the operating point, and a dead zone region is formed above the power supply voltage range. There is a risk that.

  In this regard, in FIG. 15, a differential unit 66 is provided in addition to the differential unit 68. Therefore, even if the voltage at the node NA4 is increased, the N-type transistor TC8 of the differential unit 66 is turned on, so that the signal VS4 can be amplified using the differential unit 66. Therefore, it is possible to prevent the dead zone from being formed above the power supply voltage range.

  As described above, according to the configuration of FIG. 15, it is possible to prevent the dead zone region from being formed below and above the power supply voltage range. Therefore, a rail-to-rail operational amplifier can be realized, and the signal can be amplified in a balanced manner on both the upper and lower sides with the operating point as the center. Therefore, the unbalance of the feedback of the signal from the output of the operational amplifier OPC1 to the inverting input terminal of the OPC1 can be reduced, and the phenomenon that the center level of the signal VS4 is shifted can be prevented.

  As described above, the bias current IB2 flowing through the differential units 66 and 68 is reduced as much as possible. Specifically, W / L (gate width / gate length) of the current source transistor TC10 is made as small as possible (for example, W / L = 1/10 to 1/30). Further, the W / L of the transistor TC15 is reduced, and the W / L of the N-type transistor that generates the bias voltage BC3 of the transistor TC15 is reduced as much as possible. As a result, the bias current IB2 is reduced to, for example, several nA.

  Therefore, even if a through current flows through a path from VDD to VSS via the transistors TC7 and TC11, or a path from VDD to the transistors TC15, TC13, TC9, and TC10 through VSS, the through current is, for example, several nA. The degree is very small. Therefore, even if the outputs of the differential units 66 and 68 are short-connected as shown in FIG. By short-circuiting the outputs of the differential units 66 and 68, it is not necessary to provide an output unit or the like in the operational amplifier OPC2, so that power consumption can be reduced and the circuit scale can be reduced.

8). In this embodiment, as shown in FIG. 16, when the offset voltage of the operational amplifier OPC1 is VOF1 and the offset voltage of the operational amplifier OPC2 is VOF2, VOF1> VOF2 is set. Specifically, the gate length of the differential pair transistors TC3 and TC4 constituting the operational amplifier OPC1 is L1, the gate width is W1, the gate length of the differential pair transistors TC8 and TC9 constituting the operational amplifier OPC2 is L2, and the gate width is W2. In this case, L1 × W1 <L2 × W2 is set.

  For example, by providing a plurality of amplifier circuits as shown in FIG. 7 and cascading them, a high amplification factor can be obtained. In this case, if the offset voltage of each amplifier circuit is large, the operating point shifts, and there is a possibility that an appropriate amplification operation cannot be realized.

  In this case, for example, a method of eliminating the influence of the offset voltage by providing a capacitor for DC cut between the first stage amplifier circuit and the second stage amplifier circuit may be considered. However, according to this method, in order to charge and discharge the DC cut capacitor, it is necessary to increase the current supply capability of the operational amplifier OPC1, and the power consumption increases.

  Therefore, in order to achieve both prevention of operating point shift and low power consumption, the offset voltage is reduced by increasing L × W = L2 × W2 of the differential pair transistor of the operational amplifier OPC2 (OPC4), It is desirable to directly connect a plurality of amplifier circuits without using a DC cut capacitor.

  However, in the present embodiment, as described above, a high-speed operational amplifier is used as the operational amplifier OPC1 and a low-speed operational amplifier is used as the operational amplifier OPC2 in order to reduce power consumption. Therefore, if L × W = L1 × W1 of the differential pair transistor TC4 of the operational amplifier OPC1 is increased in order to reduce the offset voltage, the drain capacity of the TC4 also increases, which hinders the speeding up of the operational amplifier OPC1.

  On the other hand, for the operational amplifier OPC2, even if L × W = L2 × W2 of the differential pair transistors TC8 and TC9 is increased in order to reduce the offset voltage, it is sufficient that the operational amplifier OPC2 originally operates at a low speed. There is no problem.

  Therefore, in this embodiment, L2 × W2 of the differential pair transistors TC8 and TC9 of the operational amplifier OPC2 is increased, and the offset voltage VOF2 is decreased. On the other hand, L1 × W1 of the differential pair transistor TC4 of the operational amplifier OPC1 is made smaller than L2 × W2, and the offset voltage is set to VOF1> VOF2. As a result, it is possible to achieve both prevention of operating point shift and low power consumption.

9. Layout FIG. 17 shows a layout example of the amplifier circuit of this embodiment. FIG. 17 shows a layout corresponding to the detailed configuration example of FIG. In FIG. 17, the right direction is the D1 direction (first direction), the upper direction is the D2 direction (second direction), the left direction is the D3 direction (third direction), and the lower direction is the D4 direction (fourth direction). Direction). However, these directions are arbitrary. For example, the left direction may be the D1 direction, and the downward direction may be the D2 direction.

  As indicated by G1 in FIG. 17, the differential pair transistors TC3 and TC4 of the differential section 64 of FIG. 15, the first differential pair transistors TC8 and TC9 of the first differential section 66, and the second difference The transistors TC11 and TC12 of the second current mirror circuit of the moving unit 68 are arranged along the direction D1. Specifically, the transistors TC8 and TC9 are arranged on the D1 direction side of the transistors TC3 and TC4, and the transistors TC11 and TC12 are arranged on the D1 direction side of the transistors TC8 and TC9.

  When the direction orthogonal to the D1 direction is the D2 direction, the second differential pair transistors TC13 and TC14 of the second differential section 68 are connected to the second current mirror circuit as shown by G2 in FIG. The transistors TC11 and TC12 are arranged on the D2 direction side. Specifically, the N-type transistors TC11 and TC12 are formed in the N-type transistor region (P well) together with the N-type transistors TC3, TC4, TC8, and TC9. In contrast, the P-type transistors TC13 and TC14 are formed in the P-type transistor region (N well) together with the P-type transistors TC1, TC2, TC6, and TC7.

  If the transistors are arranged in this way, the differential units 64, 66, and 68 can be arranged compactly along the direction D1, and the layout area of the amplifier circuit can be reduced. Further, the signal lines connecting the differential units 64, 66, and 68 can be connected by a short path, so that the wiring length can be shortened and the parasitic capacitance can be reduced.

  Further, as indicated by G3 in FIG. 17, the output line LNA4 (node NA4) of the differential section 64 is connected to the second current mirror circuit of the differential section 68 from the differential pair transistors TC3 and TC4 of the differential section 64. Wiring is performed along the direction D1 toward the transistors TC11 and TC12.

  Further, as indicated by G4, the output line LNA4 extends in the D2 direction from the transistors TC11 and TC12 of the second current mirror circuit of the differential unit 68 toward the second differential pair transistors TC13 and TC14 of the differential unit 68. Routed along. The output line LNA4 thus wired is connected to the drain of the transistor TC4 and to the gates of the transistors TC8 and TC14.

  In this way, the output line LNA4 of the differential section 64 is wired without waste in the D1 direction and the D2 direction, and connected to the drain of the transistor TC4 and the gates of the transistors TC8 and TC14, thereby amplifying the connection configuration shown in FIG. A circuit can be realized. Further, since the wiring length of the output line LNA4 can be shortened, the parasitic capacitance of the output line LNA4 can be reduced.

  When the direction opposite to the D1 direction is the D3 direction and the direction opposite to the D2 direction is the D4 direction, the output line NLA4 of the differential section 64 is connected to the differential pair transistors TC13 and TC14 as indicated by G5 in FIG. It is wired along the direction D3 toward the capacitor CC1, and is connected to one end of the capacitor CC1.

  As indicated by G6, the connection line LNA3 (node NA3) from the other end of the capacitor CC1 is wired along the direction D4 from the capacitor CC1 toward the differential pair transistors TC3 and TC4 of the differential section 64, and the transistor TC4. Connected to the gate.

  In this way, the output line LNA4 from the transistor TC4 is wired in a substantially U-shape as shown in FIG. 17 and wired to one end of the capacitor CC1, and the connection line LNA3 from the other end of the capacitor CC2 is connected to the transistor TC4. Come back to the place. That is, the output line LNA4 and the connection line LNA3 perform a substantially rectangular wiring without waste. Further, the transistors constituting the differential units 64, 66, and 68 and the capacitor CC1 can be compactly put together and laid out, and the layout area can be reduced.

  That is, as described above, in the present embodiment, a high-speed operational amplifier is employed as the operational amplifier OPC1 configured by the differential unit 64 in order to realize bandpass filter characteristics and improve responsiveness. Specifically, the bias current IB1 flowing through the transistor TC5 is made sufficiently larger than the bias current IB2 flowing through the transistor TC10, and the gate lengths of the transistors TC1 to TC4 are shortened.

  However, even if the bias current IB1 is increased in this way, if the load capacitance of the node NA4 is large, the operation speed of the operational amplifier OPC1 is hindered.

  In this regard, in FIG. 17, wiring of the output line LNA4 of the node NA4 is eliminated as much as possible, and wiring is performed so as to be connected to the gates of the transistors TC8 and TC14 and one end of the capacitor CC1 with a minimum distance. Therefore, the wiring length of the output line LNA4 can be minimized and the parasitic capacitance can be reduced, so that the operational amplifier OPC1 can be speeded up.

  As indicated by G7 in FIG. 17, the current source transistor TC5 of the differential section 64 is disposed on the D4 direction side of the differential pair transistors TC3 and TC4. As indicated by G8, the current source transistor TC10 (and the transistor for generating the bias voltage of the TC15) of the differential unit 66 is disposed on the D4 direction side of the differential pair transistors TC8 and TC9. In this way, an efficient layout becomes possible.

  That is, the gate width W of the current source transistor TC5 of the differential section 64 is set to a large value in order to increase the speed of the operational amplifier OPC1. Further, the gate length L is also set to a large value in order to stabilize the constant current flowing through the transistor TC5. Therefore, L × W, which is the gate area of the current source transistor TC5, increases as shown by G7 in FIG.

  On the other hand, the gate length L of the current source transistor TC10 of the differential unit 66 is set to a very large value in order to reduce the current by reducing the operational amplifier OPC2. Therefore, L × W, which is the gate area of the current source transistor TC10 (and the N-type transistor for generating the bias voltage of TC15), becomes large as indicated by G10 in FIG.

  In FIG. 17, the transistor TC5 is arranged using the empty area on the D4 direction side of the transistors TC3 and TC4, and the transistor TC10 is arranged using the empty area on the D4 direction side of the transistors TC8 and TC9. . Therefore, transistors can be arranged without waste, and the layout area can be reduced.

  That is, in FIG. 17, the transistors TC1 to TC4, TC6 to TC9, and TC11 to TC14 are arranged together to shorten the wiring length of the output line LNA4 and reduce its parasitic capacitance. On the other hand, transistors TC5 and TC10 having a large L × W are arranged in an empty area on the D4 direction side of these transistors TC1 to TC4, TC6 to TC9, and TC11 to TC14. This makes it possible to arrange the transistors constituting the operational amplifier in a compact and efficient manner while shortening the wiring length, and to improve both layout efficiency and circuit characteristics.

10. Modified Example of Receiving Circuit FIG. 18 shows a modified example of the receiving circuit. In FIG. 18, the amplifying unit 60 includes the amplifying circuit of the present embodiment described in FIGS. Instead of providing an attenuator, the amplification unit 60 has an automatic gain adjustment function.

  Specifically, the control circuit 71 detects the amplitude of the output signal VS6 of the amplification unit 60. Based on the amplitude detection result, a control signal VS for adjusting the gain is output to the amplifying unit 60. Then, the amplification unit 60 automatically adjusts the gain based on the control signal VS so that the amplitude of the signal VS6 becomes constant. Then, the adjusted signal VS6 is output to the demodulation circuit 90. The demodulation circuit 90 performs demodulation processing of the modulated signal based on the signal VS6.

  Also in the configuration of FIG. 18, according to the present embodiment, the amplifier circuit 61 can be provided with a bandpass filter function and an amplification function, so there is no need to separately provide a bandpass filter. Therefore, the circuit can be reduced in scale and power consumption can be reduced.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (VSS, VDD, logic level 1, etc.) described at least once together with different terms (first power supply, second power supply, first logic level, etc.) having a broader meaning or the same meaning ) May be replaced by the different terms anywhere in the specification or drawings. Further, the configurations and operations of the receiving circuit and the amplifier circuit are not limited to those described in this embodiment, and various modifications can be made.

2 is a configuration example of a receiving circuit according to the present embodiment. Explanatory drawing of the band pass filter characteristic of an amplifier. 3 shows a detailed configuration example of a receiving circuit. 7 is a signal waveform example for explaining the operation of the receiving circuit. 2 shows a configuration example of a demodulation circuit. 7 is a signal waveform example for explaining the operation of the demodulation circuit. 2 is a configuration example of an amplifier circuit according to the present embodiment. Explanatory drawing of the band pass filter characteristic of an amplifier circuit. Explanatory drawing of the cut-off frequency of a band pass filter. 2 is a configuration example of an amplifier circuit according to the present embodiment. Explanatory drawing of a dead zone area | region. Explanatory drawing about the shift of an operating point. 1 is a first configuration example of a rail-to-rail operational amplifier. The 2nd structural example of a rail-to-rail type | mold operational amplifier. Detailed example of second configuration example Explanatory drawing of the setting method of offset voltage. A layout example of an amplifier circuit. The modification of a receiving circuit.

Explanation of symbols

OPC1, OPC3 first operational amplifier, OPC2, OPC4 second operational amplifier,
CC1, CC2, CC3, CC4 capacitor, TD1 charging transistor,
TD2 discharge transistor, CD1 charge capacitor,
TA1 attenuation transistor, CA1 attenuation capacitor,
40 attenuator, 50 DC level shifter, 60 amplifier, 61 first amplifier circuit,
62 second amplifier circuit, 63 gain setting unit, 64 differential unit, 66 first differential unit,
68 second differential unit, 70 control circuit, 80 reference voltage generation circuit, 90 demodulation circuit,
92 reference voltage generation circuit, 94 charge pump circuit, 102 first differential section,
104 second differential unit, 106 output unit

Claims (6)

An attenuator that receives the received signal and attenuates the received signal;
A DC level shifter for performing DC level shift of the signal after attenuation;
An amplifying unit having frequency characteristics of a band-pass filter and amplifying a signal after the DC level shift;
A control circuit for controlling the attenuation amount of the attenuator based on the output signal of the amplifying unit;
The control circuit includes:
By changing the filter characteristic of the attenuator according to the amplitude of the output signal of the amplification unit, the amplitude of the output signal of the amplification unit is constant even when the amplitude of the reception signal changes. While controlling the attenuation of the attenuator ,
The control circuit includes:
A charge capacitor provided between the charge node and the first power supply; and a charge transistor provided between the charge node and the second power supply; and the amplitude of the output signal of the amplifying unit; A receiving circuit that performs reference voltage comparison processing, charges the charging capacitor by the charging transistor based on a comparison result, and outputs the voltage of the charging node to the attenuator as a control voltage . In claim 1,
The attenuator has a high-pass filter characteristic,
The control circuit includes:
A receiving circuit, wherein an attenuation amount in the attenuator is controlled by changing a cutoff frequency of the high-pass filter in accordance with an amplitude of the output signal of the amplifying unit. In claim 2,
The control circuit includes:
A receiving circuit that performs control to increase the cutoff frequency of the high-pass filter as the amplitude of the output signal of the amplifying unit increases to increase the attenuation amount of the received signal in the frequency band of the carrier wave . In any one of Claims 1 thru | or 3 ,
The control circuit includes:
A receiving circuit, comprising: a discharging transistor which is provided between the charging node and a first power supply and causes a constant current to flow to the first power supply side. In claim 4 ,
A receiving circuit, wherein a discharging period set by a constant current flowing through the discharging transistor and a capacitance of the charging capacitor is longer than a first logic level transfer period of the ASK modulated receiving signal. In any one of Claims 1 thru | or 5 ,
The attenuator is
An attenuation capacitor provided between an input node of the received signal and an output node of the attenuator;
A receiving circuit, comprising: an attenuation transistor which is provided between the output node and the first power supply and to which a control voltage from the control circuit is input at a gate thereof.

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