JP2010118831A - Automatic gain control circuit and receiving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an automatic gain control circuit in which an amplifier circuit has both of a bandpass filter characteristic and automatic gain control, and to provide a receiving circuit. <P>SOLUTION: The automatic gain control circuit includes: the amplifier circuit 61 having a frequency characteristic of a bandpass filter, receiving an input signal, amplifying the input signal and outputting an output signal; a control circuit 70 for outputting a control signal for controlling the gain of the amplifier circuit 61 on the basis of the output signal; and a cutoff frequency control circuit 100. The amplifier circuit 61 includes: a first operational amplifier whose first input terminal receives the input signal; and a second operational amplifier of a voltage follower connection whose first input terminal receives an output of the first operational amplifier and whose output is input to a second input terminal of the second operational amplifier and a second input terminal of the first operational amplifier. The cutoff frequency control circuit 100 controls the cutoff frequency of at least one of the first operational amplifier and the second operational amplifier on the basis of the control signal from the control circuit 70. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an automatic gain control circuit, a receiving circuit, and the like.

  For example, in a receiving circuit that receives a signal such as a radio signal, an amplifying circuit for amplifying the received signal is provided. In such an amplifier circuit, it is desirable that the gain of the amplifier circuit can be controlled according to the signal strength when the signal strength of the received signal changes. On the other hand, if the amplifier circuit has a band-pass filter characteristic for selectively extracting only a desired frequency component, an improvement in the S / N ratio can be expected.

  However, heretofore, no amplifier circuit that can realize both automatic gain control and band-pass filter characteristics has been proposed.

  Conventionally, a smart entry system that performs ID authentication when a user who has a smart key portable device approaches a car and confirms that the user is a legitimate user has been known. (Patent Document 1).

  In this smart entry system, the vehicle-mounted device transmits an ASK modulated signal in the LF band. When the user holding the portable device approaches the car, the antenna unit of the portable device detects the electric field of this signal, and when the receiving unit of the portable device receives the request signal from the in-vehicle device, the transmitting unit of the portable device receives the ID code. Send. When the ID codes match, the car door is unlocked and the like.

The receiver of this portable device is provided with an amplifier circuit for amplifying the received signal, but in actual use, the distance between the in-vehicle device and the portable device is not constant. The signal intensity varies greatly depending on the distance. Therefore, there is a problem that the gain of the amplifier circuit must be controlled according to the signal strength.
JP 2006-37493 A

  According to some aspects of the present invention, it is possible to provide an automatic gain control circuit capable of realizing both the band-pass filter characteristic of the amplifier circuit and the automatic gain control, a receiving circuit including the automatic gain control circuit, and the like.

  One embodiment of the present invention has a frequency characteristic of a bandpass filter, an input signal is input, an amplifier circuit that amplifies the input signal and outputs an output signal, and an amplifier circuit based on the output signal. A control circuit that outputs a control signal for controlling the gain; and a cutoff frequency control circuit, wherein the amplifier circuit includes a first operational amplifier in which the input signal is input to a first input terminal, and a first operational amplifier. The output of the first operational amplifier is input to the input terminal of the second operational amplifier, and the output of the first operational amplifier is input to the second input terminal and the second input terminal of the first operational amplifier. And the cut-off frequency control circuit includes a cut-off frequency of at least one of the first operational amplifier and the second operational amplifier based on the control signal from the control circuit. It relates to automatic gain control circuit and controls the frequency.

  According to one aspect of the present invention, the output of the first operational amplifier is fed back to the second input terminal of the first operational amplifier via the second operational amplifier connected to the second operational amplifier. Bandpass filter characteristics can be realized. Further, the automatic gain control of the amplifier circuit is realized by controlling the cutoff frequency of the first and second operational amplifiers by the control signal from the control circuit. As a result, it is possible to realize both the band-pass filter characteristics of the amplifier circuit and the automatic gain control.

  In one embodiment of the present invention, the cutoff frequency control circuit performs a control to lower the cutoff frequency of the first operational amplifier based on the control signal, thereby increasing the gain at the desired frequency of the amplifier circuit. It may be lowered.

  In this way, automatic gain control is realized by changing the frequency characteristics of the band-pass filter of the amplifier circuit by controlling the cut-off frequency of the first operational amplifier to lower the gain at the desired frequency of the amplifier circuit. it can.

  In one embodiment of the present invention, the cutoff frequency control circuit performs a control to increase a cutoff frequency of the second operational amplifier based on the control signal, whereby a gain at the desired frequency of the amplifier circuit is obtained. May be lowered.

  In this way, automatic gain control is realized by changing the frequency characteristics of the band-pass filter of the amplifier circuit by controlling to increase the cutoff frequency of the second operational amplifier, and lowering the gain at the desired frequency of the amplifier circuit. it can.

  In one embodiment of the present invention, the cutoff frequency control circuit performs control to lower the cutoff frequency of the first operational amplifier based on the control signal, and raises the cutoff frequency of the second operational amplifier. By performing control, the gain at the desired frequency of the amplifier circuit may be lowered.

  In this case, the frequency characteristic of the band-pass filter of the amplifier circuit is changed by the control for lowering the cutoff frequency of the first operational amplifier and the control for increasing the cutoff frequency of the second operational amplifier, so that the frequency characteristic of the amplifier circuit can be changed. Automatic gain control can be realized by lowering the gain.

  In one embodiment of the present invention, the cutoff frequency control circuit performs control to lower both the cutoff frequency of the first operational amplifier and the cutoff frequency of the second operational amplifier based on the control signal. The gain at the desired frequency of the amplifier circuit may be lowered.

  In this way, the frequency characteristics of the band-pass filter of the amplifier circuit are changed by the control to lower the cutoff frequency of the first and second operational amplifiers, and the gain at the desired frequency of the amplifier circuit is lowered, thereby automatically gaining the gain. Control can be realized.

  In one embodiment of the present invention, the cutoff frequency control circuit includes a reference current generation circuit, a first bias voltage generation circuit, and a second bias voltage generation circuit, and the first bias voltage generation circuit includes: Generating a first bias voltage having a voltage value corresponding to a current value obtained by subtracting the current generated based on the control signal from the reference current generated by the reference current generating circuit; The second bias voltage generation circuit generates a second bias voltage having a constant voltage value corresponding to the current value of the reference current generated by the reference current generation circuit to generate the second bias voltage. You may supply to an operational amplifier.

  In this way, the first bias voltage obtained by subtracting the current corresponding to the control signal from the reference current is supplied to the first operational amplifier, thereby realizing control for lowering the cutoff frequency of the first operational amplifier. it can.

  In one embodiment of the present invention, the cutoff frequency control circuit includes a reference current generation circuit, a first bias voltage generation circuit, and a second bias voltage generation circuit, and the first bias voltage generation circuit includes: Generating a first bias voltage having a constant voltage value corresponding to the current value of the reference current generated by the reference current generating circuit, supplying the first bias voltage to the first operational amplifier, and the second bias voltage generating circuit. Generates a second bias voltage having a voltage value corresponding to a current value obtained by adding the current generated based on the control signal to the reference current generated by the reference current generating circuit. You may supply to an operational amplifier.

  In this way, the second bias voltage obtained by adding the current according to the control signal to the reference current is supplied to the second operational amplifier, thereby realizing control for increasing the cutoff frequency of the second operational amplifier. it can.

  In one embodiment of the present invention, the cutoff frequency control circuit includes a reference current generation circuit, a first bias voltage generation circuit, and a second bias voltage generation circuit, and the first bias voltage generation circuit includes: Generating a first bias voltage having a voltage value corresponding to a current value obtained by subtracting the current generated based on the control signal from the reference current generated by the reference current generating circuit; And the second bias voltage generation circuit has a voltage value corresponding to a current value obtained by adding the current generated based on the control signal to the reference current generated by the reference current generation circuit. Two bias voltages may be generated and supplied to the second operational amplifier.

  As described above, the first bias voltage obtained by subtracting the current corresponding to the control signal from the reference current is supplied to the first operational amplifier, and the current corresponding to the control signal is added to the reference current. By supplying the second bias voltage to be supplied to the second operational amplifier, it is possible to realize control for lowering the cutoff frequency of the first operational amplifier and control for raising the cutoff frequency of the second operational amplifier.

  In one embodiment of the present invention, the cutoff frequency control circuit includes a reference current generation circuit and a first bias voltage generation circuit, and the first bias voltage generation circuit is generated by the reference current generation circuit. A bias voltage having a voltage value corresponding to a current value obtained by subtracting the current generated based on the control signal from the reference current may be generated and supplied to the first operational amplifier and the second operational amplifier. .

  In this way, by supplying a bias voltage obtained by subtracting a current corresponding to the control signal from the reference current to the first and second operational amplifiers, the cutoff frequency of the first operational amplifier and the second operational amplifier are obtained. It is possible to realize control that lowers both the cut-off frequencies.

  In one embodiment of the present invention, when the first bias current flowing through the first operational amplifier is IB1 and the second bias current flowing through the second operational amplifier is IB2, IB1> IB2 is set. The amplifier circuit having the frequency characteristics of the band-pass filter may be included.

  In this way, the first operational amplifier is a high-speed operational amplifier that operates even in a high frequency band, and the second operational amplifier is a low-speed operational amplifier that operates only in a low frequency band. It becomes possible to have.

  In the aspect of the invention, the cut-off frequency on the low frequency side of the bandpass filter is set by the output impedance of the second operational amplifier and the load capacitance of the output node of the second operational amplifier, and the bandpass The cutoff frequency on the high frequency side of the filter may be set by the output impedance of the first operational amplifier and the load capacitance of the output node of the first operational amplifier.

  In this way, by adjusting the output impedance and load capacitance of the second operational amplifier, the cut-off frequency on the low frequency side of the bandpass filter is set, and the output impedance and load capacitance of the first operational amplifier are adjusted. Thus, the cut-off frequency on the high frequency side of the bandpass filter can be set.

  In the aspect of the invention, the gain setting unit may include a first capacitor provided between an output of the first operational amplifier and the second input terminal of the first operational amplifier, and the second capacitor. A second capacitor provided between the output of the operational amplifier and the low potential side power supply node may be included.

  In this way, for example, the gain of the amplifier circuit at the center frequency of the bandpass filter can be set by the capacitance ratio of the first and second capacitors.

  In one embodiment of the present invention, when the offset voltage of the first operational amplifier is VOF1 and the offset voltage of the second operational amplifier is VOF2, VOF1> VOF2 may be set.

  In this way, it is possible to minimize the offset voltage of the amplifier circuit, and it is possible to achieve both prevention of operating point shift and low power consumption.

  In one embodiment of the present invention, the gate length of the differential pair transistor constituting the first operational amplifier is L1, the gate width is W1, and the gate length of the differential pair transistor constituting the second operational amplifier is L2. When the gate width is W2, L1 × W1 <L2 × W2 may be set.

  In this way, the relationship of VOF1> VOF2 can be established in the offset voltage by setting the gate length and gate width of the differential pair transistor.

  In the aspect of the invention, the second operational amplifier may be a rail-to-rail operational amplifier.

  In this way, the second operational amplifier can amplify the signal in a balanced manner on both the upper side and the lower side centering on the operating point of the small signal amplitude. As a result, the unbalance of the feedback of the signal from the output of the first operational amplifier to the inverting input terminal can be reduced, and a situation such as a shift of the operating point can be prevented.

  In the aspect of the invention, the first operational amplifier is configured by a differential unit, the second operational amplifier is configured by first and second differential units, and the differential unit of the first operational amplifier. Is connected to first input terminals of the first and second differential units of the second operational amplifier, and the output of the first differential unit and the output of the second differential unit are common. The outputs of the first and second differential units may be connected to the second input terminals of the first and second differential units.

  In this case, since the first operational amplifier can be configured by the differential unit and the second operational amplifier can be configured by the first and second differential units, the circuit scale can be reduced and power consumption can be reduced. In addition, the first and second differential sections can amplify the signal in a balanced manner on both the upper side and the lower side with the operating point as the center, thereby reducing the unbalance of the feedback of the signal from the output of the first operational amplifier to the inverting input terminal. .

  In one embodiment of the present invention, the differential section of the first operational amplifier includes a current mirror circuit, and the input signal is input to the gate of one transistor, and the first and second transistors are input to the gate of the other transistor. A differential pair transistor to which an output of the differential section is connected, and a current source transistor that supplies a bias current flowing through the current mirror circuit and the differential pair transistor, the first operational amplifier of the first operational amplifier The differential unit includes a first current mirror circuit configured by a P-type transistor, an output of the differential unit connected to a gate of one N-type transistor, and the first and A first differential pair transistor to which an output of the second differential section is connected, and a first current mirror circuit and a bi-directional current flowing through the first differential pair transistor; A second current mirror circuit including an N-type transistor, wherein the second differential section of the second operational amplifier includes an N-type transistor. And the output of the differential unit is connected to the gate of one P-type transistor, and the output of the first and second differential units is connected to the gate of the other P-type transistor. A bias current flowing through the transistor and the second current mirror circuit and the second differential pair transistor may be supplied, and a second current source transistor configured by a P-type transistor may be included.

  In this way, a rail-to-rail operational amplifier using the first and second differential units can be realized with a simple circuit configuration, and power consumption can be easily reduced.

  Another aspect of the present invention relates to a receiving circuit including any one of the automatic gain control circuit described above, a high-pass filter that receives a reception signal, and a DC level shifter that performs a DC level shift of an output signal of the high-pass filter. To do.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. Basic Configuration Example FIG. 1 shows a basic configuration example of the automatic gain control circuit of this embodiment. Note that the automatic gain control circuit of the present embodiment is not limited to the configuration shown in FIG. 1, and some of the components (for example, the gain setting unit) are omitted, replaced with other components, or other components are added. Various modifications can be made such as.

  The automatic gain control circuit of FIG. 1 includes an amplifier circuit 61, a control circuit 70, and a cutoff frequency control circuit 100. The amplifier circuit 61 includes a first operational amplifier OPC1, a second operational amplifier OPC2, and a gain setting unit 63.

  The amplifier circuit 61 has a frequency characteristic of a band-pass filter, amplifies the input signal IN, and outputs the amplified signal OUT. Specifically, the amplifier circuit 61 has a band-pass filter characteristic having a center frequency in the frequency band (for example, 120 to 140 KHz) of the carrier wave of the input signal IN that is a desired frequency.

  The control circuit 70 outputs a control signal VC for controlling the gain of the amplifier circuit 61 according to the amplitude (amplitude magnitude) of the output signal OUT of the amplifier circuit 61.

  The cut-off frequency control circuit 100 controls the cut-off frequency of at least one of the first operational amplifier OPC1 and the second operational amplifier OPC2 based on the control signal VC.

  Here, the input signal IN is input to the non-inverting input terminal (first input terminal in a broad sense) of the first operational amplifier OPC1. In the second operational amplifier OPC2, the output OUT of the operational amplifier OPC1 is input to the non-inverting input terminal (first input terminal in a broad sense), and the output is the inverting input terminal (second input terminal in a broad sense) and It is input to the inverting input terminal (second input terminal in a broad sense) of the operational amplifier OPC1. That is, the OPC 2 is a voltage follower-connected operational amplifier.

  The gain setting unit 63 sets the gain of the amplifier circuit 61, and includes first and second capacitors CC1 and CC2. Specifically, the first capacitor CC1 is provided between the output of the operational amplifier OPC1 and the inverting input terminal (second input terminal) of the OPC1. The second capacitor CC2 is provided between the output of the operational amplifier OPC2 and VSS (first power supply in a broad sense). The configuration of the gain setting unit 63 is not limited to this configuration example, and various modifications such as changing the connection relationship or changing the circuit elements are possible.

  In the present embodiment, for example, a high-speed operational amplifier is used as the operational amplifier OPC1, and a low-speed operational amplifier is used as the operational amplifier OPC2. Specifically, for example, the bias current flowing through the operational amplifier OPC1 is made larger than the bias current flowing through the operational amplifier OPC2, or the gate length of the transistors constituting the operational amplifier OPC1 is reduced. That is, a high-speed operational amplifier that operates even in a high frequency band is employed as the operational amplifier OPC1, and a low-speed operational amplifier that operates only in a low frequency band is employed as the operational amplifier OPC2. By doing so, it is possible to give the amplifier circuit 61 the frequency characteristics of a bandpass filter.

  The band-pass filter characteristics of the amplifier circuit 61 will be described with reference to FIG. For example, in FIG. 2, GF1 is a gain-frequency characteristic of the operational amplifier OPC1, GF2 is a gain-frequency characteristic of the operational amplifier OPC2, GF3 is a gain-frequency characteristic of the OPC1 when the output signal OUT is fed back through the OPC2, and GF4 is amplified. The gain vs. frequency characteristic of the circuit 61 is represented. The operational amplifier OPC2 is a low-speed operational amplifier with a small bias current IB2, and has a low-pass filter characteristic as indicated by GF2. Therefore, the operational amplifier OPC2 functions as a voltage follower-connected operational amplifier with a gain of 1 in a frequency band lower than the cutoff frequency fc3, but functions as a voltage follower-connected operational amplifier in a frequency band sufficiently higher than fc3. Disappear.

  In a frequency band lower than the cut-off frequency fc3, the OPC2 functions as a voltage follower-connected operational amplifier. Therefore, the output signal OUT of the operational amplifier OPC1 is fed back to the inverting input terminal of the OPC1 via the voltage follower-connected operational amplifier OPC2. Therefore, eventually, OPC1 also functions as a voltage follower-connected operational amplifier, and the gain of the amplifier circuit 61 is set to approximately 1 as indicated by A1 in FIG.

  When the signal frequency increases and the gain GF2 of the operational amplifier OPC2 decreases as shown by A2 in FIG. 2, the OPC2 gradually stops functioning as a voltage follower-connected operational amplifier. As a result, the gain GF4 of the amplifier circuit 61 gradually increases as indicated by A3.

  When the signal frequency becomes sufficiently higher than the cut-off frequency fc3 of the operational amplifier OPC2, the OPC2 does not function as a voltage follower-connected operational amplifier at all, and the OPC2 becomes as if it does not exist. Then, the amplifier circuit 61 is equivalent to a circuit composed of the operational amplifier OPC1 and the capacitors CC1 and CC2. Therefore, when the capacitors CC1 and CC2 are set to CA1 and CA2, the gain of the amplifier circuit 61 is set to GF1 = CA1 / CA2. That is, as indicated by A4 in FIG. 2, the gain at the peak frequency fd (desired signal, carrier frequency) of the bandpass filter characteristic is set to GF1 = CA1 / CA2. When the signal frequency becomes higher than the frequency fd, the gain GF4 of the amplifier circuit 61 gradually decreases as indicated by A5. In this way, the frequency characteristics of the bandpass filters indicated by A3, A4, and A5 are set.

  As described above, in this embodiment, a high-speed operational amplifier with a large bias current is used as the operational amplifier OPC1, and a low-speed operational amplifier with a small bias current is used as the operational amplifier OPC2, so that a bandpass filter as shown in FIG. The characteristics can be realized. As a result, only signals in the frequency fd band of the desired signal (carrier wave) can be passed and signals in other frequency bands such as noise signals can be removed, so the S / N ratio and the like can be improved. The amplifier circuit 61 can have both an amplification function and a band-pass filter function. Therefore, since it is not necessary to provide a bandpass filter separately from the amplifier circuit 61, the circuit can be reduced in size and the power consumption can be reduced by reducing circuit elements.

  In the smart entry system, since the signal from the in-vehicle device is wirelessly transmitted to the smart key portable device (electronic device), the amplitude of the received signal is, for example, 1 mV to 1 mV depending on the distance between the in-vehicle device and the portable device. It fluctuates greatly as several hundred mV. Therefore, even when the amplitude of the received signal fluctuates, it is necessary to automatically adjust the gain so that the amplitude of the output signal OUT of the amplifier circuit 61 becomes constant.

  In the present embodiment, when the input signal IN is minimum (for example, 1 mV), the amplifier circuit 61 is optimally designed so that proper signal amplification can be performed with the signal amplitude at that time and current consumption can be minimized. . When the amplitude of the input signal IN increases, the voltage of the control signal VC increases accordingly, and the cutoff frequency control circuit 100 receives a change in the voltage of the control signal VC, and supplies a bias voltage VB1 to be supplied to the operational amplifier OPC1. The bias voltage VB2 supplied to the operational amplifier OPC2 is changed.

  As described above, when the bias voltage VB1 increases and the bias current IB1 of the operational amplifier OPC1 increases, the cutoff frequency of the OPC1 increases. Conversely, when VB1 decreases and IB1 decreases, the cutoff frequency of OPC1 decreases. Similarly, when the bias voltage VB2 increases and the bias current IB2 of the operational amplifier OPC2 increases, the cutoff frequency of the OPC2 increases. Conversely, when VB2 decreases and IB2 decreases, the cutoff frequency of OPC2 decreases.

  Thus, by changing the bias voltages VB1 and VB2, the cutoff frequencies of the OPC1 and OPC2 can be changed. As described above, since the frequency characteristic of the bandpass filter of the amplifier circuit 61 is set by the cutoff frequency of OPC1 and OPC2, as a result, the gain at the desired frequency fd is controlled by changing the bias voltages VB1 and VB2. be able to.

  Specifically, for example, FIG. 3 shows a first method of gain control according to the present embodiment. 3, GF1a to GF1c are gain versus frequency characteristics of the operational amplifier OPC1, GF2 is a gain versus frequency characteristic of the operational amplifier OPC2, GF3 is a gain versus frequency characteristic of the OPC1 when the output signal OUT is fed back through the OPC2, and GF4a to GF4c represents the gain vs. frequency characteristic of the amplifier circuit 61.

  In the method shown in FIG. 3, when the amplitude of the input signal IN increases, the cut-off frequency control circuit 100 performs control to lower the cut-off frequency of the operational amplifier OPC1, and gain at a desired frequency fd (for example, the frequency of the carrier wave of the received signal). Reduce. For example, the cutoff frequency of the OPC 1 is set so that the gain at the desired frequency fd becomes maximum (indicated by B3 in FIG. 3) when the input signal IN is minimum. At this time, the gain-frequency characteristic of the OPC 1 is GF1a, and the gain-frequency characteristic of the amplifier circuit 61 is GF4a. Here, when the cutoff frequency of OPC1 decreases, the attenuation characteristics on the high frequency side of OPC1 change as indicated by B1 and B2. Corresponding to this change, the characteristics of the amplifier circuit 61 also change as indicated by B1 and B2. As a result, the gain at the desired frequency fd decreases from the maximum value shown in B3 to B4 and further to B5.

  As described above, according to the method shown in FIG. 3, the gain at the desired frequency fd is reduced to an appropriate value by lowering the cutoff frequency of the operational amplifier OPC1 as the amplitude of the input signal IN becomes larger than the minimum value. Can be reduced.

  In contrast to the situation described above, when the amplitude of the input signal IN decreases from a large value, the reverse control of the above control, that is, the cutoff frequency of the operational amplifier OPC1 is increased to increase the desired frequency fd. Gain can be increased to an appropriate value.

  FIG. 4 shows a second method of gain control according to this embodiment. 4, GF1 is a gain vs. frequency characteristic of the operational amplifier OPC1, GF2a to GF2c are gain vs frequency characteristics of the operational amplifier OPC2, GF3a to GF3c are gain vs frequency characteristics of the OPC1 when the output signal OUT is fed back via the OPC2, GF4a to GF4c represent gain versus frequency characteristics of the amplifier circuit 61.

  In the method shown in FIG. 4, when the amplitude of the input signal IN increases, the cutoff frequency control circuit 100 performs control to increase the cutoff frequency of the operational amplifier OPC2 to reduce the gain at the desired frequency fd. For example, the cutoff frequency of the OPC 2 is set so that the gain at the desired frequency fd becomes maximum (indicated by C3 in FIG. 4) when the input signal IN is minimum. At this time, the gain-frequency characteristic of the OPC2 is GF2a, the gain-frequency characteristic of the OPC1 when the output signal OUT is fed back is GF3a, and the gain-frequency characteristic of the amplifier circuit 61 is GF4a. Here, when the cutoff frequency of OPC2 increases, the attenuation characteristic on the high frequency side of OPC2 changes as indicated by C1 and C2. Corresponding to this change, the characteristics of the OPC1 due to feedback change as indicated by C6 and C7, and thus the characteristics of the amplifier circuit 61 also change as indicated by C6 and C7. As a result, the gain at the desired frequency fd decreases from the maximum value indicated by C3 to C4 and further to C5.

  As described above, according to the method shown in FIG. 4, the gain at the desired frequency fd is increased to an appropriate value by increasing the cutoff frequency of the operational amplifier OPC2 as the amplitude of the input signal IN becomes larger than the minimum value. Can be reduced.

  Contrary to the situation described above, when the amplitude of the input signal IN decreases from a large value, the reverse control of the above control, that is, the cutoff frequency of the operational amplifier OPC2 is lowered to reduce the desired frequency fd. Gain can be increased to an appropriate value.

  FIG. 5 shows a third method of gain control according to this embodiment. In FIG. 5, GF1a to GF1c are gain versus frequency characteristics of the operational amplifier OPC1, GF2a to GF2c are gain versus frequency characteristics of the operational amplifier OPC2, and GF3a to GF3c are gain versus frequency of the OPC1 when the output signal OUT is fed back via the OPC2. The characteristics, GF4a to GF4c, represent the gain vs. frequency characteristics of the amplifier circuit 61.

  In the method shown in FIG. 5, when the amplitude of the input signal IN increases, the cut-off frequency control circuit 100 performs control to lower the cut-off frequency of the operational amplifier OPC1 and performs control to increase the cut-off frequency of the operational amplifier OPC2 to obtain a desired frequency. Reduce the gain at fd. For example, the cutoff frequencies of OPC1 and OPC2 are set so that the gain at the desired frequency fd becomes maximum (indicated by D3 in FIG. 5) when the input signal IN is minimum. At this time, the gain-frequency characteristic of OPC1 is GF1a, the gain-frequency characteristic of OPC2 is GF2a, the gain-frequency characteristic of OPC1 when the output signal OUT is fed back is GF3a, and the gain of the amplifier circuit 61 The frequency characteristic is GF4a. Here, when the cutoff frequency of OPC1 decreases, the attenuation characteristics on the high frequency side of OPC1 change as indicated by D1 and D2. When the cutoff frequency of OPC2 increases, the attenuation characteristic on the high frequency side of OPC2 changes as indicated by D6 and D7, and the characteristic of OPC1 by feedback also changes as indicated by D8 and D9 in response to this change. To do. As a result, since the characteristic of the amplifier circuit 61 is a result of overlapping the changes shown in D1 and D2 and the changes shown in D8 and D9, the gain at the desired frequency fd is changed from the maximum value shown in D3 to D4 and further to D5. Decrease.

  In contrast to the situation described above, when the amplitude of the input signal IN decreases from a large value, the control opposite to the above control, that is, the cutoff frequency of the operational amplifier OPC1 is increased and the cutoff of the operational amplifier OPC2 is performed. By reducing the frequency, the gain at the desired frequency fd can be increased to an appropriate value.

  FIG. 6 shows a fourth method of gain control according to this embodiment. In FIG. 6, GF1a to GF1c are gain versus frequency characteristics of the operational amplifier OPC1, GF2a to GF2c are gain versus frequency characteristics of the operational amplifier OPC2, and GF3a to GF3c are gain versus frequency of the OPC1 when the output signal OUT is fed back through the OPC2. The characteristics, GF4a to GF4c, represent the gain vs. frequency characteristics of the amplifier circuit 61.

  In the method shown in FIG. 6, when the amplitude of the input signal IN increases, the cut-off frequency control circuit 100 performs control to lower both the cut-off frequency of the operational amplifier OPC1 and the cut-off frequency of the operational amplifier OPC2, thereby increasing the gain at the desired frequency fd. Reduce. For example, the cutoff frequency of each of OPC1 and OPC2 is set so that the gain at the desired frequency fd becomes maximum (indicated by E3 in FIG. 6) when the input signal IN is minimum. At this time, the gain-frequency characteristic of OPC1 is GF1a, the gain-frequency characteristic of OPC2 is GF2a, the gain-frequency characteristic of OPC1 when the output signal OUT is fed back is GF3a, and the gain of the amplifier circuit 61 The frequency characteristic is GF4a. Here, when the cut-off frequency of the OPC1 is lowered, the attenuation characteristics on the high frequency side of the OPC1 change as indicated by E1 and E2. When the cut-off frequency of OPC2 is lowered, the attenuation characteristic on the high frequency side of OPC2 changes as shown by E6 and E7, and the characteristic of OPC1 by feedback also changes as shown by E8 and E9 corresponding to this change. To do. As a result, since the characteristic of the amplifier circuit 61 is a result of overlapping the changes shown in E1 and E2 and the changes shown in E8 and E9, the gain at the desired frequency fd increases from the maximum value shown in E3 to E4 and further to E5. Decrease.

  Since the method shown in FIG. 6 performs control to lower the cutoff frequencies of the two operational amplifiers OPC1 and OPC2, it may be considered that the characteristic GF4a in the initial state is directly translated to the low frequency side. Accordingly, the peak position of the bandpass filter characteristic of the amplifier circuit 61 moves to the low frequency side as indicated by E3, E10, and E11 in FIG.

  Contrary to the situation described above, when the amplitude of the input signal IN decreases from a large value, the reverse control of the above control, that is, by increasing both the cutoff frequencies of the operational amplifiers OPC1 and OPC2, the desired frequency. The gain at fd can be increased to an appropriate value.

  Of the four methods described above with reference to FIGS. 3 to 6, the first method (FIG. 3) and the second method (FIG. 4) control only one cutoff frequency of the two operational amplifiers OPC1 and OPC2. Therefore, gain setting is easy. However, there is a drawback that the desired frequency shifts from the center frequency of the bandpass filter characteristics as the gain is lowered, and the S / N ratio decreases. Further, the fourth method (FIG. 6) has a drawback that the S / N ratio is lowered because the bandpass filter characteristic is translated to the low frequency side while maintaining the peak value of the gain. On the other hand, since the third method (FIG. 5) can reduce only the gain without shifting the center frequency of the bandpass filter characteristics, automatic gain control can be realized while maintaining a high S / N ratio. However, since the third method must simultaneously control the cutoff frequencies of the two operational amplifiers, the gain setting is more complicated than the other methods.

  As described above, in the basic configuration example of the present embodiment shown in FIG. 1, the amplifier circuit 61 can have a bandpass filter characteristic. The S / N ratio can be improved by removing the components. Furthermore, the gain of the amplifier circuit 61 can be automatically controlled so that the amplitude of the output signal of the amplifier circuit 61 becomes constant even when the amplitude of the input signal changes.

2. Cutoff Frequency Control Circuit FIGS. 7 to 10 show detailed configuration examples of the cutoff frequency control circuit 100 of the present embodiment. The cut-off frequency control circuit 100 of the present embodiment is not limited to the configuration of FIGS. 7 to 10, and some of the components are omitted, replaced with other components, or other components are added. Various modifications such as these are possible.

  FIG. 7 shows a first configuration example of the cutoff frequency control circuit 100. The cut-off frequency control circuit 100 of this configuration example includes first and second bias voltage generation circuits 101 and 102 and a reference current generation circuit 103. This configuration example uses the first gain control technique (FIG. 3) described above.

  Specifically, the first bias voltage generation circuit 101 subtracts the current IC generated based on the control signal VC from the reference current IREF generated by the reference current generation circuit 103 (IREF-IC). A first bias voltage VB1 having a voltage value corresponding to is generated and supplied to the operational amplifier OPC1. The second bias voltage generation circuit 102 generates a second bias voltage VB2 having a constant voltage value corresponding to the current value of the reference current IREF generated by the reference current generation circuit 103, and supplies the second bias voltage VB2 to the operational amplifier OPC2. To do.

  That is, when the amplitude of the input signal IN increases, the voltage of the control signal VC increases, and the current IC generated based on VC also increases. Therefore, the subtracted current value (IREF-IC) decreases, and as a result, OPC1 The bias voltage VB1 supplied to is reduced. Conversely, when the amplitude of the input signal IN decreases, the voltage of the control signal VC decreases and the current IC generated based on VC also decreases. Therefore, the subtracted current value (IREF-IC) increases, resulting in OPC1. The bias voltage VB1 supplied to is increased. On the other hand, the bias voltage VB2 supplied to the OPC2 maintains a constant voltage value corresponding to the current value of the reference current IREF regardless of changes in VC.

  More specifically, for example, as shown in FIG. 7, the cutoff frequency control circuit 100 in the first configuration example includes P-type transistors TP1 to TP3, TP5 and TP6, and N-type transistors TN1 to TN6. TP6 and TN6 generate a reference current IREF corresponding to a constant bias voltage VR. The control signal VC output from the control circuit 70 is supplied to the gate of TN1, and a current IC corresponding to VC flows through TP1 and TN1. Since TP1 and TP2 constitute a current mirror circuit, a current IC1 having a current value equal to that of the IC flows through TP2 and TN2. Furthermore, since TN2 and TN3 also constitute a current mirror circuit, a current ID1 having a current value equal to that of IC1 flows through TN3. Since TP3 and TP6 also constitute a current mirror circuit, a current IS1 equal to the reference current IREF flows through TP3. Here, IS1 is divided into a current IA1 and a current ID1 at the node N1, but IA1 = IS1-ID1 is established from the current conservation law (Kirchhoff's law). Since the current IA1 flows through the diode-connected TN4, a voltage corresponding to IA1 (= IREF-IC) is eventually generated at the node N1, and this becomes the bias voltage VB1.

  On the other hand, since TP5 and TP6 constitute a current mirror circuit, a current IS2 equal to the reference current IREF flows through TP5 and TN5. Since TN5 is diode-connected, a constant voltage corresponding to the reference current IREF is generated, and this becomes the bias voltage VB2.

  As described above, according to the first configuration example of the cutoff frequency control circuit 100 shown in FIG. 7, the gain of the amplifier circuit 61 is automatically controlled by the above-described first gain control technique (FIG. 3). be able to.

  FIG. 8 shows a second configuration example of the cutoff frequency control circuit 100. The cut-off frequency control circuit 100 of this configuration example includes first and second bias voltage generation circuits 101 and 102 and a reference current generation circuit 103. This configuration example uses the above-described second gain control method (FIG. 4).

  Specifically, the first bias voltage generation circuit 101 generates a first bias voltage VB1 having a constant voltage value corresponding to the current value of the reference current IREF generated by the reference current generation circuit 103 to generate an operational amplifier. Supply to OPC1. The second bias voltage generation circuit 102 also has a voltage value corresponding to a current value (IREF + IC) obtained by adding the current IC generated based on the control signal VC to the reference current IREF generated by the reference current generation circuit 103. Is generated and supplied to the operational amplifier OPC2.

  That is, when the amplitude of the input signal IN increases, the voltage of the control signal VC increases, and the current IC generated based on the VC also increases. Therefore, the added current value (IREF + IC) increases, and is supplied to the OPC 2 as a result. The applied bias voltage VB2 increases. Conversely, when the amplitude of the input signal IN decreases, the voltage of the control signal VC decreases, and the current IC generated based on VC also decreases. Therefore, the added current value (IREF + IC) decreases, and as a result, is supplied to the OPC 2 The applied bias voltage VB2 is lowered. On the other hand, the bias voltage VB1 supplied to the OPC1 maintains a constant voltage value corresponding to the current value of the reference current IREF regardless of a change in VC.

  More specifically, for example, as shown in FIG. 8, the cutoff frequency control circuit 100 in the second configuration example includes P-type transistors TP1, TP3 to TP6, and N-type transistors TN1, TN4 to TN6. TP6 and TN6 generate a reference current IREF corresponding to a constant bias voltage VR. The control signal VC output from the control circuit 70 is supplied to the gate of TN1, and a current IC corresponding to VC flows through TP1 and TN1. Since TP1 and TP4 constitute a current mirror circuit, a current IC2 having a current value equal to that of the IC flows through TP4. Since TP5 and TP6 also constitute a current mirror circuit, a current IS2 equal to the reference current IREF flows through TP5. Here, IC2 and IS2 merge at node N2 and become current IA2, but IA2 = IC2 + IS2 holds from the current conservation law (Kirchhoff's law). Since the current IA2 flows through the diode-connected TN5, a voltage corresponding to IA2 (= IREF + IC) is eventually generated at the node N2, and this becomes the bias voltage VB2.

  On the other hand, since TP3 and TP6 constitute a current mirror circuit, a current IS1 equal to the reference current IREF flows through TP3 and TN4. Since TN4 is diode-connected, a constant voltage corresponding to the reference current IREF is eventually generated, and this becomes the bias voltage VB1.

  As described above, according to the second configuration example of the cutoff frequency control circuit 100 shown in FIG. 8, the gain of the amplifier circuit 61 is automatically controlled by the above-described second gain control technique (FIG. 4). be able to.

  FIG. 9 shows a third configuration example of the cutoff frequency control circuit 100. The cut-off frequency control circuit 100 of this configuration example includes first and second bias voltage generation circuits 101 and 102 and a reference current generation circuit 103. This configuration example uses the above-described third gain control technique (FIG. 5).

  Specifically, the first bias voltage generation circuit 101 subtracts the current IC generated based on the control signal VC from the reference current IREF generated by the reference current generation circuit 103 (IREF-IC). A first bias voltage VB1 having a voltage value corresponding to is generated and supplied to the operational amplifier OPC1. The second bias voltage generation circuit 102 also has a voltage value corresponding to a current value (IREF + IC) obtained by adding the current IC generated based on the control signal VC to the reference current IREF generated by the reference current generation circuit 103. Is generated and supplied to the operational amplifier OPC2.

  That is, when the amplitude of the input signal IN increases, the voltage of the control signal VC increases, and the current IC generated based on VC also increases. Therefore, the subtracted current value (IREF-IC) decreases, and as a result, OPC1 The bias voltage VB1 supplied to is reduced. On the other hand, the added current value (IREF + IC) increases, and as a result, the bias voltage VB2 supplied to the OPC2 increases. Conversely, when the amplitude of the input signal IN decreases, the voltage of the control signal VC decreases and the current IC generated based on VC also decreases. Therefore, the subtracted current value (IREF-IC) increases, resulting in OPC1. The bias voltage VB1 supplied to is increased. On the other hand, the added current value (IREF + IC) decreases, and as a result, the bias voltage VB2 supplied to the OPC2 decreases.

  More specifically, for example, as shown in FIG. 9, the cutoff frequency control circuit 100 in the third configuration example includes P-type transistors TP1 to TP6 and N-type transistors TN1 to TN6. TP6 and TN6 generate a reference current IREF corresponding to a constant bias voltage VR. The control signal VC output from the control circuit 70 is supplied to the gate of TN1, and a current IC corresponding to VC flows through TP1 and TN1. Since TP1 and TP2 constitute a current mirror circuit, a current IC1 having a current value equal to that of the IC flows through TP2 and TN2. Furthermore, since TN2 and TN3 also constitute a current mirror circuit, a current ID1 having a current value equal to that of IC1 flows through TN3. Since TP3 and TP6 also constitute a current mirror circuit, a current IS1 equal to the reference current IREF flows through TP3. Here, IS1 is divided into a current IA1 and a current ID1 at the node N1, but IA1 = IS1-ID1 is established from the current conservation law (Kirchhoff's law). Since the current IA1 flows through the diode-connected TN4, a voltage corresponding to IA1 (= IREF-IC) is eventually generated at the node N1, and this becomes the bias voltage VB1.

  On the other hand, since TP1 and TP4 constitute a current mirror circuit, a current IC2 having a current value equal to that of the IC flows through TP4. Since TP5 and TP6 also constitute a current mirror circuit, a current IS2 equal to the reference current IREF flows through TP5. Here, IC2 and IS2 merge at node N2 and become current IA2, but IA2 = IC2 + IS2 holds from the current conservation law (Kirchhoff's law). Since the current IA2 flows through the diode-connected TN5, a voltage corresponding to IA2 (= IREF + IC) is eventually generated at the node N2, and this becomes the bias voltage VB2.

  As described above, according to the third configuration example of the cutoff frequency control circuit 100 shown in FIG. 9, the gain of the amplifier circuit 61 is automatically controlled by the third gain control technique (FIG. 5) described above. be able to.

  FIG. 10 shows a fourth configuration example of the cutoff frequency control circuit 100. The cut-off frequency control circuit 100 of this configuration example includes a first bias voltage generation circuit 101 and a reference current generation circuit 103. This configuration example uses the above-described fourth gain control technique (FIG. 6).

  Specifically, the first bias voltage generation circuit 101 subtracts the current IC generated based on the control signal VC from the reference current IREF generated by the reference current generation circuit 103 (IREF-IC). First and second bias voltages VB1 and VB2 having voltage values corresponding to are generated and supplied to the operational amplifiers OPC1 and OPC2, respectively.

  That is, when the amplitude of the input signal IN increases, the voltage of the control signal VC increases, and the current IC generated based on VC also increases. Therefore, the subtracted current value (IREF-IC) decreases, resulting in a bias. Both the voltages VB1 and VB2 are lowered. Conversely, when the amplitude of the input signal IN decreases, the voltage of the control signal VC decreases, and the current IC generated based on VC also decreases. Therefore, the subtracted current value (IREF-IC) increases, resulting in a bias. Both voltages VB1 and VB2 rise.

  More specifically, for example, as shown in FIG. 10, the cutoff frequency control circuit 100 in the fourth configuration example includes P-type transistors TP1 to TP3 and TP6 and N-type transistors TN1 to TN4 and TN6. TP6 and TN6 generate a reference current IREF corresponding to a constant bias voltage VR. The control signal VC output from the control circuit 70 is supplied to the gate of TN1, and a current IC corresponding to VC flows through TP1 and TN1. Since TP1 and TP2 constitute a current mirror circuit, a current IC1 having a current value equal to that of the IC flows through TP2 and TN2. Furthermore, since TN2 and TN3 also constitute a current mirror circuit, a current ID1 having a current value equal to that of IC1 flows through TN3. Since TP3 and TP6 also constitute a current mirror circuit, a current IS1 equal to the reference current IREF flows through TP3. Here, IS1 is divided into a current IA1 and a current ID1 at the node N1, but IA1 = IS1-ID1 is established from the current conservation law (Kirchhoff's law). Since the current IA1 flows through the diode-connected TN4, a voltage corresponding to IA1 (= IREF-IC) is eventually generated at the node N1, and these become the bias voltages VB1 and VB2.

  As described above, according to the fourth configuration example of the cutoff frequency control circuit 100 shown in FIG. 10, the gain of the amplifier circuit 61 is automatically controlled by the above-described fourth gain control technique (FIG. 6). be able to.

  In each of the four configuration examples described above, a current necessary for generating a bias voltage is obtained using a current mirror circuit. In the above description, the case where the mirror ratio of all the current mirror circuits (for example, the current ratio of IC and IC1) is 1 has been described. However, the mirror ratio of each current mirror circuit is a different value other than 1. Can be set to By doing so, the range in which the bias voltages VB1 and VB2 change can be set to a more desirable range. This mirror ratio can be set to an arbitrary value by changing the ratio of the gate width (channel width) of the two transistors constituting the current mirror circuit.

  The cut-off frequency control circuit 100 according to the present embodiment is not limited to the configuration shown in FIGS. 7 to 10 described above, and some of the components may be omitted or replaced with other components. Various modifications such as adding components are possible.

  For example, FIG. 11 shows one of the modifications. The modification of FIG. 11 is obtained by adding P-type transistors TP7 to TP9 to the above-described first configuration example (FIG. 7). The added TP7 to TP9 constitute a level shifter, and the potential of the control signal VC is raised to an appropriate potential and then input to the gate of the N-type transistor TN1. By doing so, the relationship between the potential of the control signal VC and the current IC generated based on the control signal VC can be made more desirable. Specifically, when there is no level shifter (FIG. 7), since the control signal VC is directly input to the gate of TN1, the current IC rapidly changes with a slight potential change near the threshold voltage. End up. As a result, the control signal VC is easily affected by noise and variations in transistor characteristics. On the other hand, when the level shifter is provided (FIG. 11), the gate voltage changes in a region higher than the threshold voltage, so that the change in the current IC becomes gentle. Therefore, it is less affected by noise of the control signal VC and variations in transistor characteristics, and a more stable operation can be obtained.

  The modified example (FIG. 11) is obtained by adding a level shifter to the first configuration example (FIG. 7), but in addition to the above-described second to fourth configuration examples (FIGS. 8 to 10). It can also be added.

3. Amplifier Circuit FIG. 12 shows a basic configuration example of the amplifier circuit 61 of the present embodiment. Note that the amplifier circuit 61 of the present embodiment is not limited to the configuration of FIG. 12, and various modifications such as omitting some of the components, replacing with other components, and adding other components. Is possible.

  In the present embodiment, for example, a high-speed operational amplifier is used as the operational amplifier OPC1, and a low-speed operational amplifier is used as the operational amplifier OPC2. Specifically, for example, the bias current flowing through the operational amplifier OPC1 is made larger than the bias current flowing through the operational amplifier OPC2, or the gate length of the transistors constituting the operational amplifier OPC1 is reduced. For example, as shown in FIG. 12, when the first bias current flowing through the operational amplifier OPC1 is IB1 and the second bias current flowing through the operational amplifier OPC2 is IB2, IB1> IB2 is set. For example, the bias current IB2 is set to about 1/10 to 1/40 of IB1. That is, a high-speed operational amplifier that operates even in a high frequency band is employed as the operational amplifier OPC1, and a low-speed operational amplifier that operates only in a low frequency band is employed as the operational amplifier OPC2. By doing so, it is possible to give the amplifier circuit 61 the frequency characteristics of a bandpass filter. That is, as indicated by F1 in FIG. 13, the cut-off frequency fc1 on the low frequency side of the bandpass filter of the amplifier circuit 61 is set by the output impedance ROUT2 of the operational amplifier OPC2 and the load capacitance COUT2 of the output node NA3 of OPC2.

  Note that the output impedance ROUT2 (current supply capability) of the operational amplifier OPC2 is determined by the bias current IB2 of the OPC2, the gate length of the transistors constituting the OPC2, and the like. For example, the output impedance ROUT2 decreases as the bias current increases or the gate length decreases. The load capacitance COUT2 of the node NA3 is determined by the capacitances of the capacitors CC1 and CC2, the gate capacitance of the inverting input terminal of the operational amplifier OPC1, the drain capacitance of the transistor of the operational amplifier OPC2 itself, the parasitic capacitance of the wiring of the node NA3, and the like.

  On the other hand, as indicated by F2 in FIG. 13, the cut-off frequency fc2 on the high frequency side of the bandpass filter is set by the output impedance ROUT1 of the operational amplifier OPC1 and the load capacitance COUT1 of the output node NA4 of OPC1.

  Note that the output impedance ROUT1 of the operational amplifier OPC1 is determined by the bias current IB1 of the OPC1, the gate length of the transistor constituting the OPC1, and the like. The load capacitance COUT1 of the node NA4 is determined by the capacitance of the capacitor CC1, the gate capacitance of the non-inverting input terminal of the operational amplifier OPC2, the drain capacitance of the transistor of the operational amplifier OPC1 itself, the parasitic capacitance of the wiring of the node NA4, and the like.

  FIG. 14 shows a detailed configuration example of the amplifier circuit 61. In FIG. 14, a rail-to-rail operational amplifier is employed as the operational amplifier OPC2 of the amplifier circuit 61. However, in this embodiment, an operational amplifier other than the rail-to-rail type may be employed as the operational amplifier OPC2.

  In FIG. 14, the operational amplifier OPC1 includes a differential unit (differential stage) and does not include an output unit (output stage). The operational amplifier OPC2 includes first and second differential units 66 and 68, and each differential unit does not include an output unit.

  The outputs (NA4, VS4) of the differential section 64 of the operational amplifier OPC1 are connected to the non-inverting input terminals (first input terminals) of the differential sections 66 and 68 of the operational amplifier OPC2. Specifically, for example, it is connected to the gate of one transistor of a differential pair transistor. The outputs of the differential section 66 and the output of the differential section 68 are connected in common, and the outputs (NA3, VS3) of the differential sections 66 and 68 are connected to the inverting input terminals (second output of the differential sections 66 and 68). Input terminal). Specifically, it is connected to the gate of the other transistor different from one of the differential pair transistors.

  As described above, the operational amplifiers OPC1 and OPC2 can be reduced in power consumption by adopting operational amplifiers including only the differential units 64, 66, and 68 without providing an output unit. That is, since a bias current flows in an output section provided in a general operational amplifier, the consumption current of the operational amplifier increases by the bias current. In this regard, if the output unit is not provided as shown in FIG. 14, the bias current flowing through the output unit can be saved, and the power consumption can be reduced.

  In particular, in the present embodiment, by reducing the bias current IB2 flowing through the differential units 66 and 68 as much as possible, the attenuation characteristic of the low-pass filter of the operational amplifier OPC2 as shown by A2 in FIG. The attenuation characteristic of the bandpass filter of the amplifying circuit 61 is realized. That is, since the frequency characteristic of the bandpass filter is realized by eliminating the presence of the voltage follower-connected operational amplifier OPC2 in the high frequency band, the bias current flowing through the differential units 66 and 68 is limited to, for example, several nA. And very small. Therefore, even if the outputs of the differential units 66 and 68 are short-circuited, the through current generated thereby is about several nA and can be ignored.

  On the other hand, in the present embodiment, the bias current IB1 flowing through the differential section 64 is made larger than the bias current IB2 flowing through the differential sections 66 and 68, so that the low-pass filter of the operational amplifier OPC1 as shown by A6 in FIG. Thus, the attenuation characteristic of the bandpass filter of the amplifier circuit 61 as shown in A5 is realized. Therefore, since the bias current IB1 is large, the load capacity of the output can be sufficiently driven without providing the output section in the differential section 64.

  Therefore, according to the configuration of FIG. 14, the amplifier circuit 61 can be provided with both an amplification function and a band-pass filter function, and it is possible to realize low power consumption.

  FIG. 15 shows a more detailed configuration example of the differential units 64, 66, and 68. Note that the differential units 64, 66, and 68 are not limited to the configuration shown in FIG. 15, and various modifications such as omitting some of the components or adding other components are possible.

  As shown in FIG. 15, the differential section 64 of the operational amplifier OPC1 includes a current mirror circuit configured by transistors TC1 and TC2. Further, an input signal VS2 is input to the gate of one transistor TC3, and the outputs (NA3) of the first and second differential units 66 and 68 are connected to the gate of the other transistor TC4. Differential pair transistors TC3 and TC4 including. Further, a current mirror circuit (TC1, TC2) and a current source transistor TC5 for supplying a bias current flowing through the differential pair transistors TC3, TC4 are included.

  In FIG. 15, TC1 and TC2 are P-type transistors, and TC3, TC4, and TC5 are N-type transistors. A bias voltage BC1 is input to the gate of the transistor TC5.

  The first differential section 66 of the operational amplifier OPC2 includes a first current mirror circuit configured by P-type transistors TC6 and TC7. The output (NA4) of the differential unit 64 is connected to the gate of one N-type transistor TC8, and the outputs (NA3) of the first and second differential units 66 and 68 are connected to the gate of the other N-type transistor TC9. The first differential pair transistors TC8 and TC9 are connected. The first current mirror circuit (TC6, TC7) and the first differential pair transistors TC8, TC9 are supplied with a bias current flowing through the first current mirror circuit (TC6, TC7), and includes a first current source transistor TC10 configured by an N-type transistor.

  The second differential section 68 of the operational amplifier OPC2 includes a second current mirror circuit configured by N-type transistors TC11 and TC12. The output (NA4) of the differential section 64 is connected to the gate of one P-type transistor TC14, and the outputs (NA3) of the first and second differential sections 66 and 68 are connected to the gate of the other P-type transistor TC13. It includes a second differential pair transistor TC13, TC14 connected. Further, a bias current flowing through the second current mirror circuit (TC11, TC12) and the second differential pair transistors TC13, TC14 is supplied, and a second current source transistor TC15 configured by a P-type transistor is included.

  According to FIG. 15, a rail-to-rail operational amplifier can be configured by the differential units 66 and 68.

  That is, the signal VS4 output to the node NA4 has its small signal amplification operating point (amplification center) set to 0.8 to 1.0 V, for example. Therefore, if only the differential unit 66 is provided in the operational amplifier OPC2, the N-type transistor TC8 of the differential unit 66 is turned off in the voltage range below the operating point, and a dead zone region is formed below the power supply voltage range. There is a risk that.

  In this regard, in FIG. 15, a differential unit 68 is provided in addition to the differential unit 66. Therefore, even if the voltage at the node NA4 is lowered, the P-type transistor TC14 of the differential unit 68 is turned on, and thus the signal VS4 can be amplified using the differential unit 68. Therefore, it is possible to prevent the dead zone from being formed below the power supply voltage range.

  On the other hand, if only the differential unit 68 is provided in the operational amplifier OPC2, the P-type transistor TC14 of the differential unit 68 is turned off in the voltage range above the operating point, and a dead zone region is formed above the power supply voltage range. There is a risk that.

  In this regard, in FIG. 15, a differential unit 66 is provided in addition to the differential unit 68. Therefore, even if the voltage at the node NA4 is increased, the N-type transistor TC8 of the differential unit 66 is turned on, so that the signal VS4 can be amplified using the differential unit 66. Therefore, it is possible to prevent the dead zone from being formed above the power supply voltage range.

  As described above, according to the configuration of FIG. 15, it is possible to prevent the formation of the dead zone at the lower side and the upper side of the power supply voltage range, thereby realizing a rail-to-rail operational amplifier.

  For example, if a rail-to-rail type operational amplifier is not used as the operational amplifier OPC2, an unbalance occurs in the feedback of the signal from the output of the operational amplifier OPC1 to the inverting input terminal of the OPC1, and the center level of the signal VS4 amplified by the operational amplifier OPC1 is The phenomenon of shifting occurs. In particular, when a plurality of amplifier circuits are connected in cascade, this shift amount further increases.

  In this regard, if a rail-to-rail type operational amplifier is used as the operational amplifier OPC2, it is possible to amplify the upper side and the lower side with good balance centering on the operating point. Therefore, the unbalance of the feedback of the signal from the output of the operational amplifier OPC1 to the inverting input terminal of the OPC1 can be reduced, and the phenomenon that the center level of the amplified signal VS4 is shifted can be prevented. As a result, it is possible to prevent a situation in which the center level of the output signal to the subsequent circuit (for example, a demodulator circuit described later) shifts and processing of the subsequent circuit becomes difficult.

  As described above, the bias current IB2 flowing through the differential units 66 and 68 is reduced as much as possible. Specifically, W / L (gate width / gate length) of the current source transistor TC10 is made as small as possible (for example, W / L = 1/10 to 1/30). Further, the W / L of the transistor TC15 is reduced, and the W / L of the N-type transistor that generates the bias voltage BC3 of the transistor TC15 is reduced as much as possible. As a result, the bias current IB2 is reduced to, for example, several nA.

  Therefore, even if a through current flows through a path from VDD to VSS via the transistors TC7 and TC11, or a path from VDD to the transistors TC15, TC13, TC9, and TC10 through VSS, the through current is, for example, several nA. The degree is very small. Therefore, even if the outputs of the differential units 66 and 68 are short-connected as shown in FIG. By short-circuiting the outputs of the differential units 66 and 68, it is not necessary to provide an output unit or the like in the operational amplifier OPC2, so that power consumption can be reduced and the circuit scale can be reduced.

  Note that a general rail-to-rail operational amplifier as shown in FIG. 16 may be employed as the operational amplifier OPC2. According to the operational amplifier of FIG. 16, the output of the differential unit is not short-circuited so that a through current can be prevented. However, an output unit composed of transistors TG15 and TG16, transistors TG11, TG12, TG13, TG14, and the like are required. Therefore, the current consumption increases and the circuit scale increases. In this regard, according to the configuration of FIG. 15, the power consumption can be reduced and the circuit scale can be reduced as compared with FIG.

4). Offset Voltage In this embodiment, as shown in FIG. 17, when the offset voltage of the operational amplifier OPC1 is VOF1 and the offset voltage of the operational amplifier OPC2 is VOF2, VOF1> VOF2 is set. Specifically, the gate length of the differential pair transistors TC3 and TC4 constituting the operational amplifier OPC1 is L1, the gate width is W1, the gate length of the differential pair transistors TC8 and TC9 constituting the operational amplifier OPC2 is L2, and the gate width is W2. In this case, L1 × W1 <L2 × W2 is set.

  For example, by providing a plurality of amplifier circuits in FIG. 1 and cascading them, a high amplification factor can be obtained. In this case, if the offset voltage of each amplifier circuit is large, the operating point shifts, and there is a possibility that an appropriate amplification operation cannot be realized.

  In this case, for example, a method of eliminating the influence of the offset voltage by providing a capacitor for DC cut between the first stage amplifier circuit and the second stage amplifier circuit may be considered. However, according to this method, in order to charge and discharge the DC cut capacitor, it is necessary to increase the current supply capability of the operational amplifier OPC1, and the power consumption increases.

  Therefore, in order to achieve both prevention of operating point shift and low power consumption, the offset voltage is reduced by increasing L × W = L2 × W2 of the differential pair transistor of the operational amplifier OPC2 (OPC4), It is desirable to directly connect a plurality of amplifier circuits without using a DC cut capacitor.

  However, in the present embodiment, as described above, a high-speed operational amplifier is used as the operational amplifier OPC1 and a low-speed operational amplifier is used as the operational amplifier OPC2 in order to reduce power consumption. Therefore, if L × W = L1 × W1 of the differential pair transistor TC4 of the operational amplifier OPC1 is increased in order to reduce the offset voltage, the drain capacity of the TC4 also increases, which hinders the speeding up of the operational amplifier OPC1.

  On the other hand, for the operational amplifier OPC2, even if L × W = L2 × W2 of the differential pair transistors TC8 and TC9 is increased in order to reduce the offset voltage, it is sufficient that the operational amplifier OPC2 originally operates at a low speed. There is no problem.

  Therefore, in this embodiment, L2 × W2 of the differential pair transistors TC8 and TC9 of the operational amplifier OPC2 is increased, and the offset voltage VOF2 is decreased. On the other hand, L1 × W1 of the differential pair transistor TC4 of the operational amplifier OPC1 is made smaller than L2 × W2, and the offset voltage is set to VOF1> VOF2. As a result, it is possible to achieve both prevention of operating point shift and low power consumption.

5). Control Circuit FIG. 18 shows a detailed configuration example of the control circuit 70 of the present embodiment. Note that the control circuit 70 of the present embodiment is not limited to the configuration of FIG. 18, and various modifications such as omitting some of the components or adding other components are possible.

  The control circuit 70 is provided between a charging capacitor CD1 provided between the charging node NC and VSS (first power supply), and between the charging node NC and VDD (second power supply in a broad sense). A charging transistor TD1 is included. A comparison circuit 72 (charge control circuit) included in the control circuit 70 performs comparison processing between the output signal OUT of the amplifier circuit 61 and the reference voltage VREF, and controls charging of the charging capacitor CD1 by the charging transistor TD1 based on the comparison result. To do. As a result, the voltage at the charging node NC is output to the cutoff frequency control circuit 100 as the control signal VC.

  The control circuit 70 includes a discharging transistor TD2 that is provided between the charging node NC and VSS (first power supply) and flows a constant current to the VSS side. The discharging transistor TD2 is, for example, a transistor having a lower current supply capability than the charging transistor TD1. For example, the W / L (gate width / gate length) of the discharge transistor TD2 is smaller than the W / L of TD1.

  More specifically, the discharge period set by the constant current flowing through the discharge transistor TD2 and the capacitance of the charging capacitor CD1 is the logic level 1 (first logic level in a broad sense) of the received signal that is ASK modulated. It is longer than the transfer period T1. That is, the bias voltage BD1 is input to the gate of the discharging transistor TD2, and thereby a constant current flows. The discharge period by the discharge transistor TD2 is set by the magnitude of this constant current and the capacitance of the charging capacitor CD1. The constant current flowing through the discharge transistor TD2 is set such that the discharge period is sufficiently longer than the transfer period T1 of the logic level 1 (for example, a period of 10 times or more of T1). Specifically, the magnitude of the bias voltage BD1 and the W / L of the discharging transistor TD2 are set.

  That is, since the amplitude of the reception signal IN decreases as the distance between the in-vehicle device and the portable device increases, the circuit constant of the reception circuit is set so that the reception circuit of this embodiment can detect even a reception signal with a small amplitude. Is set. Therefore, the noise signal is also detected as a received signal, which may increase the voltage of the control signal VC. Then, the potential of the control signal VC rises due to the noise signal, and the gain of the amplifier circuit 61 is set to a small value before the original received signal is input. Then, there is a possibility that the gain will not return from there, and proper gain control cannot be realized.

  In this regard, in FIG. 18, a small constant current always flows to the VSS side by the discharging transistor TD2. Therefore, even if the potential of the control signal VC increases due to the noise signal, the potential is returned to the VSS side by the discharging transistor TD2. As a result, it is possible to prevent a situation in which the potential of the control signal VC increases due to the noise signal and the gain of the amplifier circuit 61 is set to a small value before the original received signal is input.

  At this time, the discharge period by the discharge transistor TD2 is set to be sufficiently longer than the transfer period T1 of the logic level 1, which is the longer transfer period. Therefore, in the original data transfer period, the discharge by the discharge transistor TD2 can be almost ignored and proper data transfer can be realized.

  In FIG. 18, a wake-up transistor TD3 is also provided. This N-type transistor TD3 has a control signal VC input to its gate, a source connected to VSS, and a wakeup signal WAKE output to its drain. Accordingly, when the potential of the control signal VC rises and becomes larger than, for example, the threshold voltage of the transistor TD3, the wakeup signal WAKE becomes active (changes from H level to L level). As a result, the burst signal in the burst period TB is detected and notified to the receiving circuit and other circuits of the integrated circuit device including the receiving circuit that the wake-up should be performed.

  Further, in FIG. 18, a reset transistor TD9 is also provided. This N-type transistor TD9 has a reset signal input to its gate and a source connected to VSS. When the reset signal becomes H level (active), the charging node NC is reset to the VSS level.

6). Reception Circuit FIG. 19 shows a configuration example of a reception circuit including the automatic gain control circuit of this embodiment. The receiving circuit of the present embodiment is not limited to the configuration shown in FIG. 19, and various modifications such as omitting some of the components or adding other components are possible.

  The receiving circuit of FIG. 19 includes a high-pass filter 40, a DC level shifter 50, an automatic gain control circuit 200, a reference voltage generation circuit 80, and a demodulation circuit 90.

  A reception signal AIN from the antenna unit 10 configured by a coil (LC resonance circuit) or the like is input to the high pass filter 40.

  The high-pass filter 40 is provided between the capacitor CA1 provided between the input node NA0 of the reception signal AIN and the output node NA1 of the high-pass filter 40, and between the output node NA1 and VSS (first power supply in a broad sense). And includes an N-type transistor TA1 to which a constant bias voltage VH is input. That is, the high-pass filter 40 is configured by the capacitance of the capacitor CA1 and the on-resistance of the transistor TA1.

  Taking the smart entry system as an example, an ASK (Amplitude Shift Keying) modulated reception signal AIN of LF (Low Frequency) band that changes the amplitude of the carrier wave corresponding to the input digital signal is input to the high-pass filter 40. . The high-pass filter 40 passes the received signal AIN in the LF band of 120 to 140 KHz, for example, subjected to ASK modulation (amplitude modulation), and attenuates a signal having a frequency lower than that.

  The DC level shifter 50 performs a DC level shift of the signal VS1 that has passed through the high-pass filter 40, and outputs an input signal IN after the DC level shift. That is, the DC level shifter 50 performs level shift conversion so that the DC level of the input signal IN is set at the small signal amplification operating point (amplification center) of the amplifier circuit 61. This DC level shifter 50 is provided between VSS (first power supply) and its output node NA2, and has an N-type transistor TB1 to which the signal VS1 from the high-pass filter 40 is input at its gate and VDD (in a broad sense). Includes a current source ISH provided between the second power supply) and its output node NA2. Here, the current source ISH may be constituted by a P-type transistor whose gate is supplied with a constant bias voltage, or may be constituted by a resistor or the like that functions as a current source.

  The amplifier circuits 61 and 62 amplify the signal IN after the DC level shift and output an output signal OUT. Each of the amplifier circuits 61 and 62 has the frequency characteristics of the bandpass filter described in FIG. Specifically, it has a band-pass filter characteristic having a center frequency in the frequency band (for example, 120 to 140 KHz) of the carrier wave (desired signal) of the received signal IN. This amplifier circuit is not limited to two cascade-connected amplifier circuits as shown in FIG. 19, but only one amplifier circuit or three or more amplifier circuits may be cascade-connected. .

  The control circuit 70 compares the output signal OUT of the amplifier circuits 61 and 62 with the reference voltage VREF and outputs a control signal VC.

  As described above, the cutoff frequency control circuit 100 controls the cutoff frequencies of the operational amplifiers OPC1 and OPC2 based on the control signal VC, thereby setting the gains at the desired frequencies of the amplifier circuits 61 and 62 to appropriate values. be able to. By performing such automatic gain adjustment, an output signal OUT having a constant amplitude is input to the demodulation circuit 90, and the demodulation processing in the demodulation circuit 90 is facilitated.

  The reference voltage generation circuit 80 generates and outputs a reference voltage VREF.

  The demodulation circuit 90 performs a demodulation process based on the output signal OUT from the amplification circuits 61 and 62. That is, demodulation processing is performed in order to obtain an input digital signal from the ASK modulated signal.

  FIG. 20 shows a signal waveform example for explaining the operation of the receiving circuit. As indicated by G1 in FIG. 20, the receiving circuit receives a burst signal having a given number of pulses from the in-vehicle device as the reception signal AIN in the burst period TB. The burst period TB corresponds to a preamble period, and a burst signal not subjected to ASK modulation is received in the burst period TB. Automatic gain adjustment of the reception signal AIN is performed within the burst period TB.

  As indicated by G2 in FIG. 20, in the transfer periods T0 and T1 following the burst period TB, ASK-modulated signals corresponding to the logical levels 0 and 1 of the digital signal are transmitted. The lengths of the periods T0 and T1 are different (for example, T0 <T1), and by detecting the length of this period, it is detected which digital signal of logic level 0 or 1 is transmitted from the in-vehicle device. it can. Although T0 <T1 in FIG. 20, T0> T1 may be used.

  In G3 of FIG. 20, the reception signal AIN is a signal centered on 0V. As indicated by G4, the DC level shifter 50 shifts the DC level of the reception signal AIN to the voltage level (VM) at the operating point (amplification center) of the small signal amplification of the amplifier circuits 61 and 62. Then, as indicated by G5, the amplifier circuits 61 and 62 amplify the signal IN after the DC level shift, and output the amplified signal OUT.

  When the amplitude of the output signal OUT is larger than the reference voltage VREF from the reference voltage generation circuit 80, the potential of the control signal VC increases as indicated by G6 in FIG. Then, the cutoff frequency control circuit 100 changes the bias voltages VB1 and VB2 to adjust the gains of the amplifier circuits 61 and 62 to appropriate values.

  When the automatic gain adjustment is performed in this way, the amplitude of the output signal OUT becomes substantially constant within the burst period TB as indicated by G7 in FIG. Since the amplitude of the output signal OUT becomes constant as described above, the demodulation circuit 90 can stably demodulate the ASK-modulated signal in the periods T0 and T1 after the burst period TB.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, in the specification or drawings, terms (VSS, VDD, logic level 1, etc.) described at least once together with different terms (first power supply, second power supply, first logic level, etc.) having a broader meaning or the same meaning ) May be replaced by the different terms anywhere in the specification or drawings. Further, the configurations and operations of the amplifier circuit and the receiver circuit are not limited to those described in this embodiment, and various modifications can be made.

2 is a configuration example of an automatic gain control circuit of the present embodiment. Explanatory drawing of the band pass filter characteristic of an amplifier circuit. Explanatory drawing of the 1st method of gain control. Explanatory drawing of the 2nd method of gain control. Explanatory drawing of the 3rd method of gain control. Explanatory drawing of the 4th method of gain control. 1 is a first configuration example of a cutoff frequency control circuit. The 2nd structural example of a cutoff frequency control circuit. The 3rd structural example of a cutoff frequency control circuit. The 4th structural example of a cutoff frequency control circuit. A modification of the cut-off frequency control circuit. A basic configuration example of an amplifier circuit. Explanatory drawing of the frequency characteristic of operational amplifier. 3 shows a detailed configuration example of an amplifier circuit. The detailed example of a structure of an amplifier circuit. Another configuration example of a rail-to-rail operational amplifier. Explanatory drawing of the setting method of offset voltage. 3 shows a detailed configuration example of a control circuit. 2 is a configuration example of a receiving circuit including an automatic gain control circuit of the present embodiment. 7 is a signal waveform example for explaining the operation of the receiving circuit.

Explanation of symbols

OPC1 first operational amplifier, OPC2 second operational amplifier,
CC1, CC2 capacitors,
40 high-pass filter, 50 DC level shifter, 61, 62 amplifier circuit,
63 gain setting unit, 64 differential unit, 66 first differential unit, 68 second differential unit,
70 control circuit, 72 comparison circuit, 80 reference voltage generation circuit, 90 demodulation circuit,
100 cut-off frequency control circuit, 101 first bias voltage generation circuit,
102 second bias voltage generation circuit, 103 reference current generation circuit,
200 Automatic gain control circuit

Claims (18)

An amplifying circuit having a frequency characteristic of a band-pass filter, receiving an input signal, amplifying the input signal and outputting an output signal;
A control circuit that outputs a control signal for controlling the gain of the amplifier circuit based on the output signal;
Including a cutoff frequency control circuit,
The amplifier circuit is
A first operational amplifier in which the input signal is input to the first input terminal;
The output of the first operational amplifier is input to the first input terminal, and the output is input to the second input terminal and the second input terminal of the first operational amplifier. Including an operational amplifier,
The cutoff frequency control circuit is
An automatic gain control circuit that controls a cutoff frequency of at least one of the first operational amplifier and the second operational amplifier based on the control signal from the control circuit. In claim 1,
The cutoff frequency control circuit is
An automatic gain control circuit, wherein a gain at a desired frequency of the amplifier circuit is lowered by performing a control to lower a cutoff frequency of the first operational amplifier based on the control signal. In claim 1,
The cutoff frequency control circuit is
An automatic gain control circuit characterized in that, based on the control signal, a gain at a desired frequency of the amplifier circuit is lowered by performing control to increase a cutoff frequency of the second operational amplifier. In claim 1,
The cutoff frequency control circuit is
Based on the control signal, control is performed to lower the cutoff frequency of the first operational amplifier, and control is performed to increase the cutoff frequency of the second operational amplifier, thereby increasing the gain at the desired frequency of the amplifier circuit. Automatic gain control circuit characterized by lowering. In claim 1,
The cutoff frequency control circuit is
Based on the control signal, the gain at the desired frequency of the amplifier circuit is lowered by performing control to lower both the cutoff frequency of the first operational amplifier and the cutoff frequency of the second operational amplifier. Automatic gain control circuit. In claim 2,
The cutoff frequency control circuit is
A reference current generation circuit;
A first bias voltage generation circuit;
A second bias voltage generation circuit,
The first bias voltage generation circuit includes:
A first bias voltage having a voltage value corresponding to a current value obtained by subtracting a current generated based on the control signal from a reference current generated by the reference current generating circuit is generated in the first operational amplifier. Supply
The second bias voltage generation circuit includes:
2. An automatic gain control circuit, wherein a second bias voltage having a constant voltage value corresponding to the current value of the reference current is generated and supplied to the second operational amplifier. In claim 3,
The cutoff frequency control circuit is
A reference current generation circuit;
A first bias voltage generation circuit;
A second bias voltage generation circuit,
The first bias voltage generation circuit includes:
Generating a first bias voltage having a constant voltage value corresponding to the current value of the reference current generated by the reference current generating circuit, and supplying the first bias voltage to the first operational amplifier;
The second bias voltage generation circuit includes:
A second bias voltage having a voltage value corresponding to a current value obtained by adding the current generated based on the control signal to the reference current is generated and supplied to the second operational amplifier. Gain control circuit. In claim 4,
The cutoff frequency control circuit is
A reference current generation circuit;
A first bias voltage generation circuit;
A second bias voltage generation circuit,
The first bias voltage generation circuit includes:
A first bias voltage having a voltage value corresponding to a current value obtained by subtracting a current generated based on the control signal from a reference current generated by the reference current generating circuit is generated in the first operational amplifier. Supply
The second bias voltage generation circuit includes:
A second bias voltage having a voltage value corresponding to a current value obtained by adding the current generated based on the control signal to the reference current is generated and supplied to the second operational amplifier. Gain control circuit. In claim 5,
The cutoff frequency control circuit is
A reference current generation circuit;
A first bias voltage generation circuit,
The first bias voltage generation circuit includes:
A bias voltage having a voltage value corresponding to a current value obtained by subtracting a current generated based on the control signal from a reference current generated by the reference current generating circuit is generated, and the first operational amplifier and the second operational amplifier are generated. An automatic gain control circuit characterized by being supplied to an operational amplifier. In any one of Claims 1 thru | or 9,
When the first bias current flowing through the first operational amplifier is IB1 and the second bias current flowing through the second operational amplifier is IB2, by setting IB1> IB2, the amplifier circuit has the band An automatic gain control circuit characterized by having a frequency characteristic of a pass filter. In claim 10,
The cut-off frequency on the low frequency side of the bandpass filter is
Set by the output impedance of the second operational amplifier and the load capacitance of the output node of the second operational amplifier;
The automatic gain control circuit, wherein a cut-off frequency on the high frequency side of the band-pass filter is set by an output impedance of the first operational amplifier and a load capacitance of an output node of the first operational amplifier. In claim 10 or 11,
The amplifier circuit includes a gain setting unit for setting the gain of the amplifier circuit,
The gain setting unit
A first capacitor provided between an output of the first operational amplifier and the second input terminal of the first operational amplifier;
An automatic gain control circuit comprising a second capacitor provided between the output of the second operational amplifier and a low potential side power supply node. In any of claims 10 to 12,
2. An automatic gain control circuit, wherein VOF1> VOF2 is set when the offset voltage of the first operational amplifier is VOF1 and the offset voltage of the second operational amplifier is VOF2. In claim 13,
When the gate length of the differential pair transistor constituting the first operational amplifier is L1, the gate width is W1, the gate length of the differential pair transistor constituting the second operational amplifier is L2, and the gate width is W2. , L1 × W1 <L2 × W2 is set. In any of claims 10 to 14,
2. An automatic gain control circuit, wherein the second operational amplifier is a rail-to-rail operational amplifier. In any one of Claims 1 thru | or 15,
The first operational amplifier includes a differential unit,
The second operational amplifier includes first and second differential units,
The output of the differential section of the first operational amplifier is connected to first input terminals of the first and second differential sections of the second operational amplifier,
The output of the first differential unit and the output of the second differential unit are connected in common, and the output of the first and second differential units is the same as that of the first and second differential units. An automatic gain control circuit connected to the second input terminal. In claim 16,
The differential section of the first operational amplifier is:
A current mirror circuit;
A differential pair transistor in which the input signal is input to the gate of one transistor and the outputs of the first and second differential units are connected to the gate of the other transistor;
A current source transistor that supplies a bias current flowing through the current mirror circuit and the differential pair transistor;
The first differential section of the second operational amplifier is:
A first current mirror circuit composed of P-type transistors;
A first differential pair transistor in which the output of the differential unit is connected to the gate of one N-type transistor, and the output of the first and second differential units is connected to the gate of the other N-type transistor; ,
Including a first current source transistor configured to supply a bias current flowing through the first current mirror circuit and the first differential pair transistor and configured by an N-type transistor;
The second differential section of the second operational amplifier is:
A second current mirror circuit composed of N-type transistors;
A second differential pair transistor in which the output of the differential section is connected to the gate of one P-type transistor and the output of the first and second differential sections is connected to the gate of the other P-type transistor; ,
2. An automatic gain control circuit comprising: a second current source transistor configured to supply a bias current flowing through the second current mirror circuit and the second differential pair transistor and configured by a P-type transistor. An automatic gain control circuit according to any one of claims 1 to 17,
A high-pass filter that receives the received signal;
And a DC level shifter for performing a DC level shift of the output signal of the high pass filter.

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