JP4417745B2 - Inspection device for solid-state image sensor - Google Patents

Description

  The present invention relates to an inspection apparatus for inspecting characteristics of an image sensor such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS).

In the manufacturing process of an image sensor such as a CCD or CMOS, it is necessary to irradiate the image sensor with light of various conditions and to inspect its photoelectric conversion characteristics.
An image sensor such as a CCD or CMOS has a large number of light receiving elements arranged in a matrix. In order to inspect whether the characteristics of these light receiving elements have characteristics within the required ranges, it is necessary to operate the imaging element by supplying necessary signals to the imaging element while irradiating the imaging element with light. .
In order to operate the image sensor, a timing signal of about 20 channels is required. Conventionally, a timing generator that generates a timing signal, for example, designs a dedicated LSI and supplies a necessary signal from the LSI to an imaging device.

By the way, a dedicated LSI used for operating the image sensor is very expensive and lacks versatility, and is necessary for each specification of the image sensor.
On the other hand, as another method for generating a timing signal, for example, a necessary timing signal is generated using a programmable circuit, and this is written in a high-speed memory such as an SRAM (Static Random Access Memory), and a predetermined clock is generated. It is also conceivable to provide the image sensor in synchronization.
However, writing all the timing signals for operating the image sensor requires a very large capacity SRAM, which is disadvantageous in that it is costly.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a solid-state image sensor inspection apparatus that can be easily applied to solid-state image sensors of various specifications with reduced costs. It is in.

  An inspection apparatus for a solid-state image sensor according to the present invention is an inspection apparatus for a solid-state image sensor that inspects photoelectric conversion characteristics of each pixel of the solid-state image sensor, and includes a timing generator that generates a timing signal for driving the solid-state image sensor. The timing generator generates a memory circuit that stores the first signal of the timing signals and a second signal of the timing signals that changes less frequently than the first signal. A clock signal having a predetermined frequency is commonly supplied to the signal generation circuit, the memory circuit, and the signal generation circuit, and the first signal and the second signal are respectively output from the memory circuit and the signal generation circuit according to the clock signal. A clock circuit for outputting a signal to the solid-state imaging device.

  Preferably, the second signal is photoelectrically converted by each photodiode arranged on the matrix of the solid-state imaging device, and is supplied to a vertical register for transferring the accumulated charge in the vertical direction of the imaging surface. The first signal is supplied to a horizontal register that transfers the charge transferred by the vertical register to the output unit of the solid-state imaging device.

  More preferably, the inspection apparatus for a solid-state image pickup device according to the present invention is configured such that the timing generator, a connection unit that performs electrical connection with the solid-state image pickup device, and a signal between the solid-state image pickup device through the connection unit. The motherboard further includes a signal processing circuit for transmitting and receiving, and the timing generator is detachable from the motherboard.

In the present invention, the timing generator generates a timing signal for driving the solid-state imaging device, and among the signals constituting the timing signal, the first signal is stored in the memory circuit, and the second signal is transmitted by the signal generation circuit. Generate. That is, in the present invention, among the timing signals of the timing generator, a high-speed first signal having a high change frequency is stored in the memory circuit, and a low-speed second signal having a low change frequency is a programmable signal. Generate by the generation circuit. Then, by supplying a common clock signal to the memory circuit and the signal generation circuit, the first and second signals are output to the solid-state imaging device.
In the present invention, the first signal of the high-speed system having a high change frequency and the second signal of the low-speed system having a low change frequency constituting the timing signal are separated, and only the first signal of the high-speed system is stored in the memory. Since the data is stored in the circuit, the memory circuit is effectively used and the memory capacity can be reduced.
In the present invention, since the timing generator is detachable from the motherboard, the programming of the signal generator circuit of the timing generator can be changed according to the specifications of the solid-state imaging device, and the storage contents of the memory circuit can be changed. It can be easily handled.

  According to the present invention, the cost of a solid-state image sensor inspection apparatus can be reduced, and the solid-state image sensor of various specifications can be easily applied.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of an inspection apparatus for a solid-state imaging device to which the present invention is applied.
An inspection system 1 shown in FIG. 1 inspects a photoelectric conversion characteristic of a CCD (charge coupled device) image sensor 50 (hereinafter referred to as a CCD 50).
The inspection system 1 includes a handler 2, a motherboard 10, a light source device 30, a handler controller 45, a board controller 46, a light source controller 47, processing devices 40A to 40D, and the like.

Here, FIG. 2 is a diagram showing a configuration of the motherboard 10.
The motherboard 10 is made of a printed wiring board. A circular opening 10 </ b> A is formed at the center of the motherboard 10. This opening 10 </ b> A is for allowing the light irradiated to the CCD 50 to pass therethrough.
On the motherboard 10, a timing generator 13, a socket 15, and a signal processing circuit 17 are mounted.
The timing generator 13 is an embodiment of the timing generator of the present invention, the socket 15 is an embodiment of the connecting means of the present invention, and the signal processing circuit 17 is an embodiment of the signal processing circuit of the present invention.

The socket 15 is electrically connected to the motherboard 10 via a plurality of connectors 17.
The socket 15 includes mounting portions 16 for mounting the CCD 50 at a plurality of locations (four locations). The mounting portion 16 includes an opening 16a. Light from a light source device 30 (to be described later) is applied to the imaging surface of the CCD 50 mounted on the mounting unit 16 through the opening 16a. The CCD 50 is mounted so that the imaging surface faces the mother board 10 side.
When the CCD 50 is mounted on the mounting unit 16, the CCD 50 is electrically connected to each circuit mounted on the mother board 10.

The timing generator 12 generates a timing signal for driving the CCD 50, as will be described later.
The timing generator 12 is provided corresponding to the four CCDs 50 and is electrically connected to the mother board 10 via the connector 13. The timing generator 12 is detachable from the motherboard 10.

  The signal processing circuit 17 is provided corresponding to the four CCDs 50 and exchanges various signals with the solid-state imaging device 50 mounted on the mounting unit 16. The signal processing circuit 17 outputs the imaging signal obtained from the CCD 50 to the processing devices 40A to 40D as a digital signal.

In FIG. 1, the mother board 10 is mounted on the support part 3 of the handler 2.
The handler 2 mounts the CCD 50 to be inspected on each mounting portion 16 of the socket 15 on the mother board 10, and moves the CCD 50 that has been inspected from the socket 15. Since the handler 2 is a well-known technique, detailed description thereof is omitted.

  The light source device 30 is provided below the support portion 3 of the handler 2. The light source device 30 irradiates the CCD 50 with light through the opening 3 </ b> A formed in the support portion 3, the opening 10 </ b> A of the motherboard 10, and the opening portion 16 a of the mounting portion 16 of the socket 15. The light source device 30 includes an optical system that converts light output from a light source such as a halogen lamp into light having conditions necessary for the inspection of the CCD 50.

The handler controller 45 controls the operation of the handler 2. The handler controller 45 is constituted by a personal computer, for example.
The board controller 46 exchanges signals with, for example, a circuit such as the timing generator 12 on the mother board 10 and controls them. The board controller 46 is constituted by a personal computer, for example.
The light source controller 47 controls the operation of the light source device 30. The light source controller 47 is constituted by a personal computer, for example.

  The processing devices 40 </ b> A to 40 </ b> D are electrically connected to the motherboard 10, and input image signals captured by the CCDs 50 mounted on the socket 15. The processing devices 40A to 40D inspect the photoelectric conversion characteristics and the like of each pixel of the CCD 50 based on each input image signal, and display the inspection result. The processing devices 40A to 40D are configured by, for example, a personal computer.

Here, before describing the configuration of the timing generator, the structure and operation of the CCD 50 to be inspected will be described.
FIG. 3 is a schematic configuration diagram of the CCD 50.
The CCD 50 includes pixels PX arranged in a matrix, and the pixel PX includes a photodiode PD and a vertical register VR.

The CCD 50 basically performs photoelectric conversion and charge accumulation in the photodiode PD of each pixel PX, and transfers the accumulated charge to the output unit OUT.
Charge transfer is performed by the vertical register VR and the horizontal register HR. The signal from the timing generator 12 is used for transferring charges by the vertical register VR and the horizontal register HR. Signals output from the timing generator 12 include vertical drive signals V1 to V4 and horizontal drive signals H1 and H2.

The vertical transfer is generally performed by giving a four-phase clock pulse, and the horizontal transfer is given by giving a two-phase clock pulse. By adding a clock pulse to the terminal at a determined timing, electric charges are carried to the output unit in a bucket relay manner.
Specifically, the charge is carried to the output unit OUT by the following procedure.
For example, in the case of a CCD 50 having 640 (vertical) × 480 (horizontal) pixels, (1) the photodiode PD of 640 × 480 pixels PX receives light and performs photoelectric conversion and charge accumulation operation for a certain period. (2) At the read timing, 640 × 480 charges are simultaneously transferred to the adjacent vertical register VR. (During this time, the operation of the horizontal register HR is stopped). This is “vertical transfer”. (3) 480 charges are transferred to the horizontal register HR at the timing of the vertical drive signals V1 to V4. This is “horizontal transfer”. (4) While the next 480 charges are transferred to the horizontal register HR, the 480 charges already transferred to the horizontal register HR are transferred to the output unit OUT one by one.
By repeating the above (3) and (4) 640 times, an image of one frame is obtained. While this is repeated 640 times, the next 640 × 480 charges are accumulated in the photodiode PD.
Since these operations must all be synchronized in timing, they are performed in synchronization with a clock signal having a predetermined period.

FIG. 4 shows an example of the vertical drive signals V1 to V4 and the horizontal drive signals H1 and H2.
Note that the vertical drive signals V1 to V4 and the horizontal drive signals H1 and H2 shown in FIG. 4 are a part of signals for driving the CCD 50, and actually a signal of about 20 ch is required.
FIG. 4A shows an example of a signal waveform during vertical transfer, and FIG. 4B shows an example of a signal waveform during horizontal transfer.

Each signal shown in FIG. 4 is synchronized with a clock signal CLK having a predetermined cycle.
When the vertical drive signals V1 to V4 shown in FIG. 4A are compared with the horizontal drive signals H1 and H2 shown in FIG. 4B, the horizontal drive signals H1 and H2 change at a relatively high frequency and have a high frequency. Although it is a signal (high-speed signal), it can be seen that the vertical drive signals V1 to V4 change at a relatively high frequency and are low-frequency signals (low-speed signals). This requires a low-speed signal because a large amount of charge is handled in the vertical direction and takes a long time to transfer. In the horizontal direction, a high-speed signal is required because a small amount of charge is handled and high-speed operation is required. It has become. In general, in order to operate the CCD 50, about 20 channels of timing signals are necessary. Of these, high-speed signals are about several channels, and low-speed signals are overwhelmingly large. On the other hand, all signals are generated in synchronization with the clock, but high-speed signals change at a relatively high frequency, and low-speed signals change at a relatively low frequency.
For this reason, in the present embodiment, the timing generator 12 writes a high-speed signal to a high-speed memory such as an SRAM (Static Random Access Memory) and gives it to the CCD 50 in synchronization with a predetermined clock. On the other hand, the low-speed signal is generated using, for example, an FPGA (Field Programmable Gate Array).

The configuration of the timing generator 12 will be described with reference to FIG.
As shown in FIG. 5, the timing generator 12 includes a clock circuit 20, a low-speed signal generation circuit 24, a control circuit 25, and a memory circuit 22.
The low-speed signal generation circuit 24 is an embodiment of the signal generation circuit of the present invention, the memory circuit 22 is an embodiment of the memory circuit of the present invention, and the clock circuit 20 is an embodiment of the clock circuit of the present invention.

  The clock circuit 20 generates a clock signal CLK having a predetermined frequency based on a constant frequency signal supplied from the crystal oscillator 21 and supplies the clock signal CLK to the low-speed signal generation circuit 24 and the memory circuit 22.

  For the memory circuit 22, for example, a memory device capable of reading data at high speed such as SRAM is used. In the memory circuit 22, the horizontal drive signals H1 and H2 shown in FIG. 4B, that is, high-speed signals are written. Therefore, when the clock signal CLK is supplied to the memory circuit 22, the horizontal drive signals H1 and H2 are output to the control circuit 25 in synchronization with the clock signal CLK.

The low-speed signal generation circuit 24 and the control circuit 25 are configured by the FPGA 23. As will be described later, the FPGA 23 is programmed to configure a desired counter circuit and logic circuit. Since FPGA is a well-known technique, detailed description is omitted.
The low speed signal generation circuit 24 generates low speed signals such as the vertical drive signals V1 to V4 shown in FIG. 4A in synchronization with the clock signal CLK, and outputs the low speed signals to the CCD 50.

The control circuit 25 first reads data for generating a timing signal from the board controller 46 in synchronization with the clock CLK, and writes it into the memory circuit 22.
The control circuit 25 reads out data from a desired address of the memory circuit 22 in synchronization with the clock CLK and outputs the data to the CCD 50 in a state where the above data is written in the memory circuit 22. Further, the control circuit 25 exchanges data with the board controller 46.

FIG. 6 shows an example of the configuration of the low-speed signal generation circuit 24 formed in the FPGA 23.
The low-speed signal generation circuit 24 includes a plurality of frequency dividing circuits 27A to 27C, a plurality of exclusive OR circuits (EXOR circuits) 27D and 27E, and the like.
A clock signal CLK is input to each of the frequency dividing circuits 27A to 27C.

FIG. 7 shows output signals A, B, C, D, and E of the frequency dividing circuits 27A to 27C and the EXOR circuits 27D and 27E.
The frequency dividing circuit 27A sets the output signal A to the high level by the input of the clock signal CLK, then counts the clock signal CLK from the 36th input clock, and keeps the output signal A at the low level until the 89th clock.
The frequency dividing circuit 27B sets the output signal B to the high level by the input of the clock signal CLK, then counts the clock signal CLK from the 54th clock of the input, and keeps the output signal B at the low level until the 89th clock.
The frequency dividing circuit 27C sets the output signal B to the high level by the input of the clock signal CLK, then counts the clock signal CLK from the 72nd clock input, and keeps the output signal C to the low level until the 89th clock.

  The EXOR circuit 27D outputs the exclusive OR of the output signals A and B as the output signal D. The EXOR circuit 27E outputs an exclusive OR of the output signal D and the output signal C as the output signal E.

  As can be seen from FIG. 7, an arbitrary low-speed signal can be generated by appropriately setting the count start time in the frequency dividing circuits 27A to 27C. That is, it is possible to arbitrarily generate low-speed signals such as the vertical drive signals V1 to V4 shown in FIG. Further, since each signal shown in FIG. 7 is synchronized with the clock signal CLK, it can be completely synchronized with the high-speed signal read from the memory circuit 22.

In this embodiment, timing signals for driving the CCD 50 are classified into low-speed signals such as vertical drive signals V1 to V4 and high-speed signals such as horizontal drive signals H1 and H2, and these signals are generated. At this time, only high-speed signals are generated using a high-speed memory, and low-speed signals are generated by an FPGA logic circuit or the like. As a result, memory resources can be saved significantly, and the cost of the inspection apparatus can be reduced.
In addition, by using a memory and FPGA to generate timing signals for driving the CCD 50, it is possible to generate arbitrary waveforms for both high-speed signals and low-speed signals, and the number of channels can be varied. The combined design is very easy.

  In this embodiment, since the timing generator 12 is detachably mounted on the mother board 10, if the timing generator 12 is replaced in accordance with the specifications of the CCD 50, various specifications can be dealt with quickly and easily. .

  In the above-described embodiment, the case where the present invention is applied to a packaged CCD has been described. However, the present invention can also be applied to a solid-state image sensor before packaging. Further, the present invention can be applied to a solid-state imaging device other than a CCD.

It is a block diagram of the inspection apparatus of the solid-state image sensor to which this invention is applied. It is a figure which shows the structure of a motherboard. It is a schematic block diagram of CCD. It is a figure which shows an example of a vertical drive signal and a horizontal drive signal. It is a figure which shows the structure of a timing generator. It is a figure which shows an example of a structure of the low speed type | system | group signal generation circuit formed in FPGA. It is a figure which shows an example of the signal output from a low speed type | system | group signal generation circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Inspection apparatus, 2 ... Handler, 10 ... Motherboard, 12 ... Timing generator, 15 ... Socket, 18 ... Signal processing circuit, 30 ... Light source device, 45 ... Controller for handler, 46 ... Controller for board, 47 ... Controller for light source , 40A to 40D ... Processing device.

Claims (3)

An inspection apparatus for a solid-state image sensor that inspects photoelectric conversion characteristics of each pixel of the solid-state image sensor,
A timing generator that generates a timing signal for driving the solid-state imaging device;
The timing generator includes a memory circuit that stores a first signal of the timing signals;
A programmable signal generating circuit that generates a second signal of the timing signal that changes less frequently than the first signal;
A clock signal having a predetermined frequency is commonly supplied to the memory circuit and the signal generation circuit, and the first signal and the second signal are respectively output from the memory circuit and the signal generation circuit according to the clock signal. A solid-state imaging device inspection apparatus comprising: The second signal is photoelectrically converted by each photodiode arranged on the matrix of the solid-state imaging device, and is supplied to a vertical register for transferring the accumulated charge in the vertical direction of the imaging surface,
The solid-state image sensor inspection device according to claim 1, wherein the first signal is given to a horizontal register that transfers the charge transferred by the vertical register to an output unit of the solid-state image sensor. And further comprising a motherboard on which the timing generator, connection means for performing electrical connection with the solid-state image sensor, and a signal processing circuit for transferring signals to and from the solid-state image sensor through the connection means are mounted.
The solid-state imaging device inspection apparatus according to claim 1, wherein the timing generator is detachable from the motherboard.

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