JP2009077173A - Solid-state image pickup device and its inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS image sensor performing operation confirmation of a signal processing part without actually performing imaging, and easily attaining the operation confirmation by desired data. <P>SOLUTION: The CMOS image sensor is provided with: a pixel array part 2 in which pixels 1 are arranged like a matrix; vertical signal lines 16 wired by every pixel column; column latches 19 which are connected to the vertical signal lines to hold electric signals read from the pixels; and a horizontal transfer part 6 constituted so that selection signals for sequentially selecting the column latches are supplied, and is constituted so that predetermined data is supplied from each register of a shift register constituting a horizontal scanning part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and an inspection method thereof. More particularly, the present invention relates to an XY address type solid-state imaging device represented by a CMOS (Complementary Metal Oxide Semiconductor) image sensor and an inspection method thereof.

  Conventionally, as shown in FIGS. 2A and 2B, a CMOS image sensor includes a pixel array unit 102 in which a large number of pixels 101 having photoelectric conversion elements are arranged in a matrix, and each pixel array unit. A vertical scanning unit 103 that selects pixels one row at a time and controls the shutter operation and readout operation of each pixel, and a column signal that reads out signals from the pixel array unit one row at a time and performs predetermined signal processing for each column A processing unit 104, a horizontal scanning unit 106 that selects signals from the column signal processing unit one by one and guides them to the horizontal signal line 105, and a signal processing unit 107 that converts the data from the horizontal signal line into an intended output format And a timing generator 108 for supplying various pulse signals necessary for the operation of each unit based on the reference clock.

  Here, each pixel in the pixel array section, as shown in FIG. 3, transfers a photodiode (PD) 110 in which electrons generated by photoelectric conversion are accumulated, and an electron accumulated in the PD to a floating diffusion (FD) 111. A transfer transistor (transfer Tr) 112 for performing the operation, an amplification transistor (amplification Tr) 113 for converting the potential fluctuation of the FD into an electric signal by connecting the gate to the FD, and a pixel for reading the signal are selected in units of rows. A selection transistor (selection Tr) 114 for resetting, and a reset transistor (reset Tr) 115 for resetting the potential of FD to the power supply potential (Vdd). The selection Tr is connected to the vertical signal line 116 wired for each pixel column in a source follower structure.

  The column signal processing unit 104 includes a comparator 117, a column counter 118, and a column latch 119. The comparator 117 is connected to the vertical signal line, and charges accumulated in the pixels are input as pixel outputs. At the same time, a ramp wave whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock is input (see “ramp wave” in FIG. 4), and the relationship between the pixel output and the ramp wave is “(ramp When the relationship of “wave”> (pixel output) ”is satisfied, a high level (H level) signal is output. When the relationship of“ (ramp wave) <(pixel output) ”is satisfied, low level (L level) is output. It is configured to output a signal (see “Comparator output” in FIG. 4).

  Further, the column counter 118 is a DDR counter (Double Date Rate) counter, that is, a counter that employs a configuration that counts at both the rising timing and falling timing of the input counter clock (see “Counter output” in FIG. 4). “Refer to the above.) The count is stopped when the output signal from the comparator becomes L level, and the counter value is output as a digital value of the pixel output.

  The column latch 119 is configured to be able to capture the output of the column counter into the latch unit 119a based on the “column counter result capturing instruction signal” from the timing control unit in the signal processing unit, and to perform timing control in the signal processing unit. In response to a “data output instruction signal (selection signal)” issued from the horizontal scanning unit based on the “horizontal scanning start signal” from the unit, the output of the column counter taken in the latch unit is output to the horizontal signal line 105. It is configured.

  Further, the horizontal scanning unit has a shift register, and each register (flip-flop) constituting the shift register corresponds to a corresponding column latch based on a “horizontal scanning start signal” from the timing control unit in the signal processing unit. The "data output instruction signal" can be supplied sequentially.

  In the CMOS image sensor configured as described above, an arbitrary row of the pixel array unit is output and selected by a “row selection instruction” from the vertical scanning unit, and the selected row passes through a comparator and a column counter. Thus, pixel data is determined as the count value of the column counter. The count value of the column counter is taken into the latch part of the column latch based on the “column counter result take-in instruction signal” from the timing control part in the signal processing part. Thereafter, based on the “horizontal scanning start signal” from the timing control unit in the signal processing unit, the “data output instruction signal” is sequentially supplied from each register of the horizontal scanning unit, and the latch data of the column latch is sequentially applied to the horizontal signal line. Output. The data output to the horizontal signal line is taken into the sense amplifier 120, transferred to the signal processing unit, subjected to signal output processing by the signal data processing unit in the signal processing unit, and then output as a CMOS image sensor output. It becomes.

By the way, in the inspection of the conventional solid-state imaging device, particularly mass-production screening inspection, the solid-state imaging device is irradiated with light to actually take an image, and the inspection is performed using the imaging signal at that time (for example, patents) Reference 1).
According to such an inspection method for actually capturing an image, it is possible to perform an inspection in a state close to actual use conditions, and the quality of a solid-state image sensor is determined based on image information actually captured. This makes it easier to set sorting criteria for mass production sorting.

JP 2001-258053 A

  However, in the conventional solid-state imaging device inspection method described above, it is necessary to actually perform imaging even in the case where the operation confirmation regarding the processing after the data is taken in by the latch portion of the column latch is performed. . In the case of an inspection method that actually performs imaging, it takes a long time for inspection because it is necessary to control the light source or to wait for the storage time during actual use. In addition, since it is necessary to introduce a special system equipped with a high-precision light source for inspection instead of a normal logic tester, capital investment is increased.

  In addition, there is a demand for fetching desired data in the column latch when checking the operation regarding the processing after fetching the data in the latch section of the column latch. In this case, it is necessary to generate data to be captured by imaging, and imaging control for that purpose is very difficult.

  The present invention was devised in view of the above points, and can confirm the operation of the signal processing unit without actually performing imaging, and easily realize the operation confirmation with desired data. It is an object of the present invention to provide a solid-state imaging device capable of performing the same and an inspection method thereof.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a pixel array unit in which pixels are arranged in a matrix, a vertical signal line wired for each pixel column of the pixel array unit, and the vertical A holding unit that is connected to a signal line and holds an electrical signal read from the pixel, and a selection signal for sequentially selecting the holding unit can be supplied, and a predetermined data signal is supplied to the holding unit A horizontal scanning unit configured to be capable of being provided, and a signal processing unit that outputs an electrical signal read from a holding unit selected by the horizontal scanning unit.

  Here, a horizontal scanning unit configured to be able to supply a selection signal for sequentially selecting the holding unit and configured to be able to supply a predetermined data signal to the holding unit without performing imaging in the pixel array unit. The data signal can be input from the unit to the holding unit. In addition, since a data signal can be input from the horizontal scanning unit to the holding unit without performing imaging, desired data can be easily input to the holding unit.

  In order to achieve the above object, a solid-state imaging device inspection method according to the present invention includes a pixel array section in which pixels are arranged in a matrix, and a vertical signal wired for each pixel column of the pixel array section. A line, a holding unit that is connected to the vertical signal line and holds an electric signal read from the pixel, and a selection signal for sequentially selecting the holding unit, and a predetermined signal is supplied to the holding unit. A solid-state imaging device inspection method comprising: a horizontal scanning unit configured to be capable of supplying a data signal; and a signal processing unit that outputs an electrical signal read from a holding unit selected by the horizontal scanning unit. A step of inputting a predetermined data signal from the horizontal scanning unit to the holding unit, and a step of reading the predetermined data input to the holding unit to the signal processing unit.

  Here, by inputting a predetermined data signal from the horizontal scanning unit to the holding unit, it is possible to input the data signal to the holding unit without performing imaging at the pixel array unit. In addition, since a data signal can be input to the holding unit without performing imaging, desired data can be easily input to the holding unit.

  The solid-state imaging device inspection method according to the present invention includes a pixel array unit in which pixels are arranged in a matrix, a vertical signal line wired for each pixel column of the pixel array unit, and a connection to the vertical signal line A holding unit that holds the electric signal read from the pixel, a horizontal scanning unit including a shift register, and a signal processing unit that outputs the electric signal read from the holding unit selected by the horizontal scanning unit Each of the registers constituting the shift register is configured to be able to supply a selection signal for selecting the holding unit to the holding unit corresponding to the register, and a predetermined signal is supplied to the corresponding holding unit. A method of inspecting a solid-state imaging device configured to be able to supply a data signal, the step of transferring a predetermined data signal between the registers, and from the register to the holding unit corresponding to the register And a step of inputting the constant of the data signal, and a step of reading a predetermined data input to the holding unit to the signal processing unit.

  Here, by inputting predetermined data from the register to the holding unit to which the register corresponds, it is possible to input a data signal to the holding unit without performing imaging at the pixel array unit. In addition, since a data signal can be input to the holding unit without performing imaging, desired data can be easily input to the holding unit.

  In the solid-state imaging device and the inspection method thereof according to the present invention, since it is possible to input a data signal to the holding unit without imaging at the pixel array unit, the signal processing unit without actually imaging at the pixel array unit Can be confirmed.

  In addition, since a data signal can be input to the holding unit without performing imaging, a desired data signal can be easily input to the holding unit, and operation confirmation with the desired data signal can be easily realized. be able to.

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIGS. 1A and 1B are schematic views for explaining a CMOS image sensor as an example of a solid-state imaging device to which the present invention is applied. The CMOS image sensor shown here is the conventional CMOS described above. Similar to the image sensor, a pixel array unit 2 in which a large number of pixels 1 having photoelectric conversion elements are arranged in a matrix, and each pixel of the pixel array unit is selected one by one to perform shutter operation and readout operation of each pixel. The vertical scanning unit 3 to be controlled, the signal from the pixel array unit are read out one row at a time, the column signal processing unit 4 that performs predetermined signal processing for each column, and the signal of the column signal processing unit are selected one by one A horizontal scanning unit 6 that leads to the horizontal signal line 5, a signal processing unit 7 that converts the signal from the horizontal signal line into an intended output format, and various pulses necessary for the operation of each unit based on a reference clock Having a timing generator 8 supplies the No..

  Here, each pixel in the pixel array section includes a PD 10 in which electrons generated by photoelectric conversion are accumulated, a transfer Tr 12 for transferring the electrons accumulated in the PD to the FD 11, a gate, as in the conventional CMOS image sensor. Is connected to the FD to amplify the Tr 13 for converting the FD potential variation into an electric signal, the selection Tr 14 to select the pixel from which the signal is read out in units of rows, and reset the FD potential to the power supply potential (Vdd). For resetting Tr15. The selection Tr is connected to the vertical signal line 16 wired for each pixel column in a source follower structure (see FIG. 3).

  The column signal processing unit has a comparator 17, a column counter 18, and a column latch 19 as in the conventional CMOS image sensor. The comparator 17 is connected to the vertical signal line and is stored in the pixel. The charge is input as the pixel output, and a ramp wave whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock is input. The relationship between the pixel output and the ramp wave is “(Ramp wave)> ( When the relationship “pixel output)” is satisfied, an H level signal is output, and when the relationship “(ramp wave) <(pixel output)” is satisfied, an L level signal is output.

  Further, the column counter 18 is a DDR counter, and is configured to stop counting when the output signal from the comparator becomes L level and output the counter value as a pixel output digital value.

  Here, in this embodiment, a ramp wave whose output decreases at a constant rate at the rising timing and falling timing of the counter clock is taken as an example, and the counter is counted at the timing when the output signal from the comparator becomes L level. However, the output signal from the comparator uses a ramp wave whose output increases at a constant rate at the rising and falling timings of the counter clock. The counter may be stopped at the timing when becomes H level. Furthermore, in the present embodiment, the DDR counter is described as an example, but it is needless to say that the type of the counter is not particularly limited.

  The column latch 19 is configured to be able to capture the output of the column counter into the latch unit 19a based on the “column counter result capturing instruction signal” from the timing control unit in the signal processing unit, and to perform timing control in the signal processing unit. In response to a “data output instruction signal (selection signal)” from the horizontal scanning circuit that is issued based on the “normal operation horizontal scanning start signal” from the unit, the output of the column counter that is fetched into the latch unit is output to the horizontal signal line 5 It is configured to do.

  Further, in the column latch of the CMOS image sensor to which the present invention is applied, the latch unit 19a receives the data output instruction signal from the horizontal scanning unit based on the “data output instruction signal as the latch data” from the timing control unit in the signal processing unit. The “data output instruction signal” can be fetched as latch data.

  The horizontal scanning unit includes a selector 20 and a shift register. The selector includes a “normal operation horizontal scanning start signal”, a “sense amplifier test operation signal”, and “normal” from the timing control unit in the signal processing unit. "Operation / test operation switching signal" is input, and the selector can output either "normal operation horizontal scanning start signal" or "sense amplifier test operation signal" based on "normal operation / test operation switching signal" It is configured.

  Furthermore, each register constituting the shift register can sequentially supply a “data output instruction signal (selection signal)” to the corresponding column latch when the output signal from the selector is “horizontal scanning start signal during normal operation”. When the output signal from the selector is a “sense amplifier test operation signal”, the output signal from the selector is supplied as latch data to the latch section of the corresponding column latch.

  Further, the signal processing unit supplies a “flip-flop shift operation clock” to each register constituting the shift register, and “normal operation horizontal scanning start signal”, “sense amplifier test operation signal”, and “normal operation / A timing control unit that supplies a test operation switching signal “to a selector in the horizontal scanning unit and supplies a“ column counter result fetch instruction signal ”and a“ fetch instruction signal as a data output instruction signal as latch data ”to a latch in the column latch. 21, a signal data processing unit 22 that performs data output processing of data transferred from the sense amplifier during normal operation, and data transferred from the sensor amplifier during sense amplifier test operation are compared with expected value data, and the comparison result is obtained. A test expected value confirmation unit 23 for outputting to the outside is provided.

  In the CMOS image sensor configured as described above, when performing imaging, an arbitrary row in the pixel array unit is output-selected by a “row selection instruction” from the vertical scanning unit, as in the case of a conventional CMOS image sensor. Thus, the pixel data of the selected row is determined as the count value of the column counter via the comparator and the column counter. The count value of the column counter is taken into the latch part of the column latch based on the “column counter result take-in instruction signal” from the timing control part in the signal processing part. The selector is set to output a “normal operation horizontal scanning start signal” based on the “normal operation / test operation switching signal” from the timing signal control unit in the signal processing unit. Based on the “horizontal scanning start signal during normal operation” from the control unit, the “data output instruction signal” is sequentially supplied from each register of the horizontal scanning unit, and the latch data of the column latch is sequentially output to the horizontal signal line. It becomes. The data output to the horizontal signal line is taken into the sense amplifier 20, transferred to the signal processing unit, subjected to signal output processing by the signal processing unit in the signal processing unit, and then output as a CMOS image sensor output. Become.

  When checking the operation after fetching data in the latch section of the column latch, first, the selector performs “sense” based on the “normal operation / test operation switching signal” from the timing control section in the signal processing section. "Amplifier test operation signal" is set to be output, and "Sense amplifier test operation signal" from the timing control unit in the signal processing unit is sequentially supplied to each register of the shift register. Desired data is set. Thereafter, based on a “data output instruction signal as a latch data instruction signal as latch data” from the timing control section in the signal processing section, desired data set in each register is captured in the latch section of the column latch. .

  Subsequently, the selector is set to output a “normal operation horizontal scanning start signal” based on the “normal operation / test operation switching signal” from the timing control unit in the signal processing unit, and the timing control in the signal processing unit is performed. Based on the “normal operation horizontal scanning start signal” from the unit, the “data output instruction signal” is sequentially supplied from each register of the horizontal scanning unit, and the latch data of the column latch is sequentially output to the horizontal signal line. When the data output to the horizontal signal line is taken into the sense amplifier 20, transferred to the signal processing unit, and compared with a predetermined expected value by the expected value confirmation unit in the signal processing unit, there is no problem as a result of the comparison. Outputs “1” as the expected value confirmation state, and outputs “0” as the expected value confirmation state when a problem occurs as a result of the comparison.

  In the CMOS image sensor and the inspection method to which the present invention is applied, the operation check after the data is taken in by the latch portion in the column latch does not depend on the data imaged in the pixel array portion, and further, desired The operation can be confirmed using the data signal.

Further, even in the case of a solid-state imaging device in which a high-speed interface is used as a communication means, it is easy to determine whether a CMOS image sensor is defective or a high-speed interface is defective.
That is, since the conventional solid-state imaging device inspection method actually performs imaging, the result of the operation check is also output in the same manner as the sensor output during normal operation. And, in the case of a solid-state imaging device that uses a high-speed interface as a communication means, since the output is made through the high-speed interface, if there is a problem with the data output through the high-speed interface, It is not easy to determine whether the CMOS image sensor is defective or the high-speed interface is defective, and as a result, it is difficult to confirm the operation of the CMOS image sensor. On the other hand, in the CMOS image sensor and the inspection method to which the present invention is applied, since the comparison result in the expected value confirmation unit is output separately from the sensor output that outputs via the high-speed interface, specifically, Since the operation confirmation data is output without going through the high-speed interface, the operation confirmation of the CMOS image sensor can be surely performed.

  FIG. 5 shows an example of a timing chart of each signal in the case of performing a CMOS image sensor inspection method to which the present invention is applied.

  In the timing chart shown here, the “normal operation / test operation switching signal” is set to the H level at the timing indicated by the symbol t1 in the figure, and the test operation mode is selected, so that the “sense amplifier test operation signal” is used for the flip-flop operation. In synchronization with the clock, test data is set as a “data output instruction signal” in each register constituting the shift register.

  Next, when the test data is set up to the final register (the nth register), the “data output instruction signal as the latch data as the latch data” is set to the H level at the timing indicated by t2 in the figure. The “data output instruction signal” is taken in as data in each column latch column.

  Subsequently, the normal operation mode is selected by setting the “normal operation / test operation switching signal” to the L level at the timing indicated by the symbol t3 in the figure, and the “normal operation horizontal scanning start signal” is set to the H level by one pulse. Thus, in synchronization with the “flip-flop operation clock”, a “data output instruction signal” for sequentially selecting each register is output, and the data fetched into the column latch is read.

  In the timing chart shown here, for the same setting data, a period indicated by symbols t3 to t4 in the drawing, a period indicated by symbols t4 to t5 in the drawing, a period indicated by symbols t5 to t6 in the drawing, and a symbol t6 to A case where reading is performed five times in total during a period indicated by t7 and a period indicated by reference numerals t8 to t9 in the figure is taken as an example.

  The CMOS image sensor is inspected according to the timing chart as described above, but the “expected value confirmation state” from the expected value confirmation unit in the signal processing unit is H level (output of “1” as the expected value confirmation state). In some cases, there is no problem with the output of the CMOS image sensor, and when the “expected value confirmation state” is L level (output of “0” as the expected value confirmation state), there is a problem with the output of the CMOS image sensor. It shows that. That is, the “expected value confirmation state” changes from the H level to the L level at the timing indicated by the symbol t9 in the figure, which indicates that there is a problem with the output of the CMOS image sensor.

It is a schematic diagram (1) for demonstrating the CMOS image sensor which is an example of the solid-state image sensor to which this invention is applied. It is a schematic diagram (2) for demonstrating the CMOS image sensor which is an example of the solid-state image sensor to which this invention is applied. It is a schematic diagram (1) for demonstrating the conventional CMOS image sensor. It is a schematic diagram (2) for demonstrating the conventional CMOS image sensor. It is a schematic diagram for demonstrating the structure of a pixel. It is a schematic diagram for demonstrating operation | movement of a comparator. 2 shows an example of a timing chart of each signal when performing a CMOS image sensor inspection method to which the present invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel 2 Pixel array part 3 Vertical scanning part 4 Column signal processing part 5 Horizontal signal line 6 Horizontal scanning part 7 Signal processing part 8 Timing generator 10 PD
11 FD
12 Transfer Tr
13 Amplified Tr
14 Selection Tr
15 Reset Tr
16 Vertical Signal Line 17 Comparator 18 Column Counter 19 Column Latch 19a Latch Unit 20 Selector 21 Timing Control Unit 22 Signal Data Processing Unit 23 Test Expected Value Confirmation Unit

Claims (6)

A pixel array section in which pixels are arranged in a matrix;
A vertical signal line wired for each pixel column of the pixel array section;
A holding unit that is connected to the vertical signal line and holds an electrical signal read from the pixel;
A horizontal scanning unit configured to supply a selection signal for sequentially selecting the holding unit, and configured to supply a predetermined data signal to the holding unit;
A solid-state imaging device comprising: a signal processing unit that outputs an electrical signal read from a holding unit selected by the horizontal scanning unit. The horizontal scanning unit includes a shift register,
Each register constituting the shift register is configured to be able to supply a selection signal for selecting the holding unit to the holding unit corresponding to the register and to supply a predetermined data signal to the corresponding holding unit. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to be possible. The solid-state imaging device according to claim 1, wherein the signal processing unit includes an expected value confirmation unit that compares the read electrical signal with a predetermined expected value and outputs a result of the comparison. A pixel array section in which pixels are arranged in a matrix;
A vertical signal line wired for each pixel column of the pixel array section;
A holding unit that is connected to the vertical signal line and holds an electrical signal read from the pixel;
A horizontal scanning unit configured to supply a selection signal for sequentially selecting the holding unit, and configured to supply a predetermined data signal to the holding unit;
A solid-state imaging device inspection method comprising: a signal processing unit that outputs an electrical signal read from a holding unit selected by the horizontal scanning unit,
Inputting a predetermined data signal from the horizontal scanning unit to the holding unit;
And a step of reading predetermined data input to the holding unit to the signal processing unit. A pixel array section in which pixels are arranged in a matrix;
A vertical signal line wired for each pixel column of the pixel array section;
A holding unit that is connected to the vertical signal line and holds an electrical signal read from the pixel;
A horizontal scanning unit comprising a shift register;
A signal processing unit that outputs an electrical signal read from the holding unit selected by the horizontal scanning unit,
Each register constituting the shift register is configured to be able to supply a selection signal for selecting the holding unit to the holding unit corresponding to the register, and supply a predetermined data signal to the corresponding holding unit. An inspection method for a solid-state image sensor configured to be possible,
Transferring a predetermined data signal between the registers;
A step of inputting a predetermined data signal from the register to the holding unit corresponding to the register;
And a step of reading predetermined data input to the holding unit to the signal processing unit. The solid-state imaging device inspection method according to claim 4, further comprising a step of comparing the electric signal read out to the signal processing unit with a predetermined expected value and outputting a result of the comparison.

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