JP4417519B2 - Mobile station and its current consumption reduction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem of a conventional mobile station adopting multi- processor control in an FDMA system digital mobile communication system conducting intermittent reception in the standby state that has its own average current consumption because data denoting whether or not paging exists in its own station at the intermittent reception are layer 2 information resulting that a processor to start the processing of the layer 2 or over is to be started with a processor processing the layer 1. SOLUTION: A bit processing function for part bit of layer 2 data is added to a processor that processes the layer 1. The processor processing the layer 1 discriminates whether or not paging to itself exists. When no paging is applied to its own station, the processor processing the layer 2 is not started to reduce the average current consumption of the mobile station.

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiprocessor-controlled mobile station and a method for reducing current consumption in an FDMA digital mobile communication system including a base station and a mobile station.
[0002]
[Prior art]
A conventional intermittent reception of a mobile station in a narrowband digital communication system (SCPC / FDMA) standard, ARIB STD-T61, which is an FDMA digital mobile communication system, will be described. FIG. 4 is a system configuration diagram, and this system includes a radio base station (hereinafter referred to as a base station) and a plurality of mobile stations. FIG. 4 shows one base station 41 and two mobile stations 42 and 43. From the base station 41, various control signals are constantly transmitted through the control channel for information notification, call connection, and the like, and the mobile stations 41 and 42 perform call connection through the control channel. Rather than operating the receiver at all times during standby, intermittent reception is performed in which the reception operation is performed only during a time period during which a general call channel (PCH) for sending an incoming signal to the mobile station is being sent. The signal structure of the control channel is a hierarchical structure conforming to the OSI model, and includes a physical layer, a data link layer, and a network layer. These are hereinafter referred to as layer 1, layer 2, and layer 3.
[0003]
FIG. 3 shows a hardware configuration example of the mobile station apparatus (reception processing unit). A radio signal is received by the RF receiver 31, converted into a digital signal by the A / D converter 32, and demodulated by a DSP (digital signal processing device) 33 that is a linear receiver. The demodulated signal is decoded by the DSP 34 that performs layer 1 processing, and passed to the MPU 36 that performs layer 2 and 3 processing via the DPRAM 35 that is a dual port RAM. The DSP 34 sets a value in the start / stop timer 37 that sets the intermittent reception intervals of the MPU 36, DSP 34, and DSP 33. The MPU 36 analyzes the received data and gives an instruction for intermittent reception. The start / stop control circuit 38 starts and stops the MPU 36, the DSP 34, and the DSP 33 according to the value set in the timer 37. The ROM 39 stores information necessary for the mobile station such as a mobile station identifier (MSI) for identifying the mobile station, and the MPU 36 reads it out as necessary.
[0004]
FIG. 5 shows a configuration of the base station downlink control channel and an arrangement example of the general call channel (PCH). The frame length of the radio channel is 40 ms, and a super frame is configured with 18 times the frame length as a unit. The control channel has a super frame structure, and a broadcast channel (BCCH), a general call channel (PCH), and the like are arranged at predetermined positions in the super frame. In the figure, a PCH is arranged on the frame 16. The mobile station receives the PCH after registering the location with the base station, and enters the incoming call process if the mobile station identifier (MSI) calling the mobile station is transmitted to the PCH. Therefore, the mobile station receives only PCH intermittently during standby. This intermittent reception allows the mobile station to reduce current consumption during standby.
[0005]
FIG. 2 shows a block diagram of intermittent reception processing in the prior art. In FIG. 2, the DSP 34 in FIG. 3 is described as the processor 1, and the MPU 36 is described as the processor 2. The mobile station that has received the PCH at the time of standby demodulates the received data of the PCH by the reception data demodulation processing unit 20 (corresponding to the DSP 33), and the data is decoded by the data decoding processing unit 21 of the processor 1 (corresponding to the DSP 34) that performs layer 1 processing. Is decrypted. The decoded data is sent to the processor 2 (corresponding to the MPU 36) that performs data layer 2 and 3 processing, and is analyzed by the data analysis unit 23 of the processor 2, and whether the reception processing of the mobile station is continuous reception or intermittent reception. The continuous reception / intermittent reception instruction unit 24 notifies the processor 1 of the result. In the case of intermittent reception, the processor 1 calculates the stop time intervals of the processors 1 and 2 and the reception data demodulation processing unit 20 and sets them in the timer 37. The start / stop control circuit 38 stops and starts the processors 1 and 2 and the reception data modulation unit 20 according to the timer set value. In the case of continuous reception, the reception is continued without stopping the operations of the processors 1 and 2 and the reception data modulation unit 20.
[0006]
FIG. 9 shows an example of time change of current consumption of the processors 1 and 2 in the prior art. The mobile station has received only the PCH of frame 16 in the superframe of FIG. FIG. 9A shows the position of the PCH in the downlink control CH. The hatched portion is PCH, and the figure shows the case where the first two are simultaneous calls (paging) to other stations and the third is paging to the own station. FIG. 9B shows the current consumption of the processor 1. In accordance with the value set in the timer 37 shown in FIGS. 2 and 3, the start / stop control circuit 38 operates the processor 1 for a certain period of time at intervals of sending PCH. Similarly, the current consumption of the processor 2 is shown in FIG. The processor 2 also operates at the same cycle as the processor 1. That is, the processor 1 and the processor 2 are operated regardless of paging to another station or paging to the own station. FIG. 10 shows a detailed time change example of current consumption of the processors 1 and 2 in the prior art. FIG. 10A shows the PCH position of the downlink control channel in an enlarged manner. FIG. 10B shows current consumption of the processor 1, and current is consumed only during the time areas 91, 92 and 93. The time area 91 is a time during which the PCH data is decoded, and corresponds to the PCH frame time. When the processor 1 decodes the PCH data in the time area 91, the processor 1 starts up the processor 2 and delivers the decoded data. FIG. 10C shows the current consumption of the processor 2, which is operating for the time areas 94 and 95. The processor 2 analyzes the decoded data received from the processor 1 in the time area 94, determines whether it is continuous reception or intermittent reception, and if it is intermittent reception, instructs the processor 1 to perform intermittent reception. When receiving the instruction, the processor 1 sets the start / stop interval of the processors 1 and 2 in the time area 93 to the timer and stops the operation. A time area 92 is a time during which the processor 1 performs layer 1 processing other than data decoding, and a time area 95 is a time during which the processor 2 performs processing of layers 2 and 3 other than received data analysis.
[0007]
FIG. 20 shows an intermittent reception processing flow of the processor 1 in the prior art. Whether the processor 1 decodes the PCH data received from the reception data demodulator 21 (STEP 120), sends the decoded data to the processor 2 (STEP 121), and performs continuous reception or intermittent reception from the processor 2 (STEP 122). If the received result is continuous reception (NO in STEP122), the received data decoding process is continued (STEP123), and an instruction from the processor 2 is awaited (STEP122). If it is intermittent reception (YES in STEP 122), values are set in the start / stop timers of the processors 1 and 2 and the reception data demodulator 21 (STEP 124), and the operation is stopped. As a result, the mobile station shifts to an intermittent reception state.
[0008]
As described above in detail, since the information of the PCH data received by the mobile station at the time of intermittent reception is information of layer 2 or higher, in the case of the multiprocessor system, the processor 2 usually analyzes this data. Therefore, it is necessary to activate the processor 2 every time PCH is received. In addition, since the stop processing for shifting to the intermittent operation has to wait for the data analysis of the processor 2, the conventional mobile station has been operating for both the processors 1 and 2 for a long time.
[0009]
[Problems to be solved by the invention]
As described above, it is a problem to reduce the average current consumption of the mobile station that both the processor 1 and the processor 2 must be operated in the intermittent reception during standby.
[0010]
It is an object of the present invention to reduce the average current consumption of the processor 2 by performing the determination of continuous reception / intermittent reception normally performed by the processor 2 in the multiprocessor-controlled FDMA mobile communication system. It is an object of the present invention to provide a mobile station and a current consumption reduction method thereof.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a processor 1 for processing layer 1 data and a processor 2 for processing layer 2 and layer 3 data in an FDMA digital mobile communication system that performs intermittent reception during standby. In mobile stations operating under multiprocessor control,
In the processor 1,
Data decoding means for decoding the received demodulated data;
Bit analysis of layer 2 or higher data decoded by the data decoding means at the time of intermittent reception, and there is a shortened mobile station identifier in the received address field, or if there is a mobile station identifier and the identifier is An activating means for activating the processor 2 by determining that the activation of the processor 2 is necessary only when the station identifier matches the station identifier;
Timer setting means for calculating a stop time interval between the processor 1 and the processor 2 for intermittent reception and setting the timer;
A mobile station characterized in that is provided.
[0012]
The present invention also includes a processor 1 that processes layer 1 data and a processor 2 that performs layer 2 and layer 3 data processing in an FDMA digital mobile communication system that performs intermittent reception during standby. In a method for reducing current consumption of an operating mobile station,
At the time of intermittent reception, the processor 1 performs bit analysis on the data of layer 2 or higher, and there is a shortened mobile station identifier in the received address field subjected to bit analysis, or there is a mobile station identifier and the identifier is the mobile station of its own mobile station Provided is a method for reducing current consumption of a mobile station, characterized in that the processor 2 is activated only when it matches the identifier.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail. FIG. 1 is a block diagram showing a configuration example of a mobile station according to the present invention. A reception data demodulator 10 composed of a digital signal processor demodulates received modulation data. This received data is passed to the processor 1 that processes layer 1. In the processor 1, a data composite unit 11 for decoding layer 1 data, a processor 2 activation determination unit 12 for performing activation determination of the processor 2 for performing processing of layers 2 and 3, and an interval for intermittent reception of each processor are set. There is a start / stop timer setting unit 13. The processor 2 that performs the processing of layers 2 and 3 determines whether to perform continuous reception or intermittent reception based on the analyzed data, the data analysis unit 14 that performs data analysis of the layer 2 or higher, and the processor There is a continuous / intermittent reception instructing unit 15 for instructing 1. The timer 16 is set with a stop time interval of each processor at the time of intermittent reception, and the start / stop control circuit 17 controls the start and stop of the processors 1 and 2 and the reception data demodulator 10 based on this value.
[0014]
Next, the data structure of the PCH defined in the narrowband digital communication system (SCPC / FDMA) and ARIB STD-T61 will be described in detail. FIG. 11 shows PCH channel coding. One frame of radio section is 384 bits, 30 bits linearizer preamble (LP) and burst transient response time (R), 2 bits preamble (P), 96 bits general call channel (PCH), 56 bits It consists of a radio information channel (RICH), a 20-bit synchronization word (SW), a 4-bit idle bit (I), and a 176-bit PCH. The PCH data part is 96 + 176 = 272 bits. This is subjected to descrambling, deinterleaving, and error correction decoding to obtain W (8 bits) of signal configuration information and information of layer 2 or higher (88 bits) as PCH data. FIG. 12 shows the configuration of PCH data transmitted in one frame. It is composed of 1 octet W (signal configuration information) and 11 octets of layer 2 or more information. The 0th to 5th bits of W are W0, the 6th bit is F2, and the 7th bit is F1. If F1 is 0, this unit is a non-leading unit, and if it is 1, it indicates the leading unit. If F2 is 0, this unit is a non-final unit, and if it is 1, it indicates the final unit. W0 indicates the number of valid bytes when F2 = 1, and indicates the number of remaining units when F2 = 0.
[0015]
FIG. 13 shows the layer 2 data frame format. A layer 2 data frame includes an address field, a control field, and information, and is composed of a plurality of octets. FIG. 14 shows an address field format. The fourth and fifth bits of the first octet are AI (ID display field), and the second and subsequent octets are SMSI (abbreviated mobile station identifier) and MSI (mobile station identifier). FIG. 15 shows the contents of the ID display field (AI). The MSI and SMSI included in the address field are identified by the value of AI. For example, as shown in FIG. 15, if AI is “00”, neither SMSI nor MSI exists, and if “01”, only MSI exists. FIG. 16 shows the SMSI format, and FIG. 17 shows the MSI format. The SMSI is an identifier selected by the base station and temporarily assigned to the mobile station, and has a fixed length of 1 octet. The MSI is a fixed address unique to the mobile station. The length of the MSI is variable and is determined by EA (address field extension bit). If EA is “0”, it is a non-final octet, and if “1”, it is a final octet. MSI has a maximum bit length of 64 bits and 10 octets.
[0016]
Next, the operation of the intermittent processing of the present invention will be described in detail based on the intermittent reception processing flow of the processor 1 shown in FIGS. When the received data from the received data demodulator 10 is decoded by the data decoder 11 (STEP 101), the processor 2 activation determination unit 12 determines whether the processor 2 needs to be activated. For this, first, it is determined whether or not it is the head unit by looking at the seventh bit (F1) of the first octet of the PCH data in FIG. 12 (STEP 102). If F1 is “1” and the first unit (YES in STEP 102), then it is checked whether there is an SMSI (STEP 103). This can be done by looking at the second octet in FIG. That is, the second octet of FIG. 12 is the first octet of the layer 2 data frame format of FIG. 13 and the first octet of FIG. The fourth and fifth bits (AI) of the first octet of FIG. 14 can be used to determine whether SMSI is included or MSI is included. If the SMSI is included (YES in STEP 103), the processor activation determining unit 12 activates the processor 2 (STEP 107), sends data to the processor 2 (STEP 108), and the data decoding unit 11 continues the received data decoding process. (STEP 109).
[0017]
If there is no SMSI (NO in STEP 103), then it is checked whether there is an MSI (STEP 104). If the MSI is included (YES in STEP 104), the processor 1 compares the MSI of the local station previously notified from the processor 2 with the received MSI (STEP 105), and if they match (YES in STEP 106), the processor activation determination The unit 12 activates the processor 2 (STEP 107), sends data to the processor 2 (STEP 108), and the data decoding unit 12 continues the received data decoding process (STEP 109). If the reception data processing is continued (STEP 109), the decoded data is sent to the processor 2, the layer 2 or higher is analyzed by the data analysis unit 14 of the processor 2, and an instruction as to whether or not to shift to intermittent reception is received. The signal is sent from the intermittent reception instruction unit 15 to the processor 1. The processor 1 has received an intermittent reception instruction (STEP 110), but if no intermittent reception instruction has been received (NO in STEP 110), the reception data decoding process is continued (STEP 109), and if an intermittent reception instruction has been received (YES in STEP 110). Then, the start / stop timer setting unit 13 sets the interval of intermittent reception to the timer 16 (STEP 112). When the timer is set, the start / stop control circuit 17 controls the start / stop of the processor 1, the processor 2, and the reception data demodulator 10 according to the timer and enters an intermittent reception state.
[0018]
If F1 of the PCH data is not “1” (NO in STEP 102), there is no MSI in the address field (NO in STEP 104), and even if there is an MSI, it does not match the MSI of the local station (NO in STEP 106). The remaining units of PCH are calculated from F2 and W0 (STEP 111), and the processor 1 sets the intermittent reception interval to the timer 16 by the start / stop timer setting unit 13 of the processor 1 without starting the processor 2 (STEP 112). When the timer is set, the start / stop control circuit 17 controls the start / stop of the processor 1, the processor 2, and the reception data demodulator 10 according to the timer, and enters the intermittent reception state. That is, if the PCH does not have its own MSI, intermittent reception can be performed without activating the processor 2.
[0019]
FIG. 18 shows activation determination conditions for the processor 2. That is, when F1 is “1” and AI is “01” and the received MSI matches the local station MSI, or when F1 is “1” and AI is “10” or “11”, processor 1 is processor 2 Is activated, otherwise it is not activated. In this way, the processor 1 can easily determine whether or not the processor 2 is to be activated by reading and determining only F1, AI, and MSI by bit processing. If the SMSI is present, the processor 2 is unconditionally activated when the SMSI is used in a bidirectional channel (SCCH: signal channel and UPCH: user packet channel) between the base station and the mobile station. SMSI is not used because PCH is a one-way channel. If the received PCH includes the SMSI, it means that the channel received with the PCH is not PCH. That is, since the frame structure of the control channel has changed, it is necessary to start the processor 2 in order to know the correct PCH position.
[0020]
FIG. 6 shows an example of a change over time in current consumption of the processors 1 and 2 in the present invention. FIG. 6A shows the PCH transmission time of the downlink control channel. This is an example in which PCH is sent to the hatched area, the first two are paging to other stations, and the third is paging to the own station. FIG. 6B shows a change in current consumption of the processor 1, which operates corresponding to the interval at which PCH is sent. On the other hand, FIG. 6C shows a change in current consumption of the processor 2, which does not operate when paging to another station and operates only when paging to the own station. FIG. 7 shows an example of detailed changes in current consumption over time when the processors 1 and 2 according to the present invention receive paging to other stations. The processor 1 is operating in the time areas 71, 72, and 73. Since the mobile station is performing intermittent reception, the start / stop control circuit 17 in FIG. 1 starts the processor 1 when it is time to send PCH. The processor 1 that has started the operation decodes the data of the downlink control channel in the time area 71 by the data decoding unit 11 and determines whether or not the processor 2 needs to be activated in the time area 72. In FIG. 7, paging to another station is not included in the data because the MSI of the own station is not included in the data. The processor 1 stops its operation. In FIG. 7, since the processor 2 is not activated, the current consumption of the processor 2 is zero.
[0021]
FIG. 8 is a detailed example of a change in current consumption over time when the processors 1 and 2 according to the present invention receive paging to the own station. The processor 1 is operating in the time areas 81, 82, 83, 84, and 85. Since the mobile station is performing intermittent reception, the start / stop control circuit 17 in FIG. 1 starts the processor 1 when it is time to send PCH. The processor 1 that has started the operation decodes the data of the downlink control channel in the time area 81 by the data decoding unit 11 and determines whether or not the processor 2 needs to be activated in the time area 82. Since it is paging to the own station in FIG. 8, it is determined in the time area 83 that the MSI of the own station is included in the data, the processor 2 is activated, and the decoded data is sent to the processor 2. The time during which the activated processor 2 is operating is the time areas 86 and 87. In the time area 86, the data analysis unit 14 of the processor 2 analyzes the layer 2 data, and instructs the processor 1 to perform intermittent reception when it is time to perform intermittent reception. When the processor 1 receives this instruction, the start / stop timer setting unit 13 sets the value of the intermittent reception interval in the timer 16 in the time area 85 and the processor 1 stops its operation. In the time area 84 of the processor 1, other processing of layer 1 is performed. When the processor 2 also sends an intermittent reception instruction to the processor 1, it performs other processes of layers 2 and 3 in the time area 87, and stops its operation when the process ends.
[0022]
FIG. 9 showing the current consumption of the processors 1 and 2 according to the conventional method at the time of standby and FIG. 6 showing the current consumption of the processors 1 and 2 according to the present invention are compared. The current consumption of the processor 2 is also required during paging, but the current consumption is 0 in FIG. When PCH is received during normal standby, the probability of paging to the local station is extremely low, and the fact that the current consumption of the processor 2 becomes zero is a great effect on the reduction of the average current consumption. In the conventional method, the decoded data is passed to the processor 2, and the processor 2 determines whether the paging to the other station or the paging to the own station is performed as the layer 2 processing. The processor 1 is operating during the determination. . On the other hand, in the present invention, the paging to the other station or the paging to the own station is determined by the bit processing of the processor 1. Since the processing time is shorter in the bit processing than the determination in the layer 2, the operation time of the processor 1 is shorter in the present invention than in the conventional method, and the average current consumption of the processor 1 is also higher than that in the conventional method. There is also an advantage of less.
[0023]
【The invention's effect】
According to the present invention, in a multiprocessor-controlled mobile station of an FDMA digital mobile communication system, it is possible to reduce the average current consumption of the mobile station during standby, and to extend the charging interval of the rechargeable battery of the mobile station. In addition, the size of the battery mounted on the mobile phone can be reduced, and the mobile phone can be reduced in size and weight.
[Brief description of the drawings]
FIG. 1 is a block diagram of intermittent reception processing of the present invention.
FIG. 2 is a block diagram of a conventional intermittent reception process.
FIG. 3 is a hardware configuration diagram of a reception processing unit of a mobile station.
FIG. 4 is a system configuration diagram of a mobile communication system.
FIG. 5 is a diagram illustrating a configuration of a downlink control channel and an arrangement example of a general call channel (PCH).
FIG. 6 is a diagram showing an example of a change over time of current consumption of processors 1 and 2 of the conventional method.
FIG. 7 is a diagram showing a detailed example of a change in current consumption time of processors 1 and 2 when paging is received at another station in the conventional method.
FIG. 8 is a diagram showing a detailed example of a change in current consumption time of processors 1 and 2 when receiving paging by the local station in the conventional method.
FIG. 9 is a diagram showing a detailed example of a change in current consumption time of the processors 1 and 2 when paging is received at another station of the present invention.
FIG. 10 is a diagram showing a detailed example of a change in current consumption time of processors 1 and 2 when receiving own-page paging according to the present invention.
FIG. 11 is a diagram of PCH channel coding.
FIG. 12 is a PCH frame configuration diagram.
FIG. 13 is a diagram of a layer 2 data frame format.
FIG. 14 is a diagram showing the contents of an ID display field (AI).
FIG. 15 is a diagram illustrating the meaning of an ID display field (AI).
FIG. 16 is a diagram of a shortened mobile station identifier (SMSI) format.
FIG. 17 is a format diagram of a mobile station identifier (MSI).
FIG. 18 is a diagram showing activation conditions for the processor 2;
FIG. 19 is a diagram showing an operation flow of the processor 1 of the present invention.
FIG. 20 is a flowchart of the operation of the conventional processor 1;
[Explanation of symbols]
10, 20 Received data demodulation unit 11, 21 Data decoding unit 12 Processor 2 activation determination unit 13, 22 Activation / deactivation timer setting unit 14, 23 Data analysis unit 15, 24 Continuous reception / intermittent reception instruction unit 16, 37 Timer 17, 38 Start / Stop Control Circuit 31 RF Receiver 32 A / D Converter 33, 34 Digital Signal Processing Device (DSP)
35 Dual Port Ram (DPRAM)
36 MPU
39 RAM
41 wireless base station 42 mobile station 71-73 hour area 81-87 hour area 91-95 hour area

Claims (2)

A mobile station operating in multiprocessor control, having a processor 1 for processing layer 1 data and a processor 2 for processing layer 2 and layer 3 data in an FDMA digital mobile communication system that performs intermittent reception during standby In
In the processor 1,
Data decoding means for decoding the received demodulated data;
Bit analysis is performed on data of layer 2 or higher decoded by the data decoding means at the time of intermittent reception , and when there is a shortened mobile station identifier in the paging channel of the received address field subjected to bit analysis, and there is a mobile station identifier and when the identifier matches the mobile station identifier of the mobile station, and starting means for starting the processor 2 determines the required starting the saw processor 2 when their,
Timer setting means for calculating a stop time interval between the processor 1 and the processor 2 for intermittent reception and setting the timer;
A mobile station characterized in that a mobile station is provided. A mobile station operating in multiprocessor control, having a processor 1 for processing layer 1 data and a processor 2 for processing layer 2 and layer 3 data in an FDMA digital mobile communication system that performs intermittent reception during standby In the current consumption reduction method of
During intermittent reception, in the processor 1, Layer 2 or more data of the received address field and bits analysis, when the paging channel of the receiver address field and bit analysis is shortened mobile station identifier, and the identifier if there is a mobile station identifier When the mobile station identifier matches the mobile station identifier of the own mobile station, the processor 2 is activated only at those times.

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