JP4406519B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device suitable for high speed and low voltage operation.
[0002]
[Prior art]
MOS transistors having characteristics of high integration and low power consumption (in the present specification, the word MOS transistor is used to represent an insulated gate field effect transistor) are widely used in semiconductor integrated circuit devices. ing. The on / off characteristics of the MOS transistor are determined by the threshold voltage of the MOS transistor. In order to increase the drive capability and improve the operation speed of the circuit, the threshold voltage must be set low.
[0003]
However, 1993 Symposium on VLSI Circuits Digest of Technical Papers, pp45-46 (May 1993) If the threshold voltage is set too low, the transistor cannot be completely turned off due to the subthreshold characteristic (tailing characteristic) of the MOS transistor. Therefore, there is a problem that subthreshold leakage current (hereinafter referred to as leakage current) increases and the power consumption of the semiconductor integrated circuit becomes very large.
[0004]
Therefore, when designing a semiconductor integrated circuit device composed of MOS transistors, the threshold voltage of the MOS transistor is determined in consideration of the desired operating frequency and power consumption, and the semiconductor manufacturing process conditions are determined. Yes.
[0005]
In Japanese Patent Application Laid-Open No. 11-195976 (prior art), the operation speed of a plurality of signal paths in a semiconductor integrated circuit device is slow in a path having a sufficient delay (time for signal transmission along the signal path). High-threshold voltage MOS transistors with a small leakage current are frequently used. Conversely, in a path with no delay, a large number of low-threshold voltage MOS transistors with a high leakage current are used. The configuration is stated. Furthermore, in order to design a semiconductor integrated circuit in which a plurality of threshold voltage MOS transistors are mixed, a cell composed of a high threshold voltage MOS transistor and a low threshold voltage having the same logic function and shape. A method of designing by preparing both a cell constituted by a MOS transistor is disclosed.
[0006]
[Problems to be solved by the invention]
FIG. 10A shows a signal path including two flip-flops f101 and f102 and four logic gates g101 to g104. The clock signal CK is input to the flip-flops f101 and f102, and the circuit operates in synchronization therewith. Therefore, in order for this circuit to operate at the target operating frequency, the delay needs to be within the cycle time of the clock signal. In the prior art, when a circuit is configured with a gate composed of a MOS transistor with a high threshold voltage, if the delay exceeds the cycle time, it is partially replaced with a gate composed of a low threshold voltage MOS transistor. The leakage current is suppressed while realizing the target operating frequency. A thick part of the logic gate symbol indicates a gate composed of a MOS transistor having a high threshold voltage (this notation is also used hereinafter). In the example of FIG. 10A, the flip-flop f101 and the NAND gates g101 and g103 are composed of high threshold voltage MOS transistors, and the flip-flop f102 and the NAND gates g102 and g104 are low threshold voltage MOS transistors. It is configured. For example, the gate g101 is composed of a high threshold voltage PMOS transistor and NMOS transistor as shown in FIG. Further, as shown in FIG. 10C, the gate g102 is composed of a low threshold PMOS transistor and NMOS transistor. It is to be noted that the symbol of the MOS transistor also indicates that what is shown with a thick source and drain is a high threshold voltage MOS transistor (this notation is also used hereinafter). Here, the terms “low threshold MOS transistor” and “high threshold MOS transistor” in the present application are referred to as a low threshold MOS transistor. A MOS transistor having a relatively high absolute value of the threshold voltage is referred to as a high threshold MOS transistor. Further, the threshold voltage level due to manufacturing variations is not taken into consideration, and this is realized by intentionally changing design parameters and the like. Specifically, the threshold value of the MOS transistor is changed by changing the impurity node of the semiconductor substrate or well under the gate insulating film of the MOS transistor by means such as implantation, changing the dimension of the gate insulating film thickness, or changing the gate length. The voltage can be varied. It is also possible to vary the threshold voltage of the MOS transistor by applying a substrate bias to the substrate or well of the MOS transistor and changing the value of the substrate bias voltage.
[0007]
Here, in the prior art, it has not been sufficiently studied how to provide the threshold voltage of the individual transistors constituting the logic gate, in particular, the flip-flop circuit. That is, since the semiconductor integrated circuit is generally a synchronous circuit as shown in FIG. 10, the operating speed of the flip-flop circuit is important for operating at the target operating frequency. At this time, FIG. 11A in which all high threshold voltage MOS transistors are used as flip-flops using high threshold voltage MOS transistors is used as a flip-flop using low threshold voltage MOS transistors. Assume that FIG. 11C using all low threshold voltage MOS transistors is used. Note that tg 101 to 102 and tg 111 to 112 in the flip-flop are clocked inverter circuits that switch between a cut-off state and an inverted signal output by a clock signal CK (FIGS. 11B and 11D).
[0008]
However, the inventors have found that if the flip-flop is configured as shown in FIGS. 11 (a) and 11 (c), the increase in speed may be hindered.
[0009]
In the signal propagation path shown in FIG. 10A, data is output from the flip-flop f101 which is the starting point at the rising time of the clock signal CK, and the signal is output from the logic gates g101 to g104 by the rising time of the next clock signal. To the end-point flip-flop f102.
[0010]
In the start point flip-flop f101, when the clock signal CK is “0”, the transmission gate p101 is opened, and the input signal D is passed through the inverter circuit i101. At this time, the transmission gate p102 is closed, and the signal one clock before stored in the inverter circuit i103 and the clocked inverter circuit tg102 is output through the output inverter circuit i104. When the clock signal CK rises to “1”, the transmission gate p101 is closed to finish the signal capture, and the inverter circuit i102 and the clocked inverter circuit tg101 store the data. On the other hand, the transmission gate p102 is opened, and the captured data is output through the output buffer i104 when the clock signal is “0”. Therefore, the delay of the flip-flop f101 means that the clock signal CK rises and passes through the inverter circuits i105 to 106, opens the transmission gate p102, passes data through the transmission gate p102, and further passes through the output inverter circuit i104. It is the time required for That is, the gates that are effective in reducing the delay are the inverter circuits i105, i106, i104 and the transmission gate p102.
[0011]
Next, the end point flip-flop will be described. Of course, it is too late if the signal reaches the input pin D of the flip-flop f102 at the moment when the clock signal CK rises to "1". When the clock signal CK rises to “1”, the transmission gate p111 is closed by the clock signal that has passed through the inverter circuits i115 and i116. Therefore, data must be stored by the inverter circuit i113 and the clocked inverter circuit tg112 unless the data signal has passed through the inverter circuit i111, the transmission gate p111, and the inverter circuit i112 before the transmission gate p111 is closed. Can not be. That is, the time when the signal arrives at the signal input pin D of the flip-flop f102 needs to reach with a margin time from the time when the clock signal CK rises to “1”. This extra time is usually called setup time. The gates effective for reducing the setup time are inverter circuits i111 and i112 and a transmission gate p111. Conversely, if the inverter circuits i115 and i116 through which the clock signal CK passes as shown in FIG. 11C are configured by low threshold MOS transistors, the time for closing the transmission gate p111 is advanced, which means that the setup time is reduced. Will lead to a larger.
[0012]
As described above, in a circuit that receives a clock signal and a data signal such as a flip-flop, it is low even for a MOS transistor that does not contribute to speeding up to constitute a circuit by using low threshold MOS transistors uniformly. Use of the threshold MOS transistor may increase power consumption.
[0013]
[Means for Solving the Problems]
In order to operate the flip-flop at a high speed, only the MOS transistor having the effect of shortening the delay among the MOS transistors in the flip-flop cell is set to the low threshold, and the MOS transistor having no effect on the delay shortening is set to the high threshold. It is to make.
[0014]
A first logic gate having a data input node and an output node, to which at least data input from the data input node is input, and a latch for holding the data, between the data input node and the output node; And a threshold voltage (absolute value) V1 of the first conductivity type first MOS transistor included in the first logic gate and a threshold value of the first conductivity type second MOS transistor included in the latch. The voltage (absolute value) V2 is configured to satisfy the relationship V2> V1. Here, the relationship of V2> V1 does not include an accidental process due to process variation, and is realized by a predetermined process or the like.
[0015]
In particular, the high threshold MOS transistor and the low threshold MOS transistor are the same transistors as the high threshold MOS transistor and the low threshold MOS transistor used in the logic circuit.
[0016]
That is, the first logic gate includes a data input node and an output node, and includes a first logic gate to which at least data input from the data input node is input and a latch for holding data between the data input node and the output node. A flip-flop; a second flip-flop having a data input node; and a logic circuit connected to the output node of the first flip-flop and the data input node of the second flip-flop. A first flip-flop including a first conductivity type first MOS transistor having (absolute value) V1 and a first conductivity type second MOS transistor having a threshold voltage (absolute value) V2 greater than the threshold voltage V1; The threshold voltage (absolute value) V3 of the first-conductivity-type third MOS transistor constituting the first logic gate is (V3 The absolute value of the difference between V2)> (the absolute value of the difference between V3 and V1) is satisfied, and the latch of the first flip-flop includes a fourth MOS transistor of the first conductivity type, and a threshold value of the fourth MOS transistor. The voltage (absolute value) V4 is configured to satisfy the relationship of (absolute value of difference between V4 and V1)> (absolute value of difference between V4 and V2).
[0017]
Further, when the flip-flop circuit includes a circuit portion that operates only during the test, a high threshold MOS transistor is used for such a circuit portion.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
As shown in FIGS. 10A to 10C, the logic circuit to which the present invention is applied is a MOS transistor having at least two types of threshold voltages for both the logic gate and the flip-flop constituting the logic circuit. It is configured using.
(First embodiment)
The circuit of FIG. 1A is an application of the present invention to a level sensitive latch. The circuit shown in FIG. 1A is used as a latch that requires high-speed operation. The latch l11 is an inverter circuit i11 that drives an input signal, i12 that drives an output, an inverter circuit i13 (i14) that inputs a clock signal and drives a clock signal (clock inverted signal), and the clock signal CK is “1”. In order to hold data when the transmission gate p11 that is sometimes open and allows data to pass and the transmission gate p11 is in the closed state, it is composed of an inverter circuit i15 and a clocked inverter circuit tg11 that are connected to each other. The transmission gate p11 is a pass transistor in which the sources and drains of the PMOS transistor and the NMOS transistor are connected to each other. FIG. 1B also shows the transistor configuration of the clocked inverter circuit tg11. The clocked inverter tg11 has a configuration in which PMOS transistors TP11 and TP12 which are vertically stacked in two stages and NMOS transistors TN11 and TN12 which are vertically stacked in two stages are connected in series. The input data signal in1, the clock signal CK and the clock inverted signal CK / are input. When the clock signal CK is “1”, the inverted signal ont1 of the input signal in1 is output, and when the clock signal CK is “0” It will be cut off.
[0019]
As described above, the latch l11 is called an active high latch because it allows data to pass only when the clock signal CK is “1”. The propagation path of the data signal in this latch is the inverter circuit i11, the transmission gate p11, and the inverter circuit i12. If the MOS transistor of the gate on this path is set to a low threshold value, it contributes to shortening the delay of the latch. To do.
[0020]
On the other hand, the delay reduction effect of the gate located in the clock signal propagation path is as follows. When the data signal arrives before the clock becomes “1”, the delay time is shortened because the transmission gate p11 can be opened quickly by setting the clock signal driving inverter circuits i13 and i14 to a low threshold. There is an effect. On the other hand, in the case where the clock signal is “1” faster than the data signal, the clock signal driving inverter circuits i13 and i14 do not contribute to the delay reduction of the latch at all.
[0021]
Therefore, it is most effective to lower the threshold value of the inverter circuit i11, the transmission gate p11, and the inverter circuit i12, which are effective in reducing the delay in all states. Here, since the MOS transistor used for the latch and the other MOS transistor used for the logic gate are common, the low threshold MOS transistor of the logic gate is used as the low threshold MOS transistor of the latch, and the high threshold of the latch is used. A high threshold MOS transistor having a logic gate may be used as the MOS transistor. Therefore, in the high threshold MOS transistor of the latch, the absolute value of the difference between the absolute value of the threshold voltage and the absolute value of the threshold voltage of the low threshold MOS transistor used for the other logic gate is The absolute value of the difference between the absolute value of the threshold voltage and the absolute value of the threshold voltage of the high threshold MOS transistor used for the other logic gates becomes larger. On the other hand, in the low threshold MOS transistor of the latch, the absolute value of the difference between the absolute value of the threshold voltage and the absolute value of the threshold voltage of the high threshold MOS transistor used for other logic gates is The absolute value of the difference between the absolute value of the threshold voltage and the absolute value of the threshold voltage of the low threshold MOS transistor used for the other logic gates is larger.
[0022]
In the case where a MOS transistor having three or more threshold voltages is used in the logic gate, the relative threshold value shown in FIG. The voltage may be selected and used so as to satisfy the voltage relationship.
[0023]
With the configuration shown in FIG. 1A, it is possible to achieve the same high speed by using less threshold MOS transistors than when all the transistors are lowered in threshold. In the latch example of FIG. 1A, the number of low threshold MOS transistors is six out of the total 16 transistors. As a result, the leakage current can be reduced to about half as compared with the case where all are constituted by low threshold MOS transistors. On the other hand, a latch that does not require high-speed operation may be configured by replacing the low threshold MOS transistor with a high threshold MOS transistor. This is the same for each circuit shown below.
[0024]
1 shows an active high latch that allows data to pass when the clock signal becomes 1, but an active low latch that allows data to pass when the clock signal is 0 is similarly raised or lowered. It is possible to configure by using different threshold voltages.
[0025]
The circuit in FIG. 2 is a modification of the circuit in FIG. In order to store data, a transmission gate p22 is used instead of the clocked inverter circuit tg11. 1 operates in the same manner as in FIG. In order to hold data when the transmission gate p21 is in the closed state, inverter circuits i25 and i26 and a transmission gate p22 are provided. The transmission gate p22 is in an open state to hold data when the transmission gate p21 is closed, and conversely is closed when the transmission gate p21 is open. As in the configuration example of FIG. 1, the propagation path of the data signal in this latch is the inverter circuit i21, the transmission gate p21, and the inverter circuit i22. When the MOS transistor of the gate on this path is set to a low threshold value, This contributes to shortening the latch delay.
[0026]
The circuit of FIG. 3A is an example in which the present invention is applied to an edge trigger type master-slave flip-flop. When the clock signal CK is “0”, the transmission gate p31 is opened, and the input signal D is passed through the inverter circuit i31. At this time, the transmission gate p32 is closed, and the signal one clock before stored in the inverter circuit i33 and the clocked inverter circuit tg32 is output through the output inverter circuit i34.
[0027]
At the moment when the clock signal CK rises to “1”, the transmission gate p32 is closed to finish the signal capture, and the inverter circuit i32 and the clocked inverter circuit tg31 store the data. At this time, the transmission gate p32 is opened, and the captured data is output through the output inverter circuit i34 when the clock is “0”.
[0028]
The delay when the flip-flop f31 is at the start point of the signal propagation path means that the clock signal CK rises, the clock signal that has passed through the inverter circuits i35 and i36 opens the transmission gate p32, and the data passes through the transmission gate p32. Further, this is the time required to pass through the output inverter circuit i34. From the above, when the flip-flop is at the starting point of the path, the inverter circuits i34, i35, i36 and the transmission gate p32 are effective in reducing the delay.
[0029]
On the other hand, when the flip-flop f31 is at the end point of the signal propagation path, the setup time of the flip-flop is added to the delay of the path. That is, before the clock signal CK is input and passes through the inverter circuits i35 and i36 and the transmission gate p31 is closed, the data signal needs to pass through the inverter circuit i31, the transmission gate p31, and the inverter circuit i32. Therefore, in order to reduce the setup time, it is desirable to use low threshold MOS transistors for the inverter circuits i31 and i32 and the transmission gate p31.
[0030]
Here, when the inverter circuits i35 and i36 are configured by using low threshold MOS transistors, it is effective in reducing delay when positioned at the start point, but the transmission gate p21 is closed when positioned at the end point. On the contrary, the setup time is increased in order to reduce the time until the time. Therefore, regardless of whether the flip-flop is present at the start point or the end point of the signal propagation path, the gate that is effective in reducing the delay of the path passes for the data signal to be input and output from the output terminal. Inverter circuits i31, i32, i34 and transmission gates p31, p32 located on the path.
[0031]
Since the inverter circuit i3 and the clocked inverter circuits tg31 and tg32 do not affect the speeding up, it is desirable to configure them with high threshold MOS transistors. Although the effects of the inverter circuits i35 and i36 differ depending on the start point and the end point, a configuration that can reduce the setup time is shown in FIG.
[0032]
FIG. 4 is a modification of the circuit of FIG. The clocked inverters tg31 and tg32 are respectively replaced with an inverter circuit i47 and a transmission gate p43, an inverter circuit i48 and a transmission gate p44.
(Second Embodiment)
An example in which the flip-flop using a part of the low threshold MOS transistors and the flip-flop using all the high threshold MOS transistors described in FIG. Shown in a). FIG. 5A shows three signal propagation paths from the start point flip-flop to the end point flip-flop. In FIG. 5A, the logic gates between the flip-flops are all illustrated as NAND, but in actuality, they are configured by various logic gates such as AND and OR. The first signal propagation path is a path including a flip-flop f51 as a start point, a flip-flop f52 as an end point, and two logic gates therebetween. The second signal propagation path is a path including the flip-flop f53 as the start point, the flip-flop f54 as the end point, and four logic gates therebetween. The third signal propagation path is a path including a flip-flop f55 as a start point, a flip-flop f56 as an end point, and six logic gates therebetween. Unless the delays of the three signal propagation paths are all suppressed within the cycle time, the logic circuit cannot operate at the clock frequency.
[0033]
Since the first path has a small number of logic gates and a sufficient delay, all the logic gates and the flip-flops f51 and f52 at the start and end points are only cells composed of high threshold voltage MOS transistors and have a cycle time or less. Delay can be realized. However, in the second signal propagation path, the number of stages is increased, and when a cell composed of high threshold voltage MOS transistors is used, the delay exceeds the cycle time. Therefore, a cell composed of only two of the four logic gates is used as a low threshold voltage MOS transistor, and a cell using a low threshold voltage MOS transistor is also used as the starting flip-flop f53. Since the third signal propagation path has a larger number of stages, cells in which all the logic gates are composed of low-threshold MOS transistors are used, and the thresholds of the start-point flip-flop f55 and the end-point flip-flop f56 are also low. A cell using a value MOS transistor is used. FIG. 5B is a configuration example of an internal circuit of the high threshold flip-flop used in the flip-flops f51, f52, and f53. The low threshold flip-flops used in the flip-flops f54, f55, and f56 can use the configuration examples shown in FIGS.
(Third embodiment)
In order to assure the quality of the semiconductor device, a test is performed after its manufacture. A so-called flip-flop with a scan circuit is used in order to perform a comprehensive test for operating logic gates in a semiconductor device. An example of this is shown in FIG. In addition to the signal propagation paths (f61, f62) and (f63, f64) during normal operation, for example, a scan path z61 is provided between the flip-flop f61 and the flip-flop f64. During the test, the test data input node Sin is selected by the scan enable Se, and the test data is set in each flip-flop via the scan path (the operation for setting the test data in this way is called a scan operation). Since the scan operation is generally performed at a lower frequency than the normal operation, the circuit for the scan operation is not required to have high speed. Therefore, the test circuit portion that does not contribute to the speeding up of the flip-flop with the scan circuit during the normal operation can be composed of a high threshold MOS transistor.
[0034]
FIG. 6B shows the configuration of the MUX scan flip-prop f61. The MUX scan flip-flop is composed of a data input node D for receiving a data signal during normal operation and a test data input node Sin for receiving test data input by transmission gates p63 and p64 according to the value of the scan enable signal Se. A function of selecting by a multiplexer is provided. That is, when the scan enable signal Se is “1”, the transmission gate p63 is closed while the transmission gate p64 is opened, and the test data Sin is taken in. Conversely, when the scan enable signal Se is “0”, the transmission gate p64 is closed while the transmission gate p63 is opened, and the data signal D is captured. Therefore, the scan enable signal Se is fixed to 0 during normal operation.
[0035]
Therefore, the inverter circuit i67 that drives the test data, the inverter circuit i68 that generates the inverted signal of the scan enable signal, and the transmission gate p64 that passes and blocks the test data are configured using high threshold MOS transistors. As a result, the leakage current can be reduced by setting the MOS transistor that operates only during the scan operation and does not contribute to the normal speed increase to a high threshold.
[0036]
The latch 171 in FIG. 7 is called a shift register latch, and has a structure in which data can be sequentially set during a test by connecting the shift register latches in the semiconductor integrated circuit in series. The shift register latch l71 is a combination of two latches lp71 and lp72. In the normal operation mode, the internal latch lp71 operates as a normal latch by fixing both shift clocks SCK1 and SCK2 to “0”. Among the gates constituting the latch lp71, the inverter circuit i71 and the four NAND gates g70 to g73 actually operate during normal operation. During the normal operation, the inverter circuit i72, the two NAND gates g74 and g75, and the four NAND gates g76 to g79 do not operate.
[0037]
In this configuration example, the inverter circuit i71 and the four NAND gates g70 to g73, which are logic gates contributing to high speed during normal operation, are configured by low threshold MOS transistors, and the other gates are high thresholds. It is composed of MOS transistors.
(Fourth embodiment)
It is desirable to use a high-threshold MOS transistor for a circuit portion that does not contribute to speeding up the entire semiconductor integrated circuit. FIG. 8 shows a semiconductor integrated circuit c81 using a high threshold MOS transistor as a clock signal driver. FIG. 8 schematically shows how the clock signal is distributed. A clock signal from a clock driver in the center of the chip is hierarchically distributed to the entire chip through H-type wiring. A clock signal is distributed from the first-stage clock driver AD1 to the second-stage clock driver groups BD1 to BD4, and a clock signal is distributed from the second-stage clock driver BD1 to the third-stage clock driver groups CD1 to CD4. . The clock distribution after the third stage clock driver is omitted in the figure. A clock signal is supplied from a third-stage clock driver group to flip-flops (shown as rectangles in the figure) arranged on the entire surface of the chip. In the figure, a rectangle with a thick solid line is a flip-flop composed of all high-threshold MOS transistors as shown in FIG. 5B, and the other rectangles are shown in FIG. 3A and FIG. 6B. This is the flip-flop described in relation to the above. As described above, the high threshold voltage flip-flop and the two threshold voltage mixed flip-flops are mixedly used as necessary. In the example of FIG. 8, as shown in the first to third embodiments, the gate that drives the clock signal has little contribution to the high speed even in the flip-flop that requires high speed. A MOS transistor is used. For the same reason, it is desirable that the driver groups AD, BD, and CD for distributing the clock signal to the entire chip are composed of high threshold MOS transistors.
[0038]
FIG. 9 shows an example in which the present invention is applied to a microprocessor. The building blocks are: CPU (central processing unit), FPU (floating point arithmetic unit), CACHE (built-in memory), BSC (bus control circuit), DMAC (direct memory access control circuit), INT (interrupt control circuit), BIST ( Build-in self-test circuit). The cells constituting the building block are represented by rectangles. Among the cells in each block, the shaded cells are high threshold MOS transistors, and the open cells are low threshold MOS transistors. Here too, the low threshold cell of the flip-flop cell is a flip-flop in which two types of threshold voltage MOS transistors using high threshold MOS transistors are mixed in a portion that does not contribute to speeding up.
[0039]
For example, it can be seen that the processor CPU, FPU (arithmetic circuit) and built-in memory (memory peripheral circuit such as a decoder circuit) having many critical paths with no delay have a large number of low threshold voltage cells. . In addition, the control circuit (BSC, DMAC, INT) having a sufficient delay has a small percentage of cells having a low threshold voltage. Furthermore, the test control circuit (BIST or the like) that operates only in the test mode and does not operate in the normal operation is composed of high threshold voltage cells. As described above, according to the present invention, it is possible to appropriately use a low threshold MOS transistor and a high threshold MOS transistor as needed, and to minimize the use of a low threshold MOS transistor. Realizes high speed operation and low power consumption at the same time.
[0040]
The present invention realizes a high-speed operation and a low leakage current when active. In addition to this, it is possible to combine a known technique for raising the threshold value by controlling the substrate bias power supply during standby or a known technique for cutting off the power supply to the main circuit by the power switch.
[0041]
【The invention's effect】
Without sacrificing the speed at the time of active operation of the semiconductor integrated circuit device, it is possible to reduce the usage ratio of the low threshold MOS transistor and suppress the leakage current.
[Brief description of the drawings]
FIG. 1 (a) is a circuit diagram of a latch circuit of the present invention, and FIG. 1 (b) is a circuit diagram of a clocked inverter thereof.
FIG. 2 is a circuit diagram showing another configuration example of the latch circuit of the present invention.
3A is a circuit diagram of the flip-flop circuit of the present invention, and FIG. 3B is a circuit diagram of the clocked inverter.
FIG. 4 is a circuit diagram showing another configuration example of the flip-flop circuit of the present invention.
5A is a diagram of a logic circuit, and FIG. 5B is a circuit diagram of a high threshold flip-flop circuit.
6A is a diagram of a logic circuit having a scan path, and FIG. 6B is a circuit diagram of a flip-flop circuit with scan.
FIG. 7 is a circuit diagram of a shift register latch circuit of the present invention.
FIG. 8 is a diagram showing a semiconductor integrated circuit device.
FIG. 9 is a diagram illustrating a microcomputer.
10A is a diagram of a logic circuit, FIG. 10B is a logic gate composed of high threshold MOS transistors, and FIG. 10C is a low threshold MOS transistor. It is a configured logic gate.
FIG. 11A is a circuit diagram of a flip-flop composed only of a high threshold MOS transistor, FIG. 11B is a circuit diagram of the clocked inverter, and FIG. FIG. 11D is a circuit diagram of a flip-flop composed only of a low threshold MOS transistor, and FIG. 11D is a circuit diagram of the clocked inverter.
[Explanation of symbols]
i ... inverter circuit, tg ... clocked inverter circuit, p ... transmission gate, TP ... PMOS transistor, TN ... NMOS transistor, l ... ... Latch circuit, f ... Flip-flop circuit, g ... Logic gate, AD, BD, CD ... Clock driver circuit, C81 ... Semiconductor integrated circuit device, C91: Microprocessor.

Claims (9)

A first flip-flop including a plurality of logic gates,
A second flip-flop;
And a logic circuit and input node of the output node and said second flip-flop of the first flip-flop is connected,
It said logic circuit includes a first of a first conductivity type having a threshold voltage V 2 is also greater absolute value than the 1MOS transistor and the threshold voltage V1 of the first conductivity type having a threshold voltage V 1 Including 2MOS transistors,
Threshold voltage V 3 of M OS transistor of the first conductivity type constituting the logical gate disposed on the propagation path of the data signal to the output node from the data input node of the first flip-flop, (Absolute value of difference between V3 and V2)> (Absolute value of difference between V3 and V1)
Threshold voltage V 4 of the first conductivity type MOS transistors constituting the logic gate which is arranged in addition to on the propagation path, the (absolute value of the difference between V4 and V1)> (V4 and difference V2 the semiconductor integrated circuit device that meets the relationship of absolute value). In claim 1,
Said logic circuit, said first 1MOS are transistors connected in series, the 3 MOS transistors of a second conductivity type having a threshold voltage V 5, and are connected the first 2MOS transistor in series, the threshold voltage V5 includes a first 6MOS transistor of a second conductivity type having a threshold voltage V 6 absolute value is greater than,
Threshold voltage V 7 of the M OS transistor of the second conductivity type constituting the upper Symbol logical gates are arranged from the data input node of the first flip-flop on the propagation path of the data signal to the output node , (The absolute value of the difference between V7 and V6)> (the absolute value of the difference between V7 and V5)
A second conductivity type in the threshold voltage V 8 of the M OS transistor constituting the logic gates are arranged in addition to on the propagation path (absolute value of the difference V8 and V5)> (V8 and the V6 A semiconductor integrated circuit device that satisfies the relationship (absolute value of difference). In claim 2,
The latches of the first flip-flop, said a first node located between said data input node and the output node of the first flip-flop, a first inverter input to the first node is connected If the input unit is connected to the output of the first inverter, a semiconductor integrated circuit device which have a second inverter having an output portion connected to said first node. In claim 2,
The first flip-flop, the input unit is connected to the clock input nodes of the first flip-flop, a semiconductor integrated circuit device having a clock driver for controlling the operation timing of the above Symbol logical gates. In claim 1,
The semiconductor integrated circuit device one above Symbol logical gate of the first flip-flop is a transmission gate provided between said data input node and said output node. In claim 1,
One of the logic gates of said first flip-flop, which on SL test data input node or latte strike data is input,
A semiconductor integrated circuit device in which the test data is held in a latch of the first flip-flop. In claim 2,
One of the logic gates of said first flip-flop, which on SL test data input node or latte strike data is input,
A semiconductor integrated circuit device in which the test data is held in a latch of the first flip-flop. First to fourth flip-flop including a plurality of logic gates,
Is connected between the data input node of the output node and said second flip-flop of the first flip-flop, a first logic circuit including a plurality of logic gates,
Is connected between the data input node of said third output node of the flip-flop and the fourth flip-flop, a second logic circuit including a logical gate of multiple,
The number of logic gates of the first logic circuit is greater than the number of logic gates of the second logic circuit,
Logic gates of the first logic circuit includes a first 1MOS transistor of a first conductivity type having a threshold voltage V 1,
Logic gates of the second logic circuit includes a first 2MOS transistor of a first conductivity type having a threshold voltage V 2 is also greater absolute value than the threshold voltage V1,
In at least one of said first flip-flop and the second flip-flop, the first conductivity type constituting the upper Symbol logical gate disposed on the propagation path of the data signal from the data input node to the output node M OS threshold voltage V 3 of the transistor, the (absolute value of the difference between V3 and V2)> satisfies the relationship (V3 and the absolute value of the difference between V1), said logic gates being arranged in addition to on the propagation path threshold voltage V 4 of the 4MOS transistor of the first conductivity type constituting the, (V4 and the absolute value of the difference between V1)> semiconductor integrated circuit device that meets the relationship of (V4 and absolute value of the difference between V2) . In claim 8 ,
Logic gates of the first logic circuit is connected the first 1MOS transistor in series, includes a first 3 MOS transistor of a second conductivity type having a threshold voltage V5,
Said logic gate of the second logic circuit is connected the first 2MOS transistor in series, the first 4 MOS transistor of a second conductivity type having a threshold voltage V6 absolute value is greater than the threshold voltage V 5 Including
Second conductive type fifth MOS transistor constituting the logic gate arranged on the data signal propagation path from the data input node to the output node in at least one of the first flip-flop and the second flip-flop the threshold voltage V7 of, (absolute value of the difference between V 7 and V 6)> satisfy the relationship of (an absolute value of the difference between V 7 and V 5), said logic being arranged in addition to on the propagation path the second threshold voltage of the conductivity type second 6 MOS transistor V8 constituting the gate, the relationship of (an absolute value of the difference of V 8 and V 5)> (the absolute value of the difference of V 8 and V 6) Filled semiconductor integrated circuit device.

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