JP4399399B2 - Signal amplification circuit and optical receiving circuit - Google Patents

Description

  The present invention relates to a signal amplifier circuit and an optical receiver circuit.

  In order to respond to the explosive increase in data traffic represented by the Internet, the construction of high-speed and large-capacity broadband optical access networks is rapidly progressing. As a high-speed optical access system, GE-PON (Gigabit Ethernet-Passive Optical Network) that realizes high-speed transmission of up to 1Gbps and shares an optical fiber network from a subscriber to a station building is optimal.

  FIG. 11 is a diagram showing an optical communication network 100 configured as the above-described GE-PON. In the network 100 shown in FIG. 11, a station side device (OLT: Optical Line Terminal) 101 includes N subscriber devices (ONU: Optical Network Unit) 102-1 via transmission paths 103-1 to 103-N. -102-N. The transmission path 103-i corresponding to each subscriber unit 102-i (i: 1 to N) is an optical fiber 103a, a branch coupler 103b, and an optical fiber 103c-i corresponding to each subscriber unit 102-i. Is configured.

  In the network 100 shown in FIG. 11, a time domain multiple access (TDMA) system is adopted for uplink transmission from the subscriber apparatuses 102-1 to 102-N to the station-side apparatus 101. That is, each of the subscriber devices 102-1 to 102-N transmits a packet in the time slot assigned by each of the subscriber devices 102-1 to 102-N through the transmission paths 103-1 to 103-N. Thus, time division multiplexing is realized.

  Here, according to the positional relationship between the place where the subscriber apparatuses 102-1 to 102-N are installed and the place where the station apparatus 101 is installed, each of the subscriber apparatuses 102-1 to 102-N and the station side. The distances of the transmission paths 103-1 to 103-N with the apparatus 101 are different. Therefore, the transmission loss of each of the transmission paths 103-1 to 103 -N may vary, and the dynamic range due to the transmission loss difference may reach 30 dB (1000 times).

  That is, since the optical packets from the subscriber apparatuses 102-1 to 102-N are transmitted to the station side apparatus 101 through the transmission paths 103-1 to 103-N having such a transmission loss difference, the station side apparatus The reception level at 101 may also vary. On the other hand, by setting a guard time of, for example, several tens to several hundreds ns between the time slots when transmitting the optical packet by the time division multiplexing described above, the reception level as described above in the packet reception in the station side device 101 is set. To avoid being affected by variations in

  That is, while the guard time is set so that the optical packets from the subscriber units 102-1 to 102-N are transmitted as burst optical signals, the station side device 101 has a guard time between time slots. The operation environment corresponding to the reception level of the optical signal from the subscriber apparatuses 102-1 to 102-N assigned to the next time slot is arranged.

  In the station-side device 101 that constitutes such an optical network 100, each of the subscriber devices 102-1 to 102-N is improved in order to improve the communication capability from the subscriber devices 102-1 to 102-N to the station-side device 101. Realization of a function for instantaneously determining optical packets (burst optical signals) having greatly different levels is required. At the same time, in order to spread the optical access system, it is important to realize an optical receiving circuit having the above functions with a simple and cost-effective configuration.

  FIG. 12 is a diagram showing an optical receiving circuit 110 provided in the conventional station apparatus 101 for receiving and determining an optical packet. Also in Patent Document 1, a configuration equivalent to the optical receiving circuit 110 shown in FIG. 12 is described. In the optical receiver circuit 110 shown in FIG. 12, a photodiode 111 that receives time-division multiplexed burst optical signals from the subscriber units 102-1 to 102-N and outputs an electrical signal corresponding to the received light level. A preamplifier 112 that amplifies an electric signal from the diode 111 and a differential amplifier circuit 113 that performs differential amplification on the electric signal from the preamplifier 112 (see FIG. 13A) are provided.

  The differential amplifier circuit unit 113 includes a peak detection circuit 113a, a bottom detection circuit 113b, a voltage dividing circuit 113c, a differential amplifier 113d, and a reset circuit 113e. The peak detection circuit 113a and the bottom detection circuit 113b are provided with amplifiers 113a-1 and 113b-1 and capacitors 113a-2 and 113b-2, respectively, and the peak (maximum) level and bottom (minimum) of the electric signal from the preamplifier 112 are provided. The level is detected (see FIG. 13B). The voltage dividing circuit 113c includes resistors 113c-1 and 113c-2, and generates an electric signal corresponding to an intermediate value between the peak level and the bottom level detected by the peak detecting circuit 113a and the bottom detecting circuit 113b by dividing the voltage.

The differential amplifier 113d outputs a signal having a level corresponding to the difference between the electrical signal from the preamplifier 112 and the electrical signal generated by the voltage dividing circuit 113c and corresponding to an intermediate value between the peak level and the bottom level. To do. This shortens the time required for signal identification when the optical signals on the subscriber units 102-1 to 102-N rise.
At this time, the reset circuit 113e receives a signal for generating a reset signal from the outside, generates a reset signal at the timing of the guard time between packets, and outputs it to the peak / bottom detection circuits 113a and 113b. The peak / bottom detection circuits 113a and 113b receive the reset signal from the reset circuit 113e and initialize the held peak level and bottom level (see t1 and t2 in FIG. 13C).

  By initializing the peak level and the bottom level held in the peak / bottom detection circuits 113a and 113b by such a reset signal, the signal levels from the subscriber units 102-1 to 102-N shown in FIG. Signal identification corresponding to the difference (see FIG. 13A) can be performed, and the optical signal reception levels from the subscriber units 102-1 to 102-N assigned to the next time slot The operating environment corresponding to can be prepared.

In addition, as a technique related to the present invention, there are techniques described in Patent Documents 2 and 3 below.
JP-A-6-310967 JP 2003-332988 A JP 2000-115218 A

  However, in the above-described technique shown in FIG. 12, since initialization is performed using a reset signal, the initialization time can be effectively reduced, but the station side device can perform reset synchronized with the timing of the guard time between packets. A signal needs to be generated. The time slot set as the transmission timing from the subscriber unit is required to have a variable length according to each subscriber unit. Since the transmission timing management becomes complicated, the function for generating the reset signal is also more complicated than in the case of the fixed length.

In addition to the circuit configuration for generating such a reset signal, providing the configuration for resetting the value held by the above-described reset signal in the peak / bottom detection circuits 113a and 113b There is a problem of increasing the scale and cost.
The techniques described in Patent Documents 2 and 3 also generate the reset signal as described above, and have the same problem.

  The present invention has been made in view of such problems, and an object thereof is to enable an optical burst signal to be received with high accuracy and stability without using a reset signal.

Thus, the signal amplifier circuit of the present invention is to detect the peak level of the input electric signal, a peak detection holding circuit that holds the charging of the peak level first capacitive element, the input electrical signal both the the bottom detection holding circuit for the bottom level held by the charge of the second capacitive element, the peak level and the bottom held respectively by said peak detection holding circuit and the bottom detection holding circuit for detecting a bottom level of and divided by a threshold from the level, a differential amplifier circuit for differentially amplifying the said input electrical signal, a reference signal having a voltage corresponding to the voltage of the input electric signal, said first capacitive element and said A level release circuit that supplies the two capacitive elements through the first resistance element and the second resistance element, respectively, and the input electrical signal is a signal in which a plurality of electrical signals are time-division multiplexed. , When said input electric signal is at the level of the no-signal charges held respectively in said first capacitive element and said second capacitor element, through said first and second resistive elements, respectively the A first discharge time constant due to the first capacitance element and the first resistance element and a second discharge time constant due to the second capacitance element and the second resistance element are discharged by the level release circuit . The input electrical signal is shorter than the time division multiplexing guard time and longer than the same level continuous time in the plurality of electrical signals .

Furthermore, the signal amplification circuit of the present invention is a signal amplification circuit for a differential input signal based on a level difference between a first electrical signal that conducts a first signal line and a second electrical signal that conducts a second signal line , A peak level of the electric signal level in the first signal line is detected, a first peak detection holding circuit for holding the peak level by charging the first capacitor element is provided, and an electric signal level in the second signal line is detected. A second peak detection holding circuit for detecting the peak level and holding the peak level by charging the second capacitor element is provided, and an electric signal from the first signal line is held by the second peak detection holding circuit. A first addition circuit for adding the peak level being held, and a second addition for adding the peak level held by the first peak detection holding circuit to the electrical signal from the second signal line. And the circuit, first, a differential amplifier for differentially amplifying the respective addition results from the second addition circuit, a reference signal of a voltage corresponding to the voltage of the first and second electrical signals, respectively, the A level release circuit is provided to supply the first capacitive element and the second capacitive element through the first resistive element and the second resistive element, and the differential input signal is time-division multiplexed with a plurality of electrical signals. and a signal, said when the differential input signal is at the level of the no-signal charges held respectively in the capacitor element and the second capacitive element of said 1, wherein the first and second resistive element Are discharged by the level release circuit, respectively, and a first discharge time constant by the first capacitor element and the first resistor element, and a second discharge time by the second capacitor element and the second resistor element. The discharge time constant of the input electric signal Shorter than division multiplexing of guard time, and is characterized by longer than the same level continuous time in the plurality of electric signals.

The optical receiver circuit of the present invention includes a photoelectric conversion element that converts an optical input signal into an electrical signal, a preamplifier circuit that amplifies the electrical signal, and a signal that amplifies the electrical signal amplified by the preamplifier circuit as an input signal. an optical receiver circuit includes an amplifier circuit, the signal amplifier circuit detects a peak level of the input electric signal, a peak detection holding circuit that holds the charging of the peak level first capacitive element When both detects a bottom level of the input electric signal, each hold the bottom level in the bottom detection holding circuit and, the peak detection holding circuit and the bottom detection holding circuit for holding the charging of the second capacitor element and divided by the threshold from the peak level and the bottom level is a differential amplifier circuit for differentially amplifying the said input electrical signal, to respond to the voltage of the input electric signal A level release circuit for supplying a voltage reference signal to the first capacitive element and the second capacitive element through the first resistive element and the second resistive element, respectively. When the electric signal is a time-division multiplexed signal and the input electric signal is at a no-signal level, the charges respectively held in the first capacitor element and the second capacitor element are And the second resistive element are discharged by the level release circuit, respectively, and a first discharge time constant by the first capacitive element and the first resistive element, the second capacitive element and the second resistive element The second discharge time constant by the resistance element is shorter than the guard time of the time division multiplexing of the input electric signal and longer than the same level continuous time of the plurality of electric signals .

  Thus, according to the present invention, in the level release circuit, when there is no input signal, the peak level and the bottom level held by the peak detection holding circuit and the bottom detection holding circuit can be released by discharging. Therefore, there is an advantage that an optical burst signal can be received with high accuracy and stability by a simple circuit configuration that does not use a reset signal.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In addition to the above-described object of the present invention, other technical problems, means for solving the technical problems, and operational effects thereof will become apparent from the disclosure of the following embodiments.
[A] Description of First Embodiment of the Invention FIG. 1 is a diagram showing an optical receiver circuit 10 to which a signal amplifier circuit 13 according to a first embodiment of the invention is applied. This signal amplifying circuit 13 can be applied to the optical receiving circuit in the station side device 101 in the network 100 shown in FIG. That is, as shown in FIG. 1, the optical receiver circuit 10 can be configured by providing the photodiode 11 and the preamplifier 12 together with the signal amplifier circuit 13.

  That is, in the optical receiving circuit 10, the photodiode 11 receives the time-division multiplexed optical burst signal from the subscriber unit (see reference numerals 102-1 to 102-N in FIG. 11) and amplifies it by the preamplifier 12. Further, the signal amplifying circuit 13 can amplify the signal according to the code that is data-modulated as the optical burst signal.

  Unlike the differential amplifier circuit unit 113 shown in FIG. 12, the signal amplifier circuit 13 is a subscriber unit 102-1 assigned to the next time slot forming the optical burst signal transmitted by time division multiplexing. Operation corresponding to the reception level of the optical signal from the subscriber units 102-1 to 102-N with a simple configuration that does not have a function of generating a reset signal in order to receive the optical signal from -102-N The environment can be prepared. The signal amplification circuit 13 shown in FIG. 1 includes a peak detection holding circuit 21, a bottom detection holding circuit 22, a differential amplification circuit 23, and a level release circuit 24.

  Here, the peak detection holding circuit 21 detects the peak level of the electric signal from the preamplifier 12 that forms the input signal, and holds the detected peak level by charging. The amplifier 21a, the rectifying diode 21b, the capacitance 21c (capacitance value Cp) and a buffer circuit 21d. That is, the peak level of the input signal can be detected and held by the voltage level obtained by charging the capacitor 21c. In other words, the capacitor 21c is a first voltage holding element that holds a peak level voltage.

The buffer circuit 21d is for blocking the charged electric charge in the capacitor 21c so as not to be discharged to the voltage dividing resistor 23a-1 described later, and can be constituted by, for example, a voltage follower circuit. .
The bottom detection holding circuit 22 detects the bottom level of the electrical signal from the preamplifier 12 that forms the input signal and holds the detected bottom level by charging. The amplifier 22a, the rectifying diode 22b, and the capacitor 22c (Capacitance value Cb) and a buffer circuit 22d. That is, the bottom level of the input signal can be detected and held by the voltage level obtained by charging the capacitor 22c. In other words, the capacitor 22c is a second voltage holding element that holds a bottom level voltage. The buffer circuit 22d is for blocking the charged electric charge in the capacitor 22c from being discharged to the voltage dividing resistor 23a-2 side described later.

Further, in the above-described peak detection holding circuit 21 and bottom detection holding circuit 22, the outputs of the diodes 21b and 22b are used as negative feedback inputs of the amplifiers 21a and 22a, and the outputs of the buffer circuits 21d and 22d are negative of the amplifiers 21a and 22a. The structure is not included in the return.
The differential amplifier circuit 23 differentially amplifies the input signal and this threshold value using the intermediate level between the peak level and the bottom level held by the peak detection holding circuit 21 and the bottom detection holding circuit 22 as a threshold value. Thus, a voltage dividing circuit 23a and a differential amplifier 23b are provided.

  The voltage dividing circuit 23a includes two voltage dividing resistors 23a-1 and 23a-2, and the peak level and bottom level voltage levels held by the above-described peak detection holding circuit 21 and bottom detection holding circuit 22 are determined. The voltage is divided to an intermediate voltage level. The divided voltage level is output to the differential amplifier 23b as the above-described threshold value. Thus, in the differential amplifier 23b, the electrical signal from the preamplifier 12 is used as the first input and the threshold voltage from the voltage dividing circuit 23a is used as the second input, and the electrical signal level and the threshold level from the preamplifier 12 are used. It is possible to output an electrical signal corresponding to the difference between the two as an output signal.

  Further, the level release circuit 24 sets the peak level and the bottom level held by the peak detection holding circuit 21 and the bottom detection holding circuit 22 to the no-signal level of the input signal when there is no input signal. It is released by discharge. That is, the level release circuit 24 calculates the peak level voltage and the bottom level voltage held by the peak detection holding circuit 21 and the bottom detection holding circuit 22 when there is no input signal, that is, during the guard time between time slots. It can be configured as a discharge circuit that discharges so that the input signal has a level voltage when there is no signal.

  Here, the level release circuit 24 as a discharge circuit is composed of a peak reference portion 24a, a bottom reference portion 24b, and resistors 24c and 24d. The peak reference unit 24a is configured as a first voltage applying unit that applies the same voltage as the input signal voltage for discharging the peak level voltage, and the bottom reference unit 24b applies the same voltage as the input signal voltage to the bottom level. The second voltage applying unit is provided for voltage discharge.

In the first embodiment, each of the peak reference unit 24a and the bottom reference unit 24b includes amplifiers 24aa and 24ab, and can be configured by a voltage follower circuit that uses an input signal voltage from the preamplifier 12 as an output side voltage. .
Further, a resistor (first resistor element, resistance value Rp) 24c connects the capacitor 21c and the peak reference portion 24a, and a resistor (second resistor element, resistor value Rb) 24d has a capacitor 22c. Is connected to the bottom reference portion 24b. Thereby, when the voltage level obtained by charging the capacitor 21c is different from the voltage applied to the peak reference unit 24a, the capacitor 21c is discharged through the resistor 24c, and the voltage of the capacitor 21c is changed to the peak reference. The voltage matches the voltage applied to the unit 24a.

Similarly, when the voltage level obtained by charging the capacitor 22c is different from the voltage applied to the bottom reference unit 24b, the capacitor 22c is discharged through the resistor 24d, and the voltage of the capacitor 22c is changed to the bottom reference unit. The voltage matches the voltage applied to the portion 24b.
FIGS. 2A and 2B are guard times between time slots when the reception allocation time in a time division from a subscriber device (not shown) is a time slot allocated for signal input. 6 is a diagram for explaining a change in the peak level voltage held in the peak detection holding circuit 21 in the case. FIG.

That is, in the case where the time allocated for reception from a subscriber unit (not shown) is a time slot assigned for signal input, the peak detection holding circuit 21 receives the input signal in the time slot [FIG. The peak level voltage at time t1, t3, t5 in a)] is maintained [see time t1, t3, t5 in FIG. 2B].
On the other hand, when the allocated time in the time division becomes a guard time, that is, a guard time provided between two time slots allocated for signal input, the peak reference unit 24a and the bottom reference unit 24b The applied voltage is at the level of no signal. At this time, for example, a difference occurs between the peak level voltage at the time slot immediately before being held in the peak detection holding circuit 21 and the voltage given by the peak reference unit 24a.

  In the level release circuit 24 as a discharge circuit, when the voltage difference occurs as described above, the charges charged in the capacitors 21c and 22c are spontaneously discharged through the resistors 24c and 24d. As a result, the peak level voltage and the bottom level voltage held by the peak detection holding circuit 21 and the bottom detection holding circuit 22 can be released without the need for a reset signal required in the case of the prior art. It is.

  The time required for discharging the peak level voltage held in the capacitor 21c is stably determined by the time constant τp = CpRp obtained by the value Cp of the capacitor 21c and the value Rp of the resistor 24c. Similarly, the time required for discharging the bottom level voltage held in the capacitor 22c is also stably determined by the time constant τb = CbRb obtained by the value Cb of the capacitor 22c and the value Rb of the resistor 24d.

  Further, the time τp, τb required for this discharge is shorter than the time T1 set as the guard time described above, and longer than the same sign continuous time T2 assumed to exist in one packet. In addition, the resistance values of the capacitors 21c and 22c and the resistors 24c and 24d are set as appropriate. These times τp and τb are preferably the same.

  In this way, even if the same code continues in one packet, it is not discharged as in the case of the guard time, so that the same code continuous pattern is followed by a different code pattern in the same packet. Also in the thing, the code can be identified without distinction. Further, when the guard time is reached, the capacities 21c and 22c can be surely discharged within the guard time, so that packets can be identified instantaneously and accurately in the subsequent time slot.

  For example, the bit rate of GE-PON is 1.25 Gbps, and the time per bit is 0.8 ns. Since the number of bits assumed to be the same code continuation in GE-PON is about 10 bits, the time T1 assumed to be the same code continuation is about 8 ns at the above bit rate. Furthermore, since the guard time T2 of the GE-PON can be set as 102.4 ns (128 bit time) to 409.6 ns (512 bit time), the above-described discharge time constants τp and τb are also like this. It is set to be larger than T1 and smaller than T2. Note that the shorter the guard time of GE-PON, the better the transmission efficiency.

  With the above-described configuration, in the first embodiment of the present invention, an electrical signal corresponding to the level change of the optical burst signal received by the photodiode 11 is amplified by the preamplifier 12 and input to the signal amplifier circuit 13. At this time, in the signal amplifying circuit 13, the peak detection holding circuit 21 detects and holds the peak level of the input signal, and the bottom detection holding circuit 22 detects and holds the bottom level of the input signal.

Then, in the differential amplifier circuit 23, by differentially amplifying the input signal and this threshold value with the peak level and bottom level held by the peak detection holding circuit 21 and the bottom detection holding circuit as threshold values, It can be output as a binary identification signal of a burst optical signal.
At this time, in the level release circuit 24, the peak level and the bottom level held by the peak detection holding circuit 21 and the bottom detection holding circuit can be stably discharged within the guard time, so that no reset signal is used. In addition, it is possible to identify the codes of optical burst signals having different amplitudes for each time slot without impairing the instantaneous start-up characteristics of the input signal.

  Thus, according to the first embodiment of the present invention, in the level release circuit 24, when there is no input signal, the peak level and the bottom level held by the peak detection holding circuit 21 and the bottom detection holding circuit 22 are set. Since the input signal can be released by discharging so as to be at the level of no signal, there is an advantage that an optical burst signal can be received with high accuracy and stability by a simple circuit configuration not using a reset signal.

That is, since a circuit configuration for generating a reset signal can be eliminated, there is an advantage that the device scale can be reduced and the cost for the device configuration can be reduced.
[B] Description of Second Embodiment FIG. 3 is a diagram showing an optical receiving circuit to which a signal amplifying circuit 13A according to a second embodiment of the present invention is applied. The signal amplifying circuit 13A according to the second embodiment includes the peak detection holding circuit 21A and the bottom detection holding circuit 22A, and the configuration of the peak reference unit 24Aa and the bottom reference unit 24Ab forming the level release circuit 24A is the same as that of the first embodiment. It is different from the case. The remaining configuration is basically the same as that of the first embodiment described above, and the same reference numerals in FIG. 3 as those in FIG.

  That is, in the peak detection holding circuit 21 and the bottom detection holding circuit 22 in the first embodiment described above, the outputs of the diodes 21b and 22b are the negative feedback inputs of the amplifiers 21a and 22a, respectively, and the outputs of the buffer circuits 21d and 22d are as follows. Are not included in the negative feedback of the amplifiers 21a and 22a. On the other hand, in the peak detection holding circuit 21A and the bottom detection holding circuit 22A in the second embodiment, the outputs of the buffer circuits 21d and 22d are used as negative feedback inputs of the amplifiers 21a and 22a.

  In the peak detection holding circuit 21 and the bottom detection holding circuit 22 of the first embodiment described above, there is a difference voltage ΔV between the voltage level obtained by charging the capacitors 21c and 22c and the output voltage of the buffer circuits 21d and 22d. A voltage follower circuit or the like was used so as not to occur. This difference voltage ΔV does not become 0 due to an input offset in the voltage follower circuit or the like forming the buffer circuits 21d and 22d, and causes a shift in the threshold voltage level.

  In the peak detection holding circuit 21A and the bottom detection holding circuit 22A in the second embodiment, the output voltages of the buffer circuits 21d and 22d are used as the negative feedback inputs of the amplifiers 21a and 22a. A shift in threshold voltage level due to the generation of the voltage ΔV can be suppressed. In this case, the buffer circuits 21d and 21c need to be excellent in high speed in order to ensure the stability of the negative feedback, and can be configured by, for example, a source follower circuit, an emitter follower circuit, or the like.

  Correspondingly, in the second embodiment, the peak reference unit 24Aa has a configuration corresponding to the configuration of the negative feedback circuit forming the peak detection holding circuit 21A. Specifically, the peak reference unit 24Aa includes an amplifier 24aa, a diode 24ba, a buffer circuit 24da, and a buffer circuit 24da corresponding to the fact that the peak detection holding circuit 21A includes the amplifier 21a, the diode 21b, and the buffer circuit 21d. A current source 24ea for driving is provided, and a negative feedback circuit is configured in which the output of the buffer circuit 24da is the negative feedback input of the amplifier 24aa. Thereby, with respect to the input signal level given by the peak reference unit 24Aa, it is possible to suppress the deviation component of the threshold voltage due to the circuit element characteristics.

  Similarly, the bottom reference unit 24Ab has a configuration corresponding to the configuration of the negative feedback circuit forming the bottom detection holding circuit 22A. Specifically, the bottom reference unit 24Ab includes an amplifier 24ab, a diode 24bb, a buffer circuit 24db, and a buffer circuit 24db corresponding to the fact that the bottom detection holding circuit 22A includes the amplifier 22a, the diode 22b, and the buffer circuit 22d. A current source 24eb for driving is provided, and a negative feedback circuit is configured in which the output of the buffer circuit 24db is the negative feedback input of the amplifier 24ab. Thereby, with respect to the input signal level given by the bottom reference section 24Ab, it is possible to suppress the deviation component of the threshold voltage due to the circuit element characteristics.

  Also in the signal amplifier circuit 13A in the second embodiment configured as described above, as in the case of the first embodiment described above, when there is no input signal, the level release circuit 24A includes the peak detection holding circuit 21A and the bottom. Since the peak level and the bottom level held by the detection holding circuit 22A can be released by discharging so as to be the level at the time of no signal of the input signal, a simple circuit configuration that does not use a reset signal enables high accuracy and The optical burst signal can be received stably.

  Further, the outputs of the buffer circuits 21d and 22d of the peak detection holding circuit 21A and the bottom detection holding circuit 22A are used as negative feedback inputs of the amplifiers 21a and 22a, and the configurations of the peak reference unit 24Aa and the bottom reference unit 24Ab are respectively detected by the peak detection unit. Since the operation of the holding circuit 21A and the bottom detection holding circuit 22A can be simulated, the threshold voltage shift component caused by the circuit element characteristics of the buffer circuits 21d, 22d, etc., can be reduced compared to the case of the first embodiment. Further suppression can be achieved.

  The configuration of the signal amplification circuit 13A in the second embodiment includes at least buffer circuits 24da and 24db corresponding to the buffer circuits 21d and 22d in the peak detection and holding circuit 21A and the bottom detection and holding circuit 22A. For example, the diodes 24ba and 24bb and the current sources 24ea and 24eb of the peak reference unit 24Aa and the bottom reference unit 24Ab can be omitted as appropriate.

[C] Description of Third Embodiment FIG. 4 is a diagram showing an optical receiver circuit to which a signal amplifier circuit 13B according to a third embodiment of the present invention is applied. The signal amplifying circuit 13B according to the third embodiment is different in the configuration of the bottom detection holding circuit 22B from the signal amplifying circuit 13A according to the second embodiment. The remaining configuration is basically the same as in the case of the second embodiment described above, and in FIG. 4, the same reference numerals as those in FIGS. 1 and 3 indicate substantially the same parts.

  Here, the bottom detection holding circuit 22B also includes the same amplifier 22a, diode 22b and amplifier 22d as shown in FIG. 3, and the output of the diode 22b and the output of the peak detection holding circuit 21A are connected to each other as shown in FIG. The capacitor 22Bc is functionally different from that shown in FIG. That is, the capacitor 22Bc detects the bottom level voltage of the input signal from the preamplifier 12 by charging. The detected bottom level voltage is relative to the peak level voltage to be output from the peak detection holding circuit 21A. It can be detected as a potential difference.

  In other words, the peak detection holding circuit 21A holds the absolute peak level voltage of the input signal from the preamplifier 12 as a master circuit, while the bottom detection holding circuit 22B serves as a slave circuit from the preamplifier 12. The bottom level voltage of the input signal is detected as a relative potential difference with respect to the peak level voltage detected by the peak detection holding circuit 21A.

  For example, as shown in FIG. 5, it is assumed that an LD bias is applied before a signal is input, and a positive level difference Δ is generated when a signal is input with respect to an input signal level when no signal is input. The LD bias is usually about 1/10 of the light emission level, but a non-negligible level difference of about 1/2 of the signal level may occur due to the nonlinearity of the preamplifier. In this case, the absolute bottom level voltage L1 in the region P1 in which the sign for the bottom level is continuous is different from the bottom level voltage L2 in the region other than the bottom level code continuous region. In such a case, even if the threshold voltage L4 is obtained using the absolute peak level voltage L3 and the bottom level voltage L1, an accurate intermediate level is set in the code determination outside the bottom level code continuous region. Can not be.

On the other hand, if the bottom level voltage is detected as a voltage level L2 relative to the peak level voltage as in the third embodiment, an accurate intermediate in code determination outside the “0” code continuous region. The level L5 can be set.
[D] Description of Fourth Embodiment FIG. 6 is a diagram illustrating a signal amplifier circuit 13C according to a fourth embodiment of the present invention. Unlike the signal amplification circuit 13B in the third embodiment, the signal detection circuit 13C according to the fourth embodiment has an absolute bottom level of the input signal from the preamplifier 12 as a master circuit. Hold for voltage. On the other hand, the peak detection holding circuit 21C has a capacitor 21Cc for connecting the output of the diode 21b and the output of the bottom detection holding circuit 22A, and as a slave circuit, the peak detection holding circuit 21C detects the bottom level of the peak level voltage of the input signal from the preamplifier 12. It is detected as a relative potential difference with respect to the peak level voltage detected by the holding circuit 22A.

  For example, as shown in FIG. 7, it is assumed that the polarity of the signal is inverted from the case of FIG. 5 and that a negative level difference Δ is generated when a signal is input with respect to the input signal level L6 when there is no signal. To do. When the peak level code continuous area P2 is included in the packet head portion, the absolute peak level voltage L6 of the peak level code continuous area and the area other than the peak level code continuous area are used. Is different from the peak level voltage L7. In such a case, even if the threshold voltage L9 is obtained using the absolute peak level voltage L6 and the bottom level voltage L8, an accurate intermediate level is set in the code determination outside the peak level code continuous region. Can not be.

On the other hand, if the peak level voltage is detected as a relative voltage level L7 with respect to the bottom level voltage L8 as in the fourth embodiment, an accurate intermediate in code determination outside the peak level code continuous region. The level L10 can be set.
[E] Description of Fifth Embodiment FIG. 8 is a diagram showing a signal amplifier circuit 13D according to a fifth embodiment of the present invention. The signal amplifying circuit 13D shown in FIG. 8 is different from the above-described embodiments in that first and second signal lines 14-1 and 14-2 are provided as signal lines for propagating electrical signals. Signal amplification is performed on a differential input signal that represents a code level that forms modulation data based on a difference in electrical signal level between two signal lines 14-1 and 14-2.

When the signal amplifier circuit 13D in the fifth embodiment is applied to the optical receiver circuit of the GE-PON station-side device as in the above-described embodiments, the differential signal for the signal received by the photodiode is used. The function of converting to is appropriately provided.
Here, the signal amplifier circuit 13D shown in FIG. 8 includes first and second peak detection and holding circuits 31-1 and 31-2, first and second adder circuits 32-1 and 32-2, and a differential amplifier 33. And a level release circuit 34. Here, the first peak detection holding circuit 31-1 detects and holds the peak level of the electric signal level in the first signal line 14-1, and the second peak detection holding circuit 31-2 includes the second peak detection holding circuit 31-2. The peak level of the electric signal level in the signal line 14-2 is detected and held.

  The first peak detection / holding circuit 31-1 includes an amplifier 31a-1 and a capacitor 31b-1, and similarly to the peak detection / holding circuit 21 in the first embodiment, the signal line 14 is charged by charging the capacitor 31b-1. The peak level of the electric signal from -1 can be detected and held. Similarly, the second peak detection / holding circuit 31-2 includes an amplifier 31a-2 and a capacitor 31b-2, and detects and holds the peak level of the electric signal from the signal line 14-2 by charging the capacitor 31b-2. Can be done.

In the first and second peak detection holding units 31-1 and 31-2, illustration of the buffer circuit as in the first embodiment is omitted.
The first addition circuit 32-1 adds the peak level held by the second peak detection holding circuit 31-2 to the electrical signal from the first signal line 14-1, and includes a resistor 32a. -1, 32b-1 is provided as a voltage dividing circuit. In other words, the first adder circuit 32-1 adds the electrical signal from the first signal line 14-1 to the electrical signal on the second signal line 14-2 that is the inversion side of the electrical signal from the first signal line 14-1. Add peak levels.

  Similarly, the second addition circuit 32-2 adds the peak level held by the first peak detection holding circuit 31-1 to the electrical signal from the second signal line 14-2, and has a resistance. The voltage dividing circuit includes 32a-2 and 32b-2. In other words, the second adder circuit 32-2 adds the electrical signal from the second signal line 14-2 to the electrical signal on the first signal line 14-1 that is the inversion side of the electrical signal from the second signal line 14-2. Add peak levels.

Further, the differential amplifier 33 differentially amplifies the addition results from the first and second adder circuits 32-1 and 32-2, and the differential amplifier 33 compares the results of identification and amplification. It can be output as a motion signal.
Further, the level release circuit 34 determines each peak level held by the first and second peak detection holding circuits 31-1 and 31-2 when there is no differential input signal. The first peak reference unit 34a-1, the second peak reference unit 34a-2, and resistors 34b-1 and 34b-2 are provided.

  Here, the first peak reference section 34a-1 gives an electric signal level (voltage level) from the first signal line 14-1, and the output of the first peak reference section 34a-1 is a resistor. It is connected to the capacitor 31b-1 of the first peak detection holding unit 31-1 via 34b-1. Similarly, the second peak reference unit 34a-2 gives an electric signal level (voltage level) from the second signal line 14-2, and the output of the second peak reference unit 34a-2 is a resistor. It is connected to the capacitor 31b-2 of the second peak detection holding unit 31-2 through 34b-2.

  Thereby, when there is no differential input signal, the voltage applied by the first and second peak reference units 34a-1 and 34a-2 is lower than the voltage at the capacitors 31b-1 and 31b-2. Therefore, in this case, the charges charged in the capacitors 31b-1 and 31b-2 are discharged through the resistors 34b-1 and 34b-2, respectively, and the voltages in the capacitors 31b-1 and 31b-2 are different. The dynamic input signal is released so as to be at the level of no signal.

  Also in the signal amplifier circuit 13D in the fourth embodiment configured as described above, the peak detection holding circuit 31 is provided in the level release circuit 34 when there is no differential input signal as in the case of the first embodiment. Since the peak level held at −1 and 31-2 can be released by discharging so as to be the level at the time of no signal of the differential input signal, high accuracy is achieved by a simple circuit configuration that does not use a reset signal. In addition, the optical burst signal can be received stably.

[F] Others Regardless of the embodiment described above, various modifications can be made without departing from the spirit of the present invention.
For example, like the signal amplification circuit 43 shown in FIG. 9, the signal amplification circuit units 13-1 and 13-2 forming the same signal amplification circuit as in the first embodiment are provided in a plurality of stages (in the case of FIG. It may be configured by connecting to a tandem. In this way, especially when the received light level is relatively small, it is possible to reduce the deviation of the threshold level during identification amplification compared to the case where the single signal amplifier circuit 13 is used.

  Further, like the signal amplification circuit 13E shown in FIG. 10, in the signal amplification circuit 13 in the first embodiment, based on the peak level and the bottom level detected by the peak detection holding circuit 21 and the bottom detection holding circuit 22, respectively. An automatic gain control unit 50 that performs automatic gain control (AGC) of the differential amplifier 23b may be provided. In the peak detection holding circuit 21 and the bottom detection holding circuit 22 in FIGS. 9 and 10, the buffer circuits 21d and 22d and the diodes 21b and 22b are not shown.

Furthermore, it is of course possible to combine the features of the above-described embodiments and modifications as appropriate.
Moreover, it is possible for those skilled in the art to manufacture the apparatus of the present invention based on the disclosure of the above-described embodiment.
[G] Appendix (Appendix 1)
A peak detection holding circuit for detecting a peak level of an electric signal constituting an input signal and holding the peak level by charging;
A bottom detection holding circuit for detecting the bottom level of the electric signal constituting the input signal and holding the bottom level by charging;
A differential amplifying circuit for differentially amplifying the input signal and the threshold using the intermediate level between the peak level and the bottom level held by the peak detection holding circuit and the bottom detection holding circuit as a threshold;
A level release circuit that releases the peak level and the bottom level held by the peak detection holding circuit and the bottom detection holding circuit by discharging so as to be equal to the no-signal level of the input signal when the input signal is no signal And a signal amplifying circuit.

(Appendix 2)
While the peak detection holding circuit detects and holds the peak level of the input signal as a voltage level, the bottom detection holding circuit detects and holds the bottom level of the input signal as a voltage level,
The level release circuit outputs the peak level voltage and the bottom level voltage held by the peak detection holding circuit and the bottom detection holding circuit when the input signal is not present, 2. The signal amplifier circuit according to appendix 1, wherein the signal amplifier circuit comprises a discharge circuit that discharges to a voltage.

(Appendix 3)
The differential amplifier circuit is
A voltage dividing circuit that divides the voltage at the peak level held by the peak detection holding circuit and the voltage at the bottom level held by the bottom detection holding circuit and outputs the voltage at the intermediate level;
The signal amplifier circuit according to appendix 2, characterized by comprising a differential amplifier that differentially amplifies the input signal and the output from the voltage dividing circuit.

(Appendix 4)
The peak detection holding circuit is provided with a first voltage holding element for holding the peak level voltage, while the bottom detection holding circuit is provided with a second voltage holding element for holding the bottom level voltage. ,
The discharge circuit is
A first voltage applying unit that applies the same voltage as the input signal voltage for discharging the peak level voltage;
A second voltage applying unit that applies the same voltage as the input signal voltage for discharging the bottom level voltage;
A first resistance element connecting between the first voltage holding element and the first voltage application unit;
The signal amplifier circuit according to appendix 2, wherein the signal amplifying circuit includes the second voltage holding element and a second resistance element that connects the second voltage applying unit.

(Appendix 5)
The input signal is a signal in which packets are time-division multiplexed with a predetermined protection time,
The discharge circuit converts the peak level voltage and the bottom level voltage held by the first and second voltage holding elements into the input signal when a protection time when no signal is input is reached. The signal amplifier circuit according to appendix 4, wherein the signal amplifier circuit is configured to be discharged so as to have a voltage at the time of no signal.

(Appendix 6)
The first and second resistance elements are configured together with the first and second voltage holding elements so that the discharge is completed within a protection time when the input signal is not present. The signal amplifier circuit according to appendix 5.
(Appendix 7)
The signal amplifying circuit according to appendix 4, wherein the first and second voltage applying units are configured by a voltage follower circuit that receives the input signal.

(Appendix 8)
The peak detection holding circuit and the bottom detection holding circuit are configured as a negative feedback circuit, and the first and second voltage applying units correspond to the negative feedback circuit forming the peak detection holding circuit and the bottom detection holding circuit. The signal amplifier circuit according to appendix 7, wherein the signal amplifier circuit is configured as a negative feedback circuit.

(Appendix 9)
Any one of the peak detection holding circuit and the bottom detection holding circuit detects and holds the level to be detected and held on the one hand as a relative level with respect to the level detected on the other, The signal amplifier circuit according to appendix 1.
(Appendix 10)
Detects and holds the peak level of the electric signal level in the first signal line in the differential input signal representing the code level forming the modulation data by the difference between the electric signal levels conducting the first signal line and the second signal line A first peak detection and holding circuit, and a second peak detection and holding circuit for detecting and holding the peak level of the electric signal level in the second signal line;
A first addition circuit for adding the peak level held by the second peak detection holding circuit to the electrical signal from the first signal line;
A second addition circuit for adding the peak level held by the first peak detection holding circuit to the electrical signal from the second signal line;
A differential amplifier for differentially amplifying each addition result from the first and second adder circuits;
A level release circuit for releasing each peak level held by the first and second peak detection holding circuits so as to be equal to the no-signal level of the differential input signal when the input signal is non-signaled; A signal amplifying circuit characterized by being provided.

(Appendix 11)
Detects the peak level of the electrical signal forming the input signal and holds the peak level by charging, and detects the bottom level of the electrical signal forming the input signal, and holds the bottom level by charging. A bottom detection holding circuit that performs differential amplification of the input signal and the threshold using the peak detection and holding circuit and an intermediate level between the peak level and the bottom level as a threshold. A level at which the peak level and the bottom level held by the peak detection holding circuit and the bottom detection circuit are released by discharging so as to become a level at the time of no input signal of the input signal when there is no signal in the circuit and the input signal A signal amplifier circuit comprising a plurality of stages of amplifier circuit units each including a release circuit.

(Appendix 12)
A photoelectric conversion element that converts an optical input signal into an electrical signal;
A preamplifier circuit for amplifying the electrical signal;
An optical receiver circuit comprising a signal amplifier circuit that amplifies the electric signal amplified by the preamplifier circuit as an input signal,
The signal amplifier circuit is
A peak detection holding circuit for detecting a peak level of an electric signal constituting an input signal and holding the peak level by charging;
A bottom detection holding circuit for detecting the bottom level of the electric signal constituting the input signal and holding the bottom level by charging;
A differential amplifying circuit for differentially amplifying the input signal and the threshold using the intermediate level between the peak level and the bottom level held by the peak detection holding circuit and the bottom detection holding circuit as a threshold;
A level release circuit for releasing the peak level and the bottom level held by the peak detection holding circuit and the bottom detection circuit by discharging so that the input signal becomes a no-signal level when there is no signal, And an optical receiver circuit.

It is a figure which shows the optical receiver circuit to which the signal amplifier circuit concerning 1st Embodiment of this invention is applied. (A), (b) is a time chart for demonstrating operation | movement of 1st Embodiment of this invention. It is a figure which shows the optical receiver circuit to which the signal amplifier circuit concerning 2nd Embodiment of this invention was applied. It is a figure which shows the optical receiver circuit to which the signal amplifier circuit concerning 3rd Embodiment of this invention was applied. It is a figure for demonstrating operation | movement of 3rd Embodiment of this invention. It is a figure which shows the optical receiver circuit to which the signal amplifier circuit concerning 4th Embodiment of this invention was applied. It is a figure for demonstrating the operation | movement of 4th Embodiment of this invention. It is a figure which shows the signal amplifier circuit concerning 5th Embodiment of this invention. It is a figure which shows the signal amplifier circuit concerning the modification of this invention. It is a figure which shows the signal amplifier circuit concerning the modification of this invention. It is a figure which shows the optical communication network comprised as GE-PON. It is a figure which shows the optical receiver circuit provided in the conventional station side apparatus. (A)-(c) is a figure for demonstrating operation | movement of the optical receiver circuit shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Photodiode 12 Preamplifier 13, 13A-13E Signal amplification circuit 13-1, 13-2 Signal amplification circuit part 14-1, 14-2 1st, 2nd signal line 21,21A, 21C Peak detection holding | maintenance part 21a, 22a Amplifier 21b, 22b Diode 21c, 22c, 22Bc Capacitance 21d, 22d Buffer circuit 22, 22A, 22B Bottom detection holding unit 23 Differential amplifier 23a Voltage divider 23a-1, 23a-2 Resistor 23b Differential amplifier 24, 24A Level Release circuit 24a, 24Aa Peak reference section (level release circuit)
24b, 24Ab Bottom reference section (level release circuit)
24aa, 24ab amplifier 24ba, 24bb diode 24da, 24db buffer circuit 24ea, 24eb current source 24c, 24d resistance (first and second resistance elements, level release circuit)
31-1, 31-2 First and second peak detection holding units 31a-1, 31a-2 Amplifiers 31b-1, 31b-2 Capacitance 32-1, 32-2 First and second adder circuits 32a-1, 32a-2, 32b-1, 32b-2 Resistor 33 Differential amplifier 34 Level release circuit 34a-1, 34a-2 First and second peak reference sections (level release circuit)
34b-1, 34b-2 resistance (level release circuit)
43 Signal Amplifier Circuit Device 50 Automatic Gain Control Unit 100 Network 101 Station Side Device 102-1 to 102-N Subscriber Device 103-1 to 103-N Transmission Line 103a, 103c-1 to 103c-N Optical Fiber 103b Branch Coupler 110 Optical receiver circuit 111 Photo diode 112 Preamplifier 113 Differential amplifier circuit section 113a Peak detection circuit 113a-1, 113b-1 Amplifier 113a-2, 113b-2 Capacitance 113b Bottom detection circuit 113c Voltage division circuit 113d Differential amplifier 113e Reset circuit

Claims (3)

Detects the peak level of the input electric signal, a peak detection holding circuit that holds the charging of the peak level first capacitive element,
Both to detect the bottom level of the input electrical signal, and the bottom detection holding circuit for holding by the bottom level charging of the second capacitor element,
And divided by the threshold from the peak detection holding circuit and the bottom detection the peak level held respectively by the holding circuit and the bottom level, a differential amplifier circuit for differentially amplifying the said input electrical signal,
A level release circuit for supplying a reference signal having a voltage corresponding to the voltage of the input electric signal to the first capacitor element and the second capacitor element through the first resistor element and the second resistor element, respectively; ,
The input electrical signal is a signal obtained by time-division multiplexing a plurality of electrical signals,
When the input electric signal is at a no-signal level, the charges respectively held in the first capacitive element and the second capacitive element are passed through the first and second resistive elements, respectively. Discharged by the release circuit ,
The first discharge time constant by the first capacitor element and the first resistor element, and the second discharge time constant by the second capacitor element and the second resistor element are the values of the input electric signal. A signal amplifier circuit characterized by being shorter than a time division multiplexing guard time and longer than the same level continuous time in the plurality of electrical signals . A signal amplification circuit for a differential input signal based on a level difference between a first electrical signal conducting a first signal line and a second electrical signal conducting a second signal line ,
A first peak detection holding circuit for detecting a peak level of the electric signal level in the first signal line and holding the peak level by charging the first capacitor element, and an electric signal level in the second signal line are provided. And a second peak detection holding circuit for holding the peak level by charging the second capacitive element ,
A first addition circuit for adding the peak level held by the second peak detection holding circuit to the electrical signal from the first signal line;
A second addition circuit for adding the peak level held by the first peak detection holding circuit to the electrical signal from the second signal line;
A differential amplifier for differentially amplifying each addition result from the first and second adder circuits;
Reference signals of voltages corresponding to the voltages of the first and second electric signals are respectively transmitted to the first capacitor element and the second capacitor element through the first resistor element and the second resistor element. With a level release circuit to supply,
The differential input signal is a signal in which a plurality of electrical signals are time-division multiplexed.
When the differential input signal is at the level of the no-signal charges held respectively in the capacitor element and the second capacitive element of the first is, through the first and second resistive elements, respectively the Discharged by the level release circuit,
The first discharge time constant due to the first capacitor element and the first resistor element, and the second discharge time constant due to the second capacitor element and the second resistor element are the values of the input electric signal. A signal amplifier circuit characterized by being shorter than a time division multiplexing guard time and longer than the same level continuous time in the plurality of electrical signals . A photoelectric conversion element that converts an optical input signal into an electrical signal;
A preamplifier circuit for amplifying the electrical signal;
An optical receiver circuit comprising a signal amplifier circuit that amplifies the electric signal amplified by the preamplifier circuit as an input signal,
The signal amplifier circuit is
Detects the peak level of the input electric signal, a peak detection holding circuit that holds the charging of the peak level first capacitive element,
Both to detect the bottom level of the input electrical signal, and the bottom detection holding circuit for holding by the bottom level charging of the second capacitor element,
And divided by the threshold from the peak detection holding circuit and the bottom detection the peak level held respectively by the holding circuit and the bottom level, a differential amplifier circuit for differentially amplifying the said input electrical signal,
A level release circuit for supplying a reference signal having a voltage corresponding to the voltage of the input electric signal to the first capacitor element and the second capacitor element through the first resistor element and the second resistor element, respectively; ,
The input electrical signal is a signal obtained by time-division multiplexing a plurality of electrical signals,
When the input electric signal is at a no-signal level, the charges respectively held in the first capacitive element and the second capacitive element are passed through the first and second resistive elements, respectively. Discharged by the release circuit ,
The first discharge time constant by the first capacitor element and the first resistor element, and the second discharge time constant by the second capacitor element and the second resistor element are the values of the input electric signal. An optical receiving circuit characterized in that it is shorter than the time division multiplexing guard time and longer than the same level continuous time in the plurality of electrical signals .

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