JP4398957B2 - Nonvolatile semiconductor memory device and method for controlling nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) and a method for controlling the nonvolatile semiconductor memory device, and in particular, a series of data rewriting operations including a verify operation are automatically sequence-controlled by a built-in control circuit. Relates to the EEPROM.

  In recent EEPROM flash memories, a control circuit for performing write / erase sequence control is built in the chip. In this type of EEPROM, if a command and write data are input from the outside, a series of operations until a predetermined write is completed, including a data write operation and a subsequent verify operation, are automatically performed. From the start of the write operation to the completion of write, a busy signal is output to the outside and access is prohibited.

Such busy waiting time of the EEPROM flash memory impairs the high speed performance of the memory system. Therefore, in order to achieve high-speed performance in a flash memory system using a plurality of memory chips, commands and data are input in a time-sharing manner using a common data bus, and internal operations can be performed in parallel on the plurality of memory chips. It is effective to be executed. The present inventors have already proposed such a technique (Japanese Patent Application Nos. 6-95125 and 6-95126).
US Pat. No. 5,603,001

  However, in recent years, the capacity of one chip of flash memory has been increasing. If the necessary capacity of the memory system is enough for one chip, the above-described time-division control method using a plurality of chips cannot be applied, and high-speed performance cannot be obtained. Therefore, it is desired that even a single memory chip can realize high-speed performance by time-division control and parallel processing similar to the case where a plurality of chips are used.

  Also, as a convenience of the CPU controlling the memory system, even if the required capacity of the memory system is increased, the size of the file to be handled is not significantly increased except in the case of an image file or the like. There is also a circumstance that it is preferable to handle a lot. The page mapping size of the CPU of the personal computer is also maintained as a common value regardless of the CPU generation, for example, 4 kbytes.

  In such a host system environment, it is not always appropriate for the memory device side to increase the write page size or the erase block size as the storage capacity increases. In many cases, writing and erasing are preferable.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a non-volatile semiconductor memory device in which one memory chip can be controlled in the same manner as a plurality of memory chips, and a control method for the non-volatile semiconductor memory device. Yes.

  The present invention is an electrically rewritable non-volatile semiconductor memory device in which a plurality of memory circuits each having a control circuit for performing write sequence control are mounted in one memory chip, sharing a data bus, and An enable terminal for controlling activation and deactivation is provided for each of the memory circuits.

  Furthermore, the present invention is an electrically rewritable nonvolatile semiconductor memory device, in which a plurality of memory circuits each having a control circuit for performing write sequence control are mounted in one memory chip, sharing a data bus. In addition, the activation and deactivation of each memory circuit is controlled by command input.

  Furthermore, the present invention is an electrically rewritable nonvolatile semiconductor memory device, in which a plurality of memory circuits each capable of addressing are mounted in one memory chip, and each memory circuit corresponds to an address. And at least one stage of data buffer for sending out write data to be written, and write operations to the plurality of memory circuits are simultaneously performed via the data buffer.

  Furthermore, the present invention provides a plurality of addressable memory circuits mounted in one memory chip, a plurality of data registers provided for each of the memory circuits and holding write data corresponding to each address, In the control method in the electrically rewritable nonvolatile semiconductor memory device, comprising: a control circuit that starts writing operation of the write data from the plurality of data registers to the plurality of memory circuits in parallel; After the operation of inputting data is repeated a plurality of times, a write start command is input, and then a pass / fail result of the write operation in the whole of the plurality of memory circuits is output.

  According to the present invention, a plurality of memory circuits (EEPROM circuits) in one chip can be time-divisionally operated or operated in parallel as if they were a plurality of chips. Therefore, unlike when the capacity of one chip is simply increased by one control circuit, it is possible to access other memory circuits even when a certain memory circuit is busy. A performance memory system is obtained.

  As described above, according to the present invention, it is possible to obtain a non-volatile semiconductor memory device and a non-volatile semiconductor memory device control method in which one memory chip can be controlled similarly to a plurality of memory chips.

  Embodiments of the present invention will be described below with reference to the drawings.

[First Embodiment] FIG. 1 shows a configuration of a memory chip 1 according to an embodiment of the present invention. The memory chip 1 is mounted with a plurality (four in the figure) of EEPROM circuits 2 (2-1 to 2-4) each including a control circuit for controlling writing and erasing sequences. These EEPROM circuits 2 share a data bus 3. Each EEPROM circuit 2 has a normal EEPROM chip function independently. Therefore, as shown in the figure, enable terminals CE1 to CE4 for controlling activation and deactivation for each EEPROM circuit 2, and Ready / Busy signals. Terminals R / B1 to R / B4 are provided.

  FIG. 2 shows the configuration of each EEPROM circuit 2. In the memory cell array 21, electrically rewritable nonvolatile memory cells having a stacked gate structure are arranged and connected in a NAND type. The row decoder 22 and the column decoder 25 select the word line and bit line of the memory cell array 21, respectively. The address signal is taken into the address register 27 via the I / O buffer 26, decoded by the row decoder 22 and the column decoder 25, and a memory cell is selected. Bit lines of the memory cell array 21 are connected to a sense amplifier 23, and the sense amplifier 23 is connected to an I / O buffer 26 via a data register 24.

  In order to generate various high voltages used for data writing and erasing, a boosting power supply circuit 30 is provided. The control circuit 29 performs data write and erase sequence control including a verify operation, and simultaneously controls the boost power supply circuit 30 according to the operation mode. The command CMD for writing, erasing, etc. is taken into the command register 28 via the I / O buffer 26. The command fetched into the command register 28 is decoded by the control circuit 29, and writing and erasing are controlled in accordance with the command. The I / O buffer 26 receives various enable signals including an enable signal / CE instructing activation / inactivation of the entire circuit from the enable terminal CE. These control signals are also sent to the control circuit 29. The control circuit 29 outputs a busy signal to the terminal R / B via the Ready / Busy buffer 31 when the enable signal is / CE = H.

  In the memory chip 1 configured as described above, since each EEPROM circuit 2 has a normal chip function, it is possible to cause each EEPROM circuit 2 to perform data writing or erasing in parallel.

  As described above, according to this embodiment, by mounting a plurality of EEPROM circuits each having an autonomous control function in one chip, each EEPROM circuit can be operated in parallel, and High speed operation is possible. Further, by providing an enable terminal and a corresponding Ready / Bysy terminal for each EEPROM circuit, each EPROM circuit can be externally controlled like an independent memory chip. Therefore, unlike the case where the storage capacity of one chip is simply increased, high-speed performance can be realized, and data input / output requests in small capacity units can be flexibly handled.

[Second Embodiment] FIG. 3 shows a configuration of a memory chip 1a according to another embodiment. This embodiment differs from the previous embodiment in that the memory chip 1a has enable terminals CE1 to CE4 of each internal EEPROM chip 2 and a master enable for controlling the activation and deactivation of the entire memory chip 1a. It has a terminal MCE. Other than that, it is not different from the previous embodiment. As shown in FIG. 3, the master enable signal terminal MCE and the enable terminal CE of each EEPROM circuit 2 are connected to the inputs of AND gates G1 to G4, and the AND outputs of the two signals are supplied to each EEPROM circuit 2.

  With such a configuration, for example, enable signal lines from a chip set that controls a memory system including a plurality of memory chips can be reduced. For example, FIG. 4 shows an example in which two memory chips 1a1 and 1a2 are used. In this case, the enable terminals CE1 to CE4 of the two memory chips 1a1 and 1a2 are connected in common, and the master enable terminal MCE is connected in common by inserting an inverter I on one side. Also, the Ready / Busy terminals R / B of the memory chips 1a1 and 1a2 are connected in common.

  Thus, the memory chips 1a1 and 1a2 can be selectively activated by the common master enable terminals MCE “0” and “1”, and the two memory chips 1a1 and 1a2 can be controlled with a small number of signal lines. Is possible.

  Specifically, when a memory system as shown in FIG. 4 is configured, the following operation is performed in a chip set that controls the memory system in response to a request from the host side. That is, the host request is only the designation of enable CE to CE4 and the address designation. At this time, in the chip set, “0” and “1” of the master enable MCE are determined with reference to the storage capacity register of the EEPROM circuit 2 of the memory chips 1a1 and 1a2. Then, the chip set issues a master enable signal together with designation of the enable terminals CE1 to CE4 and address designation which are requests of the host. Thereby, one of the memory chips 1a1 and 1a2 is selected.

[Third Embodiment] FIG. 5 shows a configuration of a memory chip 1b according to another embodiment. This embodiment differs from the embodiment of FIG. 1 in that only one enable terminal CE and one Ready / Busy terminal R / B are provided outside. Internally, the enable terminals CE 1 to CE 4 and the Ready / Busy terminals R / B 1 to R / B 4 of the EEPRPOM circuit 2 are selected by the memory function register 4.

  The memory function selection circuit 3 is controlled by command input. For example, when the chip enable CE is activated and the selection of the enable terminal CE1, that is, the EEPROM circuit 2-1, is instructed by command input, the chip enable CE is enabled for the EEPROM circuit 2-1, by the memory function register 4. At this time, the Ready / The Busy terminal R / B outputs the Ready / Busy state of the EEPROM circuit 2-1. When the chip enable CE is deactivated, the chip enable for the entire memory chip 1b is negated.

  In this way, by performing access sorting by command input to a plurality of EEPROM circuits in the memory chip, it is possible to control a large capacity memory system with the same number of signal terminals as in the case of one EEPROM circuit. Therefore, the same CPU can be connected to memory chips of different generations only by changing the software. In addition, when the chip enable signal CE is deactivated, it is unlikely that control continues to each EEPROM circuit, so that the selection of each EEPROM circuit is canceled in conjunction with this, Control of deselection is facilitated, and subsequent control is also facilitated.

  From the software side, the activation / deactivation control for each EEPROM circuit is controlled via the chip set. Therefore, it is more consistent with the hardware configuration of the memory when the chip enable terminal is externally used and the internal EEPROM circuit is enabled by the command than the time division control of the plurality of enable terminals. It will be a good one. There are few bugs in software control.

[Fourth Embodiment] FIG. 6 shows a memory chip 1c according to an embodiment obtained by modifying the embodiment shown in FIG. The memory chip 1c of this embodiment is different from FIG. 5 in that the memory chip 1c does not have a chip enable terminal and a Ready / Busy terminal outside and includes a Ready / Busy register 5 that realizes the function in software. In this embodiment, the chip enable control command and the Ready / Busy reference command are included in the various commands CMD.

  That is, in this embodiment, by inputting a chip enable control command, internal enable signals CE1 to CE4 are generated for each EEPROM circuit 2 of the memory chip 1c. In addition, when a Ready / Busy reference command is input, the register 5 is referred to by software and the Ready / Busy state information is obtained from the return value data.

  According to such an embodiment, it is not necessary to perform a scanning operation of the signal terminal in order to monitor the Ready / Busy signal of each EEPROM circuit. Accordingly, it is not necessary to allow for a delay in switching transition time as in the case of outputting the Ready / Busy signal of each EEPROM circuit by switching the same signal line. Furthermore, if the ready / busy state of each EEPROM circuit can be obtained collectively by command control, high-speed operation control can be performed.

  In an initial setting state in which command control is not performed, if the operation is performed in the conventional memory chip specification compatible mode (that is, a specification that does not make it conscious of having a plurality of EEPROM circuit functions inside), it can be applied to the conventional device as it is. You can also. Further, if it is possible to return to the initial state by issuing a reset command, it is possible to return the memory chip to the origin at the time of abnormality processing on the software side, and a highly recoverable memory system can be obtained.

[Fifth Embodiment] FIG. 7 shows a configuration of a memory chip 1d according to still another embodiment. In this embodiment, an area for selecting which EEPROM circuit 2 is to be programmed / erased by command input between the data bus 3 common to each EEPROM circuit 2 in the memory chip 1 and the external I / O terminal. A selection decoder 6 is provided. This area selection decoder 6 enables command input, address input and data input to the I / O buffer of each EEPROM circuit 2 in time series. In this case, the selection order of the EEPROM circuit 2 can be arbitrarily set. Further, the EEPROM circuit 2 does not include a control circuit, and a control circuit 7 for controlling the writing and the like is provided as one.

  According to this embodiment, for example, while data is written in the EEPROM circuit 2-1, it is possible to input data from the outside to the other EEPROM circuits 2-2 to 2-4. Therefore, a continuous data writing operation is possible without waiting time.

  Specifically, an example of the operation of the write cache in this embodiment will be described with reference to FIGS. As shown in FIG. 8, in order to write to the EEPROM circuit 2-1, a data input (write) command “80”, an address Add1, and data Data1 are input, and then a dummy program command “11” is input. These are taken into the EEPROM circuit 2-1. The dummy program command “11” is a command that does not transfer the fetched data to the internal data register 24 and is busy during that time. The data register 24 requires a two-stage configuration in order to perform a cache operation. Similarly, in order to write to each EEPROM circuit 2, a data input command “80”, an address Add, and data Data are input, and then a dummy program command “11” is input. Finally, the write start command “15” is input.

  When this write start command “15” is input, the data held in the latches in the I / O buffer so far in each EEPROM circuit 2 is simultaneously transferred to the internal data register 24. Thereby, the writing operation to the page selected by the address is started in parallel in each EEPROM circuit 2. When data writing is started, each EEPROM circuit 2 automatically repeats writing and verifying until the condition for completion of writing is satisfied. When the batch data transfer to the internal data register 24 is completed, the external state is ready.

  In this embodiment, preferably, the Pass / Fail result of the write operation of each EEPROM circuit 2 is output in units of memory cells for each EEPROM circuit 2, and the Pass / Fail result of the entire memory chip 1d is output. As a result, the processing in the case of Fail can be performed for each EEPROM circuit 2, and if the overall Pass / Fail is known, it is determined whether to continue or stop the processing without referring to the writing result of each EEPROM circuit 2. It becomes possible to do.

  In this embodiment, preferably, the accumulation of the Pass / Fail result of the write operation repeatedly performed for each EEPROM circuit 2 is held, and the presence / absence information on the failure of the accumulation is output. As a result, the entire Pass / Fail can be determined after all the series of writing operations are completed. In particular, when a write cache operation is performed, a series of operations can be performed continuously, thereby enabling high-speed performance processing.

  Further, the accumulation of the Pass / Fail result can be considered for each EEPROM and for the entire memory chip. In the former case, each EEPROM circuit can be processed in the case of “Fail”, and in the latter case, it is not necessary to refer to each EEPROM circuit in the case of “Pass”.

  Furthermore, in this embodiment, after referring to the pass / fail result of data writing, the mode for inputting the next data to the data buffer and the data buffer continuously without referring to the pass / fail result. It is desirable to have a mode for inputting data and to allow these to be selected. In this case, the meaning of how to output the Busy signal differs depending on the mode. That is, in the former mode, the Busy state ends when the write result state can be referred to. In this case, since the data writing is actually completed, the next data input is possible. In the latter case, the Busy state ends when the next data writing becomes possible.

  By enabling such mode selection, it is possible to select high-speed processing and stable processing. If this mode selection can be performed by command input, the control software can be simplified.

It is a figure which shows the structure of the memory chip by embodiment of this invention. It is a figure which shows the structure of each EEPROM circuit of the embodiment. It is a figure which shows the structure of the memory chip by another embodiment. It is a figure which shows the memory system structural example using the memory chip of the embodiment. It is a figure which shows the structure of the memory chip by another embodiment. It is a figure which shows the structure of the memory chip by another embodiment. It is a figure which shows the memory chip structure by another embodiment. It is a figure which shows the example of the control signal input in the same embodiment. It is a figure which shows write-in operation | movement of each EEPROM circuit of the embodiment.

Explanation of symbols

  1, 1a, 1b, 1c, 1d ... memory chip, 2 ... EEPROM circuit, 3 ... data bus.

Claims (6)

In an electrically rewritable nonvolatile semiconductor memory device,
A plurality of addressable memory circuits mounted in one memory chip;
A plurality of data registers provided for each of the plurality of memory circuits and holding write data corresponding to each address;
An I / O buffer in which the write data is latched;
A control circuit that transfers the write data latched in the I / O buffer to the plurality of data registers and starts writing the write data to the plurality of memory circuits in parallel ;
Ready / busy signal terminal
In each of the plurality of memory circuits, writing and verifying in the writing operation are repeated,
Outputting a pass / fail result of a write operation in the whole of the plurality of memory circuits ;
And when each data transfer from the I / O buffer to each data register is completed and before each data write from each data register to each memory circuit is completed. In addition, a non-volatile semiconductor memory device that outputs a ready signal via the ready / busy signal terminal .   The nonvolatile semiconductor memory device according to claim 1, wherein the pass / fail result of the write operation is accumulated and held by a plurality of write operations.   The nonvolatile semiconductor memory device according to claim 1, wherein a pass / fail result of the write operation is output for each of the plurality of memory circuits.   4. The nonvolatile semiconductor memory device according to claim 3, wherein the pass / fail result of the write operation is accumulated and held by a plurality of write operations. Further equipped with a plurality of ready / busy signal terminals,
When each data transfer from each I / O buffer to each data register is completed in a time division operation, each ready signal is output via the plurality of ready / busy signal terminals. The nonvolatile semiconductor memory device according to claim 3. In an electrically rewritable nonvolatile semiconductor memory device,
Each addressable memory circuit mounted in one memory chip;
A data register provided in the memory circuit for holding write data corresponding to each address;
An I / O buffer in which the write data is latched;
A control circuit that transfers the write data latched in the I / O buffer to the data register and starts an operation of writing the write data to the memory circuit;
A ready / busy signal terminal for outputting a ready signal to the outside when data transfer from the I / O buffer to the data register is completed;
In the memory circuit, writing and verifying in the writing operation are repeated,
Outputting a pass / fail result of a write operation of the memory circuit ;
The ready / busy signal terminal is set when the data transfer from the I / O buffer to the data register is completed and before the data writing from the data register to the memory circuit is completed. A non-volatile semiconductor memory device characterized by outputting a ready signal via

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