JP4397920B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device technology, and more particularly to a technology that is effective when applied to portable devices such as mobile phones and handy-type personal computers that are becoming increasingly smaller, lighter, and thinner.

  In recent years, along with higher functionality and higher performance of electronic devices, movements to make them smaller, lighter, and thinner have become active. This is largely due to the recent rapid increase in mobile devices such as mobile phones and handheld personal computers. In addition, the role of man-machine interface for devices operated by individuals has increased, and the ease of handling and operability have become increasingly important. In the future, it is expected that this trend will intensify with the advent of the full-fledged multimedia era.

  Under such circumstances, the progress of higher density and higher integration of semiconductor chips is not known, and the size of semiconductor chips and the increase in number of electrodes have progressed, and the size of packages has increased rapidly. For this reason, on the other hand, in order to advance the miniaturization of the package, the narrowing of the pitch of the terminal leads has been accelerated, and at the same time, the mounting of the package has become difficult.

  Therefore, in recent years, super-multi-pin, high-density packages having the same area as a semiconductor chip have been proposed. For example, Nikkei BP, May 1, 1994 “Nikkei Microdevices” P98 to P102 (Non-patent Document 1) ), “Nikkei Microdevices” P96 to P97 (Non-patent Document 2) issued on February 1, 1995, and “Electronic Materials” P22 to P28 (Non-patent Documents) issued on April 1, 1995 Examples thereof include packaging technology described in the literature such as 3).

  An example of the structure in these package technologies is that, for example, a flexible wiring board is provided on the surface of a semiconductor chip via an elastomer, and a lead on one end side of the wiring of the flexible wiring board is a bonding pad on the surface of the semiconductor chip. The bump land on the other end side of the wiring of the flexible wiring board is electrically connected to the solder bump.

This package structure uses a flexible wiring board on which solder bumps are formed, and the outer dimensions are the same as that of the semiconductor chip or are larger by a protective frame to be attached if necessary. The wiring pattern of this wiring board is formed of Au-plated Cu foil, and the tip portion is etched by Cu to form an Au lead. The flexible wiring board is bonded to the surface of the semiconductor chip with an elastomer, and the Au lead is connected to the bonding pad of the semiconductor chip.
Nikkei Business Publications, May 1, 1994 "Nikkei Microdevice" P98-P102 Nikkei Business Publications, Nikkei Microdevice issued on February 1, 1995, P96-P97 Industrial Research Committee, “Electronic Materials” issued on April 1, 1995, P22 to P28

  Incidentally, in the package structure as described above, according to the study by the present inventors, the following can be considered. For example, since the flexible wiring board in the package structure employs a so-called back wiring structure in which an elastomer is formed on the wiring surface of the wiring board, the unevenness of the wiring pattern on the flexible wiring board is a factor. It is difficult to mount the camera uniformly and stably.

  That is, when applying or pasting the elastomer onto the flexible wiring board, voids that are not filled with the elastomer are formed on both sides of the convex portion of the wiring pattern, and further, since the dimensional shape of the elastomer is not stable, the semiconductor chip bonding process is also performed. It is also conceivable that there may be a problem that it cannot be performed stably.

  Accordingly, one object of the present invention is to employ a surface wiring structure to stably mount an elastic structure on a wiring board with high accuracy, to stabilize a semiconductor chip bonding process, and to perform assembly with a high yield. A semiconductor integrated circuit device is provided.

  One object of the present invention is to provide a semiconductor integrated circuit device capable of obtaining excellent electrical characteristics in terms of noise resistance and the like by employing a multiple wiring layer structure.

  One object of the present invention is to apply a surface wiring structure and a multi-wiring layer structure to various types and variations of package structures.

  One object of the present invention is to prevent contamination of wiring by components of an elastic structure by optimizing the eaves of a substrate base material.

  One object of the present invention is to prevent damage to a semiconductor chip by optimizing the package external dimensions, improve the reliability of the semiconductor chip, in addition, poor adhesion between the elastic structure and the semiconductor chip, deterioration of the flatness of the wiring board, reliability It is to prevent the decrease of

  One object of the present invention is to eliminate the need for a special wire bonder that has been softly modified by a planar S-shaped wiring structure, and to simplify the trajectory of the bonding tool to obtain the effect of shortening the tact time during bonding.

  One object of the present invention is to solve the problem at the time of cutting of wiring by a cantilever wiring structure.

  One object of the present invention is to reduce passivation or damage to a semiconductor chip underneath by expanding a passivation opening around an external terminal of a semiconductor chip, and to improve bonding properties by preventing contamination of wiring. .

  One object of the present invention is to increase the bonding area between the wiring and the substrate substrate by increasing the effective area of the wiring portion on the notch termination side of the wiring, and to obtain a stable notch cutting property.

  One object of the present invention is to suppress the warping of the wiring board by the expansion structure of the elastic structure, further improve the adhesion by the adhesive, and constitute a package having excellent moisture resistance and reliability.

  One object of the present invention is to improve the groove filling performance by the groove filling technique of the elastic structure, and to increase the strength of the metal mask by using a plurality of one-side hanging portions, and further to prevent the sealant flow. The purpose is to further improve the groove filling performance by forming a dam.

  One object of the present invention is to improve bondability and prevent damage to a semiconductor chip in an inner lead bonding technique.

  One object of the present invention is to form a suitable S-shape by simply dropping the bonding tool vertically without the return of the bonding tool by wiring design considering the bending stress ratio.

  One object of the present invention is to make it difficult for the wiring itself to crack due to the conductive material core and the wiring structure formed by Au plating, and to reduce bonding damage to the semiconductor chip.

  One object of the present invention is to suppress the bleed of the low molecular weight component of the elastic structure by forming an insulating material on the wiring, and further to prevent defects such as void entrainment during the formation of the elastic structure by flattening the surface. There is to avoid.

  One object of the present invention is to increase the hole diameter machining accuracy in an insulating film by employing a surface wiring structure in a method of manufacturing a semiconductor integrated circuit device.

  One object of the present invention is that in a method of manufacturing a semiconductor integrated circuit device, a small bump electrode can be satisfactorily bonded by applying a thin and stable insulating film by adopting a surface wiring structure, and further, an arrangement pitch of the bump electrodes is reduced. Since it can be made small, it is to constitute a semiconductor package having higher-density output terminals.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, in one semiconductor integrated circuit device of the present invention, a wiring board is provided on the main surface of the semiconductor chip via an elastic structure, and one end of the wiring of the wiring board is connected to an external terminal on the main surface of the semiconductor chip. And a land portion that is the other end of the wiring of the wiring board is electrically connected to the bump electrode, and the wiring of the wiring board has a notch And an anchor wiring having an effective area larger than that of the wiring is formed in the wiring on the terminal side of the notch.

  In the semiconductor integrated circuit device of the present invention, the anchor wiring is formed in a direction intersecting with the direction in which the wiring extends, or connected to an adjacent wiring. is there.

  In another semiconductor integrated circuit device of the present invention, a wiring board is provided on the main surface of the semiconductor chip via an elastic structure, and the lead portion that is one end side of the wiring of the wiring board is bent. Applying to a semiconductor integrated circuit device that is electrically connected to an external terminal on the main surface of the semiconductor chip and is electrically connected to a bump electrode on the other end side of the wiring of the wiring board, The wiring board has the wiring formed on the main surface of the substrate substrate, the elastic structure is disposed on the back surface side of the substrate substrate, and the insulating film is formed on the main surface of the wiring. The package structure adopts a so-called surface wiring structure. In particular, the wiring of the wiring board has a plurality of wiring layer structures.

  Further, the bump electrode connected to the external terminal of the semiconductor chip via the wiring of the wiring board is provided by disposing the external terminal of the semiconductor chip at a central portion or an outer peripheral portion of the semiconductor chip. It is arranged in the inner side, the outer side or both the inner side and the outer side.

  According to another aspect of the present invention, there is provided the semiconductor integrated circuit device according to the present invention, wherein the dimensions of the end portion of the elastic structure and the end portion of the substrate substrate of the wiring board on the external terminal side of the semiconductor chip Alternatively, it is set based on physical characteristics.

Furthermore, in one semiconductor integrated circuit device of the present invention, the distance between the end of the substrate base of the wiring substrate and the end of the elastic structure on the outer peripheral side of the semiconductor integrated circuit device is M2, and the semiconductor chip When the distance between the end of the substrate and the end of the substrate base material is M1,
M1>M2> 0
M2 and M1 are set within a range that satisfies the above relationship.

  Furthermore, in one semiconductor integrated circuit device of the present invention, the wiring of the wiring board includes at least a portion of the wiring substrate fixed to the substrate base and a tip portion connected to the external terminal of the semiconductor chip. It is formed in a shape displaced by more than the width.

  Further, in one semiconductor integrated circuit device of the present invention, the wiring of the wiring board is formed in a cantilever structure in which one side is fixed to a substrate base material of the wiring board.

  Furthermore, in one semiconductor integrated circuit device of the present invention, when the bonding tool is downed at least at the end of the opening of the surface protection film on the semiconductor chip, the wiring is The dimension is set so as not to interfere with the surface protective film.

  Furthermore, in one semiconductor integrated circuit device of the present invention, the wiring of the wiring board is formed with a large effective area of the wiring portion on the notch termination side of the wiring. In particular, the wiring part on the notch termination side is connected to the land part of the opposing wiring, is extended in the vertical or horizontal direction to a vacant area of the wiring, or adjacent wirings are connected to each other. .

  Furthermore, in one semiconductor integrated circuit device of the present invention, the elastic structure is formed over the entire circumference at least as much as the width of the outer peripheral protrusion formed on the elastic structure, compared to the outer dimensions of the semiconductor chip. It is formed in a large range.

  Furthermore, in one semiconductor integrated circuit device of the present invention, when the elastic structure is divided and formed so as not to adhere to the external terminal of the semiconductor chip, the space of the opposed spaces of the divided elastic structure is Each end is formed in a groove shape. In particular, a plurality of grooves formed at each end of the elastic structure are formed, or grooves at each end of the space facing the divided elastic structure are formed during the sealing process. A dam for sealing material flow prevention is formed in advance.

  Further, in one semiconductor integrated circuit device of the present invention, a connection structure between the external terminal of the semiconductor chip and the wiring of the wiring board is formed, and stud bumps are formed in advance on the external terminals of the semiconductor chip. The external terminal of the semiconductor chip is connected to the wiring of the wiring board via the wiring.

  Furthermore, in one semiconductor integrated circuit device of the present invention, the solder is supplied to the connection structure between the external terminal of the semiconductor chip and the wiring of the wiring board so as to enclose the wiring of the wiring board in advance, The external terminal of the semiconductor chip and the external terminal of the semiconductor chip are connected via

  Furthermore, in one semiconductor integrated circuit device of the present invention, the connection structure between the external terminal of the semiconductor chip and the wiring of the wiring board is provided with a solder or Au ball stud bump that wraps the wiring of the wiring board from above. And connecting the wiring of the wiring board and the external terminal of the semiconductor chip via the stud bump.

  Further, in one semiconductor integrated circuit device of the present invention, the connection structure between the external terminal of the semiconductor chip and the wiring of the wiring board is formed by using Al, solder, or Au wire to connect the wiring of the wiring board and the semiconductor chip. Connects to an external terminal.

Furthermore, in one semiconductor integrated circuit device of the present invention, the wiring structure of the wiring board is formed by gradually reducing the width dimension of the wiring from the end of the substrate base of the wiring board toward the tip of the wiring. The bending stress ratio α when the bending stress σ0 generated at the end of the base material is the maximum stress σ1 generated between the end of the substrate and the tip of the wiring is
α = σ1 / σ0
In particular, the bending stress ratio α when the taper length is L1, the wiring length is L2, the taper width is b1, and the wiring width is b2 is formed to have a constant width dimension from a predetermined position.
α = b1 × (L2−L1) / (b2 × L2)
In this case, the dimension and shape of the wiring are set so that the bending stress ratio α is 1.2 to 1.5.

  Furthermore, in one semiconductor integrated circuit device of the present invention, the wiring structure of the wiring board is subjected to Au plating on the surface using a conductive material as a core material.

  Furthermore, in one semiconductor integrated circuit device of the present invention, the wiring board has the wiring formed on a back surface of a substrate base material, an insulating film is formed on the back surface of the wiring, and the back surface side of the insulating film is formed. The elastic structure is disposed.

  According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor integrated circuit device comprising: forming an elastic structure on a back surface of a wiring board in which wiring is formed on the substrate base; and forming the elastic structure on the back surface of the elastic structure. Adhering the semiconductor chip so that the relative positions of the lead portion of the wiring and the external terminal of the semiconductor chip coincide with each other, connecting the lead portion of the wiring to the external terminal of the semiconductor chip, and the semiconductor chip A step of resin-sealing a connection portion between the external terminal and the wiring, a step of cutting the substrate substrate of the wiring substrate slightly outside the outer periphery of the semiconductor chip, and an insulating film on the main surface of the wiring A step of forming an opening at a position where the land portion of the wiring of the insulating film and the bump electrode are bonded, and a bump electrode bonded to the land portion of the wiring through the opening. Formation It is made of and that process.

  In particular, in the step of forming the insulating film, the opening of the insulating film is formed by defining a coating range of the material of the insulating film, or the thickness of the insulating film is formed. In the process, it is set by defining application conditions of the material of the insulating film.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1). Adopt a surface wiring structure in which an elastic structure is arranged on the back side of the substrate substrate of the wiring substrate and an insulating film is formed on the main surface of the wiring formed on the main surface of the substrate substrate. By arranging the elastic structure on the flat surface of the back surface of the substrate substrate, the elastic structure can be mounted on the substrate substrate with a voiceless and more stable and more accurate dimension. Since the shape is stable, the semiconductor chip bonding process is also stable, and assembly with a high yield can be performed.

  (2) Since the wiring on the wiring board has a multiple wiring layer structure, the signal wiring layer and the power / ground wiring layer can be separated into different layers. It becomes possible to obtain characteristics.

  (3) Since the external terminals of the semiconductor chip can be arranged in the central part or the peripheral part, and the bump electrodes connected to the external terminals can be arranged on the inner side, the outer side, or both areas from the outer periphery of the semiconductor chip. It can be applied to various types and variations of package structures.

  (4) By setting the dimensions of the end of the elastic structure on the external terminal side of the semiconductor chip and the end of the substrate substrate of the wiring board based on the component or physical characteristics of the elastic structure, the elastic structure Since the eaves of the substrate base with respect to the body can be optimized, the height variation of the bump electrode is not deteriorated, and the sealing material is not easily filled due to the wide opening sealing region of the elastic structure. Further, it is possible to prevent the wiring from being contaminated by the bleed component and the volatile component of the elastic structure.

  (5). Distance M2 between the end of the substrate base of the wiring substrate and the end of the elastic structure on the outer peripheral side of the semiconductor integrated circuit device, and distance M1 between the end of the semiconductor chip and the end of the substrate base By setting the relationship in the range of M1> M2> 0, the outer dimensions of the package can be optimized, so the outermost periphery of the package does not become a semiconductor chip, so the assembly process, socket insertion / removal, tray transport The possibility of inducing a chip crack in the middle is reduced, the circuit surface of the semiconductor chip does not come out, and the reliability can be improved. Further, the peripheral protrusions of the elastic structure after printing are the semiconductor chip Therefore, it is possible to prevent poor adhesion at the time of pasting, deterioration of the flatness of the wiring board, and reduction of reliability.

  (6). By forming the wiring of the wiring board in a shape in which the fixed portion to the substrate base and the tip portion connected to the external terminal of the semiconductor chip are displaced at least by the width of the wiring, it is S-shaped in a plane. Since it can be used as a wiring, it is possible to form a stable and suitable S-shaped lead by a simple down trajectory with a general wire bonder, so that a stable and suitable S-shaped lead can be formed, and the software has been modified. A special wire bonder is not required, a stable S-shape of the lead can be formed, and the locus of the bonding tool can be simplified, so that the tact time during bonding can be shortened.

  (7). By forming the wiring of the wiring board in a cantilever structure where one side is fixed to the substrate base material, it can be made into beam wiring, so the thickness of the notch changes like notched wiring It is possible to solve problems such as being unable to cut at the time of bonding, even if cut, it can be cut at a different part from the desired notch, or it becomes too thin and cut before the plating process of the wiring board It becomes.

  (8) By setting the end of the opening of the surface protection film on the semiconductor chip to a dimension that does not interfere with the surface protection film when the bonding tool is downed, the downside on the semiconductor chip It is possible to solve problems such as damage to the surface protective film or the semiconductor chip, contamination of the components of the surface protective film due to adhesion of the components on the lower surface of the leads, and deterioration of bonding properties.

  (9) By connecting the wiring on the notch termination side of the wiring on the wiring board to the land portion of the opposing wiring, extending in the vertical or horizontal direction in the empty area of the wiring, or connecting adjacent wirings together Since the effective area of the wiring portion can be increased, the adhesive strength between the wiring and the substrate substrate can be increased, and stable notch cutting performance can be obtained.

  (10) By forming the elastic structure in a large range over the entire circumference at least as much as the outer peripheral protrusion width formed on the elastic structure compared to the outer dimensions of the semiconductor chip, the wide elastic structure structure and Therefore, after the semiconductor chip is attached, the protrusion around the elastic structure comes out of the semiconductor chip and is bonded to the flat part of the elastic structure, so that the warping of the wiring board is kept small. In addition, because the adhesive application area is wide, it is difficult for the adhesive material to spread and non-adhered parts to occur, and evenly ooze out around the semiconductor chip, so moisture resistance and reliability can be achieved without sealing the periphery. It is possible to constitute a package excellent in the above.

  (11) When the elastic structure is divided and formed so as not to adhere to the external terminals of the semiconductor chip, the respective end portions of the opposed spaces of the divided elastic structure are formed in a groove shape. Thus, since the groove of the elastic structure can be narrowed by narrowing the metal mask suspension in the groove filling technique of the elastic structure, it is possible to improve the groove filling property of the elastic structure.

  (12) By forming a plurality of grooves formed at each end of the elastic structure, the strength of the metal mask for forming the grooves can be increased.

  (13) By forming a dam for sealing material flow prevention in advance in the groove at each end of the space facing the divided elastic structure, the groove filling performance in the sealing process can be further improved. It becomes possible.

  (14). Stud bumps are formed in advance on the external terminals of the semiconductor chip, and the external terminals of the semiconductor chip and the wiring of the wiring board are connected via the stud bumps. It is possible to solve such problems and improve the bondability by the stud bump, and further prevent damage.

  (15). By supplying solder so as to envelop the wiring of the wiring board in advance and connecting the external terminal of the semiconductor chip and the external terminal of the semiconductor chip via this solder, the improvement in the bonding property and damage in the bonding technology Can be suppressed.

  (16). Using a solder bump that wraps the wiring of the wiring board from the top, a stud bump such as Au, and connecting the wiring of the wiring board and the external terminal of the semiconductor chip via this stud bump Bondability can be improved and damage can be suppressed.

  (17). By using Al, solder or Au wire to connect the wiring board wiring and the external terminals of the semiconductor chip, it solves problems such as bondability and damage. It is possible to realize connection based on the general wire bonding concept.

  (18). The wiring width of the wiring board is gradually narrowed from the end of the substrate base of the wiring board toward the tip of the wiring, and is formed so as to have a constant width dimension from a predetermined position. By setting the size and shape of the wiring so that the ratio α is 1.2 to 1.5, a suitable S-shape can be formed by simply dropping the bonding tool vertically without returning the bonding tool. In addition, it is possible to form a stable lead S-shape without requiring a special wire bonder modified by software, and to simplify the trajectory of the bonding tool, so that the tact time during bonding can be shortened.

  (19). When the wiring structure of the wiring board is made of a conductive material as a core material and only Au plating is applied to the surface, for example, when Ni plating is applied between the core material of a conductive material such as Cu and Au plating. Compared to the lower hardness and brittleness of the lead, the lead itself is less likely to crack, and damage to the semiconductor chip that is the bonding surface can be reduced.

  (20). The back wiring is formed by forming the wiring on the back surface of the substrate substrate of the wiring substrate, forming the insulating film on the back surface of the wiring, and disposing the elastic structure on the back surface side of the insulating film. Since it can be an insulating film structure, the elastic structure can be prevented from coming into direct contact with the wiring, and the elastic structure can also be prevented from coming into contact with the roughened surface of the substrate substrate. Bleeding can be suppressed, and furthermore, an insulating film is applied to the wiring surface with unevenness, so that the surface is flattened, and it is possible to avoid problems such as void entrainment during the formation of the elastic structure.

  (21). In the front wiring structure, when the opening of the insulating film is formed by defining the coating range of the insulating film material, the opening is opened by machining in the substrate substrate of the wiring substrate of the back wiring structure Compared with, the hole diameter machining accuracy can be further improved.

  (22) In the surface wiring structure, by setting the insulating film thickness by defining the coating conditions of the insulating film material, it is possible to stably apply with a thinner thickness than the substrate substrate. Since bump lands can be formed with a small diameter and a high density, smaller bump electrodes can be satisfactorily bonded.

  (23) Since the front wiring structure can reduce the arrangement pitch of the bump electrodes as compared with the back wiring structure, it is possible to constitute a semiconductor package having higher density output terminals.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIGS. 3 and 4 are mounting substrates of the semiconductor integrated circuit device. FIG. 5 is a flowchart showing an assembly process of the semiconductor integrated circuit device, and FIGS. 6 to 58 and FIGS. 76 to 81 are diagrams of the semiconductor integrated circuit device of the first embodiment. It is a figure for the comparison explanation with the semiconductor integrated circuit device which is a characteristic and a comparative example which this inventor examined, and explanation of these figures is explained for each technical item mentioned below.

  First, the configuration of the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS.

  The semiconductor integrated circuit device according to the first embodiment is, for example, a 40-pin ball grid array type semiconductor package, excluding a semiconductor chip 1 having a plurality of bonding pads formed on the main surface and a bonding pad forming portion. A flexible wiring board in which an elastomer 2 (elastic structure) bonded on the main surface of the semiconductor chip 1 and a wiring bonded on the main surface of the elastomer 2 and connected at one end to the bonding pad of the semiconductor chip 1 are formed. 3 (wiring board), a solder resist 4 (insulating film) formed on the main surface of the flexible wiring board 3, and a solder resist 4 formed on the main surface of the solder resist 4, and wiring through the opening of the solder resist 4 The solder bump 5 (bump electrode) is connected to the other end of the semiconductor chip 1 and the bonding portion of the semiconductor chip 1 is a sealing material 6 such as a resin. It has become a more covered package structure.

  The semiconductor chip 1 has, for example, a center pad structure as shown in FIG. 1, and a plurality of bonding pads 7 (external terminals) are formed in a line at the center in the longitudinal direction. Are lined up. In this semiconductor chip 1, predetermined integrated circuits such as a memory circuit and a logic circuit are formed on a semiconductor substrate such as silicon, and bonding pads 7 made of a material such as Al are provided as external terminals of these circuits. Yes.

  The elastomer 2 is made of an elastic material such as a silicone resin, for example, and is divided into two at both ends in the longitudinal direction so as to exclude a portion where the bonding pads 7 are formed on the main surface of the semiconductor chip 1. 8 is bonded. The elastomer 2 is provided in order to relieve stress concentration on the solder bump 5 caused mainly by the difference in thermal expansion coefficient between the semiconductor chip 1 and the package mounting board in a temperature characteristic test or the like.

  For example, as shown in FIG. 2, the flexible wiring board 3 is composed of a tape 9 (substrate base material) serving as a base material of the flexible wiring board 3 and a wiring 10 bonded on the main surface of the tape 9. The lead 11 at one end of the wiring 10 is connected to the bonding pad 7 of the semiconductor chip 1, and the bump land 12 at the other end is connected to the solder bump 5. In the flexible wiring board 3, the back surface side of the tape 9 is bonded to the elastomer 2, and the solder resist 4 is formed on the main surface side of the wiring 10.

  The tape 9 constituting the flexible wiring board 3 is made of a material such as polyimide resin, and the wiring 10 is made of a material such as Cu as a core material. In the lead 11 portion of the wiring 10, a Ni plating layer made of a material such as Ni is formed on the front and back surfaces of the core material, and an Au plating layer made of a material such as Au is formed on the surface of the Ni plating layer. Yes.

  The solder resist 4 is made of an insulating material such as a photosensitive epoxy resin, and the solder bumps 5 are formed on the main surface of the wiring 10 of the flexible wiring board 3 through the openings of the solder resist 4. It is formed in a predetermined range excluding a connecting portion connected to the.

  The solder bump 5 is made of a material such as an alloy mainly composed of Pb—Sn, Pb—Sn, or the like, and is connected to the bump land 12 of the wiring 10 constituting the flexible wiring board 3. The solder bumps 5 are divided into regions on both sides of the bonding pads 7 of the semiconductor chip 1 and are arranged in two rows.

  The semiconductor integrated circuit device configured as described above is a semiconductor integrated circuit device of a general package 14 such as a memory controller as a semiconductor integrated circuit device of a chip size package 13 such as a DRAM as shown in FIGS. At the same time, it is mounted on a mounting board 15 such as a memory card, and is detachably attached to a portable device such as a mobile phone or a handy-type personal computer through an external connection terminal 16.

  Next, with regard to the operation of the first embodiment, an outline of the assembly process of the semiconductor package will be described first based on the process flow of FIG.

  First, prior to assembling a semiconductor package, for example, a wiring 10 is formed on a tape 9 and a flexible wiring substrate 3 having an lead 11 formed by etching a part of the wiring 10, an elastomer 2, a predetermined integrated circuit A semiconductor chip 1 provided with bonding pads 7 as external terminals, a sealing material 6, flux, solder for forming solder balls 17, and the like are prepared.

  This flexible wiring board 3 is formed by bonding a thin metal on a tape 9 made of polyimide resin, such as a TAB (tape automated bonding) tape, and forming a necessary pattern on the metal using photographic technology. After the resist is formed, the necessary wiring 10 (including the lead 11) is formed by etching, and the surface thereof can be plated with Ni and Au.

  Then, for example, the elastomer 2 is formed on the tape 9 of the flexible wiring board 3 to a thickness of 50 to 150 μm by printing, and further, for example, a silicone adhesive 8 is applied and printed on the surface of the elastomer 2 ( Steps 501 and 502). Here, the elastomer 2 is not necessarily printed, but a film formed in advance may be cut into a predetermined shape and adhered to the back surface of the tape 9 with the adhesive 8.

  Further, the semiconductor chip 1 is aligned on the tape 9 of the flexible wiring board 3 by aligning the leads 11 at one end of the wiring 10 of the flexible wiring board 3 and the bonding pads 7 of the semiconductor chip 1 so that the relative positions thereof coincide with each other. Is adhered and pasted on the elastomer 2 printed on (step 503).

  Then, the semiconductor chip 1 and the tape 9 of the flexible wiring board 3 are reversed while being attached via the elastomer 2, and in the lead bonding process, the lead 11 is made S by the bonding tool 18 as shown in the cross section of FIG. The lead 11 and the bonding pad 7 are connected by, for example, a technique such as ultrasonic thermocompression bonding while being deformed into a letter shape and dropped onto the bonding pad 7 of the semiconductor chip 1 (step 504).

  Subsequently, in a sealing step, the lead bonding portion between the bonding pad 7 of the semiconductor chip 1 and the lead 11 of the flexible wiring board 3 is resin-sealed by applying a sealing material 6 such as an epoxy resin from a dispenser 19. Then, the reliability of the joint between the semiconductor chip 1 and the flexible wiring board 3 is increased (step 505).

  Thereafter, in the cutting process of the flexible wiring substrate 3, the outer edge of the tape 9 is cut slightly outside the edge of the semiconductor chip 1 to form a package outline of a CSP (chip size package or chip scale package) (step 506).

  Furthermore, in the bumping step of the solder bump 5, the solder ball 17 is joined to the bump land 12 of the wiring 10 of the corresponding flexible wiring board 3 to form the solder bump 5, and finally, after selection and marking, the present embodiment 1 is completed (steps 507 and 508).

  In this semiconductor package assembly process, the tape cutting process (step 506) and the bumping process (step 507) may be reversed.

  As a result, in the case of the first embodiment, the bonding pads 7 are concentratedly arranged in a line at the center of the semiconductor chip 1, and the semiconductor chips connected from the bonding pads 7 via the wirings 10 of the flexible wiring board 3. 1 has a semiconductor package structure called a so-called fan-in-center pad structure in which solder bumps 5 are provided in a region inside the outer periphery of 1.

  Next, the characteristics of the package structure of the semiconductor integrated circuit device according to the first embodiment are compared with the package structure as a technique studied by the present inventor, and the structure and process are included based on FIGS. Will be described in order.

1. In the technical explanation of the front wiring structure, FIG. 6 is a cross-sectional view of the main part showing the front wiring structure, FIG. 7 is a cross-sectional view of the main part showing the back wiring structure, and FIG. is there.

  In the package structure of the first embodiment, as shown in an enlarged view in FIG. 6, the elastomer 2 is adhered to the back surface (semiconductor chip 1 side) of the tape 9 of the flexible wiring substrate 3, and the main surface of the wiring 10. It has a so-called surface wiring structure in which a solder resist 4 is formed on the solder bump 5 side. On the other hand, in the technique examined by the present inventor, as shown in FIG. 7, the elastomer 2 is bonded to the back surface of the wiring 10 and the tape 9 is formed on the solder bump 5 side. It has a wiring structure.

  Therefore, in the studied back wiring structure, the bump land 12 to which the solder bump 5 is bonded is formed by punching the tape 9 made of a material such as polyimide resin with a punch or the like, for example. In the wiring structure, a solder resist 4 made of a material such as a photosensitive epoxy resin is applied to the main surface of the wiring 10, and a bump land 12 having a desired size is formed at a desired position by photographic methods such as exposure and development. Therefore, the following advantages can be expected.

  (1). Since the openings for the solder bumps 5 are formed by exposure and development of the solder resist 4, more holes are formed than when the openings are opened by machining in the tape 9 of the flexible wiring board 3 of the back wiring structure. Diameter machining accuracy can be increased.

  (2) The tape 9 has a minimum practical thickness of about 50 μm, whereas the solder resist 4 can be stably applied at a thickness of about 10 to 20 μm depending on the application conditions. Smaller solder balls 17 can be satisfactorily joined.

  (3) Since the front wiring structure can reduce the arrangement pitch of the solder bumps 5 as compared with the back wiring structure, a semiconductor package having output terminals of the solder bumps 5 with higher density can be configured.

  (4) Since the elastomer 2 is disposed on the flat surface of the back surface of the tape 9, the elastomer 2 can be mounted (applied or affixed) on the tape 9 with a voicelessly more stably. Further, since the dimension and shape of the elastomer 2 are stabilized, the bonding process of the semiconductor chip 1 is also stabilized, and assembly with a high yield can be performed.

  As described above, in the technology of the back wiring structure, problems such as formation of an opening portion of the flexible wiring board 3 in the tape 9 and adhesion between the wiring 10 of the flexible wiring board 3 and the elastomer 2 occur. In the first embodiment, these problems can be solved by adopting the surface wiring structure.

  Further, in the wiring structure of the flexible wiring board 3, in addition to the single-sided wiring structure as shown in FIG. 6, for example, a double-sided wiring structure as shown in FIG. Can be used, and can be widely applied to a multi-layer wiring structure having three or more layers.

  In the example of FIG. 8, for example, the first wiring 20 is a signal wiring, the second wiring 21 is a ground plane, and the electrical connection between the second wiring 21 and the solder bump 5 or the first wiring 20 is via via holes 22. Done. Such a structure has an advantage that excellent electrical characteristics such as noise resistance can be obtained.

2. In this technical explanation of optimizing the tape for the elastomer, FIG. 9 is a plan view showing the window opening, FIG. 10 is a sectional view showing the window opening in FIG. 9, and FIG. 11 is the window opening. It is sectional drawing for the dimension description of the edge part of a part and a semiconductor chip.

  The package structure of the first embodiment has a BGA (ball grid array) structure in which solder bumps 5 are arranged in a matrix arrangement on the main surface of the flexible wiring board 3 as shown in FIG. In this example, as shown in FIG. 10, the semiconductor chip 1 has a center pad arrangement, and a window opening 23 is provided vertically in the center. In the final structure, this part and the peripheral edge of the semiconductor chip 1 are connected to the sealing material 6. With resin sealing, it has a structure with high moisture resistance and reliability.

  By the way, in the technique examined by the present inventors, the end of the elastomer 2 (window opening 23 side) is brought close to the edge of the tape 9, that is, the end of the elastomer 2 on the bonding pad 7 side of the semiconductor chip 1 in FIG. When the dimension L1 between the tape and the end portion of the tape 9 is reduced, the lead 11 is contaminated by the bleed component and volatile component of the elastomer 2.

  On the other hand, if the dimension L1 is increased, that is, if the dimension L2 is excessively retracted from the edge of the tape 9, the dimension L2 between the end portion of the elastomer 2 and the solder bump 5 becomes small, and the elastomer 2 disappears under the innermost solder bump 5. It is conceivable that the height variation of the solder bump 5 is deteriorated, the sealing region of the window opening 23 is widened, and the sealing material 6 is difficult to fill.

  On the other hand, in the first embodiment, an appropriate dimension L1 is selected, and the end of the elastomer 2 is arranged at an optimum position between the end of the tape 9 and the solder bump 5, thereby providing these. The problem can be solved at the same time.

  That is, since the window opening 23 has the above-described problems, the dimensions are defined as follows. For example, in this example, it is assumed that the printing accuracy of the elastomer 2 is about ± 100 μm. Therefore, if the dimension L1 is set to 100 μm or less, it will protrude from the tape 9 due to printing misalignment, so at least the printing accuracy (100 μm) is required.

  Furthermore, since the contamination of the lead 11 due to the bleed component or volatile component of the elastomer 2 has no problem if it is separated by about 300 μm as a result, the minimum value is 300 μm, for example, but the elastomer 2 having low contamination and bleed properties is used. Alternatively, if measures such as cleaning of contaminated parts are taken, a design close to the minimum value of 100 μm can be achieved.

  As described above, by selecting an appropriate dimension L1 as in the first embodiment, the lead 11 is prevented from being contaminated by the bleed component and volatile component of the elastomer 2, and the height variation of the solder bump 5 is stabilized. The sealing region of the window opening 23 can be easily filled.

3. Optimization of Package External Dimensions In this technical description of package external dimension optimization, FIG. 11 is a sectional view for explaining the dimensions of the window opening and the edge of the semiconductor chip described above, and FIG. 12 is an elastomer after printing. FIG. 13 is a cross-sectional view showing the warp of the tape after the semiconductor chip is attached.

For example, in the technique studied by the present inventors, in FIG. 11, the distance between the end of the semiconductor chip 1 and the end of the tape 9 of the flexible wiring board 3 on the outer peripheral side of the package is M1, and the end of the elastomer 2 is If the distance from the end of the tape 9 is M2,
(1) When M1 <0, since the outermost periphery of the package is the semiconductor chip 1, there is a high possibility of inducing cracks in the semiconductor chip 1 during the assembly process, socket insertion / removal, tray conveyance and the like.
(2) In the case of M1 <0, M2> 0, since the circuit surface of the semiconductor chip 1 goes out, there is a problem in reliability, and sealing can be performed to prevent this, but the number of processes is increased. Leads to.
(3). When M1-M2 <0, the peripheral protrusions of the printed elastomer 2 shown in FIG. 12 are applied to the bonding portion of the semiconductor chip 1 as shown in FIG. This causes deterioration of the flatness of the wiring board 3 and deterioration of reliability.
(4) When M2 = 0, it is necessary to cut the elastomer 2, which causes problems such as difficulty in cutting.

  On the other hand, in the first embodiment, the relationship between the distance between the edge of the semiconductor chip 1 or the edge of the elastomer 2 and the edge of the tape 9 is M1> M2> 0. The point can be solved. That is, in the dimension explanatory diagram showing the edge portion of the package in FIG. 11, the cutting error in the tape cutting process for determining the final outer shape is about 100 μm. It is desirable to do.

  By the way, the cross-sectional shape after the elastomer 2 is formed by printing and cured by baking is as shown in FIG. 12, and in the case of a material having a high degree of thixotropy, it is pulled by the mask when the plate is released after printing. Part tends to be high. For example, when the semiconductor chip 1 is attached under the condition of M1 <M2 where the end of the semiconductor chip 1 is smaller than the end of the elastomer 2, the surface of the tape 9 becomes the cross-sectional shape of the elastomer 2 as shown in FIG. A problem that warps by itself occurs.

  In order to prevent this, it is effective that M1> M2 and the high part around the elastomer 2 is allowed to escape from the semiconductor chip 1. For example, since the width of the protrusion is around 200 μm, (M1-M2) is 240 μm. The distance M1 is preferably about 360 μm from the distance M2 = 100 μm.

  By cutting the outer peripheral tape 9 in this way, there are few external errors, and it is not necessary to change peripheral jigs such as sockets and trays even if the semiconductor chip 1 is slightly changed in size. There are advantages.

  As described above, in the first embodiment, the occurrence of cracks and chips in the semiconductor chip 1 can be avoided, and the cutting margin in the cutting process can be increased. Furthermore, all the circuit surfaces of the semiconductor chip 1 can be disposed under the elastomer 2, and there are advantages such as improved moisture resistance and no need to seal the outer periphery.

4). Plane S-shaped lead In this technical description of the plane S-shaped lead, FIG. 14 is a plan view showing the plane S-shaped lead, FIG. 15 is a sectional view taken along arrow B in FIG. 14, and FIG. FIG. 17 is a cross-sectional view showing the trajectory of the bonding tool when forming a standard S-shaped lead, and FIG. 18 is a cross-sectional view showing the trajectory of the bonding tool when forming a flat S-shaped lead.

  For example, in the formation technique of the standard S-shaped lead 24 investigated by the present inventor, a straight notch lead or beam lead as shown by a dotted line in FIG. 14 is used, and after bonding, as shown by a thin line in FIG. In order to form a sag (S-shape) sufficient to withstand thermal deformation, the lead 11 is once lowered to a level on the semiconductor chip 1 as shown in FIG. It is necessary to move along a special bonding tool trajectory 25 of downing and joining again, and a dedicated wire bonder may be required.

  In contrast, in the first embodiment, when the wiring 10 is formed on the tape 9 of the flexible wiring board 3, the lead 11 of the wiring 10 is not a straight line, but as shown in FIG. The above-mentioned problem can be solved by creating an S-shaped flat S-shaped lead 26 in which the base portion and the bonding portion at the tip are shifted at least by the width of the lead 11.

  In this way, the flat S-shaped lead 26 has a lead shape stretched as shown in FIG. 15 by the bonding tool trajectory 25 by a simple downstroke with a general wire bonder shown in FIG. 18, but is shown in FIG. In addition, since the sag due to the original planar S-shape can be formed, a stable and preferable S-shaped planar S-shaped lead 26 can be formed.

  As a result, it is possible to form a stable S-shaped flat S-shaped lead 26 without using a specially modified wire bonder, and to simplify the bonding tool trajectory 25, so that the effect of shortening the tact time during bonding is also expected. it can.

5). In this technical description of the beam lead, FIG. 19 is a plan view for explaining the notch lead and the beam lead, FIG. 20 is a plan view showing the notch lead in part A of FIG. 19, and FIG. 21 is a plan view showing the beam lead. FIG.

  For example, in the technique studied by the present inventor, as shown in FIG. 20 which is an enlarged view of the lead 11 in FIG. 19, the lead 11 has a notch 27 such as a V-shaped cut in the cut portion. At the time of bonding, the inner side of the notch 27 is pushed down by the bonding tool 18, and the lead 11 is cut at the notch 27. However, the thickness of the notch 27 changes due to the etching variation of the wiring 10 in the manufacturing process of the flexible wiring board 3, and it cannot be cut at the time of bonding.

  Moreover, even if it can be cut, it may be cut at a portion different from the desired notch 27, or it may become too thin and cut before the plating process of the flexible wiring board 3, resulting in problems such as not being plated. .

  On the other hand, in the first embodiment, as shown in FIG. 21, one end is fixed to the tape 9 of the flexible wiring board 3, and the cantilever with the notch 27 on the cut side is opened. By adopting a structure, that is, a so-called beam lead 28, the problems at the time of cutting the lead 11 can be solved.

6). Bonding Pad Peripheral PIQ (Passivation) Dimensions In the technical description of the bonding pad peripheral PIQ dimensions, FIG. 22 is a cross-sectional view showing a lead bonding part, FIG. 23 is a plan view showing the lead bonding part, and FIG. FIG. 25 is a cross-sectional view showing a bonding portion with improved passivation opening dimensions, and FIG. 26 is a plan view showing a bonding portion of a bidirectional lead.

  For example, in the technique studied by the present inventors, in the bonding sequence as shown in FIGS. 22, 23, and 24, as shown by the bonding tool trajectory 25, the lead 11 is once dropped down until it passes on the semiconductor chip 1. Since it is laterally shifted and then down-bonded onto the bonding pad 7 of the semiconductor chip 1, the passivation 29 on the semiconductor chip 1 or the semiconductor chip 1 therebelow is damaged by the first down-swing. It is conceivable that a component of the passivation 29 adheres to the bonding portion on the lower surface of the lead 11 and is contaminated to cause problems such as deterioration of bonding properties.

  On the other hand, in the first embodiment, at least the distance L3 from the opening edge of the bonding pad 7 shown in FIGS. 22, 23 and 24 to the edge of the passivation 29 on the bonding pad 7 side is at least bonded. The above-described problems can be solved by enlarging the passivation opening 30 in a range where the lead 11 does not interfere with the passivation 29 on the side where the tool 18 is downed and improving it as shown in FIG.

  That is, in FIG. 24, for example, in the example of the semiconductor chip 1 such as a memory, the dimension L3 is about 25 μm. In addition, since the size of the bonding pad 7 is, for example, 100 μm square and the tip dimension of the bonding tool 18 is equal to or less than that, the retraction amount L3 of the passivation 29 in FIG. 25 is desirably about 125 μm or more, for example.

  As a result, the passivation 29 on the semiconductor chip 1 or the semiconductor chip 1 is not damaged, and the components of the passivation 29 do not adhere to the bonding portion on the lower surface of the lead 11 and are contaminated. can do.

  26, even when the lead 11 extends in both directions, the distance from the opening edge of the bonding pad 7 to the edge of the passivation 29 on the bonding pad 7 side at least on the side where the bonding tool 18 is pushed down. It can respond similarly by enlarging. The enlargement between the edges does not pose a problem even when applied to the opposite side to the extent that the circuit surface of the semiconductor chip 1 is not exposed.

7). Improvement of Anchor Wiring In the technical explanation of the improvement of anchor wiring, FIG. 27 is a plan view showing standard anchor wiring, and FIG. 28 is a plan view showing improved anchor wiring.

  For example, in the technique studied by the present inventor, in the pattern of the standard anchor wiring 31 on the terminal end side of the notch 27 as shown in FIG. 27, when the notch 27 is formed thicker than the design value, the portion of the notch 27 However, there is a possibility that the adhesive strength between the wiring 10 and the tape 9 in the standard anchor wiring 31 beyond that is not broken and the portion of the standard anchor wiring 31 is peeled off from the tape 9.

  On the other hand, in the first embodiment, as shown in FIG. 28, the enlarged anchor wiring 32 that increases the effective area of the anchor wiring portion on the terminal end side is used, whereby the adhesive strength between the wiring 10 and the tape 9 is increased. And a stable cutability of the notch 27 can be obtained.

That is, in FIG. 28, an improvement example of the enlarged anchor wiring 32 is shown.
(1). The enlarged anchor wiring 32 is connected to the bump land 12 of the opposing wiring 11,
(2) Extending the enlarged anchor wiring 32 in the vertical direction in the empty space of the wiring 11,
(3) Extending the expanded anchor wiring 32 in the horizontal direction in the empty space of the wiring 11,
(4). Connect adjacent enlarged anchor wirings 32,
In any case, by increasing the substantial area of the portion of the enlarged anchor wiring 32, the cutting property of the notch 27 can be stabilized by increasing the adhesive strength between the wiring 10 and the tape 9.

8). Wide Elastomer Structure In this technical description of the wide elastomer structure, FIG. 29 is a perspective view showing the structure of a standard elastomer, FIG. 30 is a perspective view showing a state of attaching a semiconductor chip in the standard elastomer, and FIG. 31 shows the structure of the wide elastomer. FIG. 32 is a perspective view showing a state where a semiconductor chip is attached with a wide elastomer, and FIG. 33 is a cross-sectional view showing a state where the semiconductor chip is attached with a wide elastomer.

  For example, in the technique studied by the present inventor, the elastomer 2 is divided and bonded to both sides of the bonding pad 7 of the semiconductor chip 1, and in the structure using the standard elastomer 33 as shown in FIGS. If the area of the elastomer 2 is smaller than that of the semiconductor chip 1 as described above, the flexible wiring board 3 is warped due to the influence of peripheral protrusions, and this warpage is a problem when the solder bumps 5 are formed and when the board is mounted. It is possible to become.

  On the other hand, in the first embodiment, in the structure using the wide elastomer 34 larger than the outer shape of the semiconductor chip 1 as shown in FIG. 31, after the semiconductor chip 1 is attached, as shown in FIGS. Since protrusions around the wide elastomer 34 come out of the semiconductor chip 1 and the semiconductor chip 1 is bonded to a substantially flat portion of the wide elastomer 34, the warp of the flexible wiring board 3 can be suppressed to a small level.

  Furthermore, as shown in FIG. 33, since the application area of the adhesive material 8 can be widened, the adhesive material 8 does not spread and hardly becomes non-adhered, and the adhesive material 8 oozes out evenly around the semiconductor chip 1. Thus, the adhesive exudation 35 can be formed, so that a package having excellent moisture resistance and reliability can be formed without sealing the periphery.

  That is, the width of the protrusion around the wide elastomer 34 varies depending on the physical property value of the material, but is, for example, about 200 to 300 μm. Therefore, in the first embodiment, as shown in FIG. The wide elastomer 34 is formed in a large range over the entire circumference not less than the protrusion width.

  If the wide elastomer 34 is formed sufficiently wide, the flatness is improved. However, if the tape 9 is to be cut at the outer periphery of the semiconductor chip 1, the tape 9 is cut together with the wide elastomer 34 at the cutting line 36, and the package is cut. It is necessary to specify the outer shape.

  As described above, by using the wide elastomer 34 larger than the outer shape of the semiconductor chip 1, it is possible to suppress the warp of the flexible wiring board 3, stabilize the adhesiveness of the semiconductor chip 1, and improve the moisture resistance and reliability of the package. Can be improved.

9. Elastomeric groove filling technology In the description of the elastomeric groove filling technology, FIGS. 31 and 32 are perspective views showing the structure of the wide elastomer and the semiconductor chip attached as described above, and FIG. 34 is a semiconductor chip in a standard elastomer. FIG. 35 is a sectional view thereof, FIG. 36 is a perspective view showing the structure after the semiconductor chip is attached with a wide elastomer, FIG. 37 is a sectional view thereof, and FIG. 38 is a metal mask. FIG. 39 is a plan view showing a metal mask of a standard elastomer, FIG. 40 is a plan view showing a metal mask of a wide elastomer, and FIG. 41 is a plan view showing a printing shape of a plurality of hanging wide elastomers. FIG. 42 is a plan view showing a potting position for filling a groove of a wide elastomer.

  For example, in the technology studied by the present inventors, in the structure of the standard elastomer 33 as shown in FIGS. 34 and 35, when the elastomer 2 is configured by printing with the metal mask 37 as shown in FIG. Since the hanging portion 39 of the printing area opening 38 of the metal mask 37 always exists, the groove 40 (space) surrounded by the walls of the semiconductor chip 1 and the elastomer 2 remains under the tape hanging portion.

  Therefore, if the window opening 23 is resin-sealed in such a structure that the groove 40 remains in the space between the semiconductor chip 1 and the elastomer 2, the sealing material 6 leaks from the groove 40. It is necessary to seal the window opening 23 after sealing by such a method.

  Thus, the concept of printing of the metal mask 37 is, for example, a metal mask having a printing area opening 38 only in a portion to be printed as shown in FIG. 39 in the case of the standard elastomer 33 and in FIG. 40 in the case of the wide elastomer 34. 37 is positioned and arranged at a predetermined position of the flexible printed circuit board 3 which is the printed material, and the elastomer 2 which is the printed material is applied by the thickness of the metal mask 37 by the squeegee 41 so that a desired thickness is obtained in a desired range. The elastomer 2 is formed.

  Therefore, in the first embodiment, the wide elastomer 34 as shown in FIG. 31 is printed with the metal mask 37 as shown in FIG. 40. In this case, the suspended portion of the printing area opening 38 of the metal mask 37 is printed. By printing the elastomer 2 with a thinned portion 39, the groove 40 surrounded by the semiconductor chip 1 and the wall of the elastomer 2 can be thinned. For example, the minimum value of the width of the groove 40 defined by the strength of the hanging portion 39 of the metal mask 37 is about 200 μm.

  Further, in the case of the structure in which the adhesive material 8 is applied to the main surface of the elastomer 2 and the semiconductor chip 1 is attached, a sufficient amount of the adhesive material is obtained as shown in FIGS. 32, 36 and 37 described above. 8 is applied, excess adhesive 8 fills the groove 40 by the pressure at the time of pasting, and the window opening 23 can be made a closed space. Can be sealed.

  Furthermore, in order to improve the groove filling property, the hanging portion 39 of the metal mask 37 may be narrowed to narrow the groove 40. However, the problem that the strength of the metal mask 37 is lowered becomes a side effect. Therefore, as shown in FIG. 41, it is possible to increase the strength of the metal mask 37 by increasing the number of the grooves 40 without changing the width of the grooves 40 by using a plurality of hanging portions 39 on each side. It is.

  Furthermore, for the purpose of improving the groove filling property, as shown in FIG. 42, for example, a resin, an adhesive or the like is previously potted at a potting position 42 of the groove 40 of the elastomer 2 immediately before the semiconductor chip 1 is attached. If a dam for preventing the flow is formed, the groove filling property can be further improved.

  Further, even when the semiconductor chip 1 is pasted and bonded and potted before potting of the window opening 23 as in the studied technique, sealing is possible if the width of the groove 40 is narrowed. Sex can also be improved dramatically.

  As described above, it is possible to improve the groove filling performance by narrowing the hanging portion 39 of the metal mask 37 and narrowing the groove 40 of the elastomer 2, and further forming a plurality of grooves 40 or pre-setting at the potting position 42. By forming the sealing material flow stop dam, the groove filling performance can be further improved.

10. Inner Lead Bonding Technology In the explanation of this inner lead bonding technology, FIG. 43 is a sectional view showing a bonding portion by standard lead bonding, FIG. 44 is a sectional view showing a bonding portion using stud bumps, and FIGS. 45 and 46 are soldering. 47 and 48 are sectional views and perspective views showing lead connections using solder or Au balls, and FIG. 49 is a sectional view showing connections using Al or solder wires. FIG. 50 is a cross-sectional view showing connection using Au wires.

  For example, in the technique examined by the present inventors, in the bonding structure as shown in FIG. 43, the lead 11 grown with Au plating is directly attached to the bonding pad 7 and ultrasonic thermocompression bonding is performed. In this case, if the bonding conditions are bad or the shape of the bonding tool 18 is bad, problems such as low bonding strength and damage to the bonding pads 7 or the like may occur.

  On the other hand, in the first embodiment, by adopting means in the following bonding form, the bonding condition and the damage caused by the bonding condition as described above, the shape of the bonding tool 18, etc. The problem can be solved.

  That is, FIG. 44 shows an example in which the stud bump 43 is used. In this example, the semiconductor chip 1 having the stud bumps 43 previously formed on the bonding pads 7 of the semiconductor chip 1 by a method such as plating or ball bonding is used. It has a structure that improves the damage and prevents damage.

  45 and 46 show connection examples of the lead 11 using the solder 44, and show a connection form in which the lead 11 is wrapped with the solder 44. FIG. This example is a technology of a connection structure that connects a bonding pad 7 made of Al or the like of the semiconductor chip 1 and an electrode of a tape 9 such as TAB that becomes a CSP substrate. As a method of supplying the solder 44 at this time, there is a method of connecting the solder 44 to the bonding pad 7 of the semiconductor chip 1 by using the tape 9 already interposed so as to wrap the leads 11 of the tape 9.

  As a connection method at this time, in the method of connecting by pressurizing and heating using a bonder, the surface of the semiconductor chip 1 in contact with the bonding pad 7 of the semiconductor chip 1 is formed as much as possible with the shape of the solder 44 interposed in the tape 9 such as TAB. It is desirable to make it flat. In the connection method using a reflow furnace, solder paste or flux is interposed on the surface of the bonding pad 7 of the semiconductor chip 1 so as to contact the solder 44 of the tape 9 such as TAB.

  Next, when the solder 44 is supplied using a solder paste, the solder paste is interposed on the surface of the bonding pad 7 of the semiconductor chip 1 by printing or using a syringe. At this time, the tape 9 such as TAB may be bonded before or after, but it is assumed that the lead 11 of the tape 9 contacts the solder 44 when the tape 9 is bonded to the semiconductor chip 1. Become.

  47 and 48 are characterized in that a lead 11 of a tape 9 such as TAB is wrapped from above using a solder or a stud bump such as an Au ball 45 and connected to the bonding pad 7 of the semiconductor chip 1. Connection technology.

  FIG. 49 shows an example in which the wiring 10 of the flexible wiring board 3 and the bonding pad 7 of the semiconductor chip 1 are connected using Al or solder wire 46. Further, FIG. 50 shows an example in which the wiring 10 of the flexible wiring board 3 and the bonding pad 7 of the semiconductor chip 1 are connected using Au wires 47. In such a connection example, the connection can be made not by inner lead bonding such as TAB but by a general wire bonding concept.

11. Lead design technology capable of forming S-shape without tool return In the explanation of lead design technology capable of forming S-shape without tool return, FIG. 17 shows the locus of the bonding tool when forming the standard S-shape lead described above. 51 is a perspective view for explaining lead design, FIG. 52 is a perspective view showing lead deformation after bonding, FIG. 53 is an explanatory view showing the relationship between lead dimensions and bending stress ratio, and FIGS. FIG. 80 is a cross-sectional view showing a lead deformation shape corresponding to the bending stress ratio.

  For example, in the technique studied by the present inventor, as described in the technique for forming the planar S-shaped lead 26, the bonding tool 18 is laterally shifted to form the S-shaped lead 11 as shown in FIG. That is, a special bonding tool locus 25 including a tool return is necessary.

  On the other hand, in the first embodiment, if the dimensions of the lead 11 as shown in FIG. 51 are as shown in FIG. 53, for example, the bending stress ratio α is a desired 1.2 to 1. 52, a suitable S-shape of the lead 11 as shown in FIG. 52 can be formed simply by vertically dropping the bonding tool 18 without a tool return. In FIG. 52, 48 is a tape end, 49 is a tape side corner, and 50 is a chip side corner.

  For example, in the example of the embodiment (1), the bending stress ratio α = in the dimensions of taper length L1 = 100 μm, wiring length L2 = 380 μm, taper width b1 = 65 μm, lead width b2 = 38 μm, lead thickness h = 18 μm. 1.26. Similarly, it is 1.25 in the example of (2), 1.26 in the example of (3), 1.31 in the example of (4), and 1.46 in the example of (5).

  On the other hand, in the studied technique, for example, in the example of (1), the taper length L1 = 100 μm, the wiring length L2 = 280 μm, the taper width b1 = 60 μm, the lead width b2 = 38 μm, and the lead thickness h = 18 μm. The bending stress ratio α is 1.02 outside the range of 1.2 to 1.5, and is 1.13 in the example of (2).

  As described above, when the bending stress ratio α is in the range of 1.2 to 1.5, the bending stress is concentrated on the intermediate portion of the lead 11 during the wiring operation, so that a favorable wiring state in which the bending is gently performed is obtained. On the other hand, when the bending stress ratio α is less than 1.2 as in the studied technique, the bending stress is concentrated on the tape end 48 of the lead 11, so that it is stretched, and when it exceeds 1.5, Since the bending stress is concentrated only in the middle part of the lead 11 and the curvature radius is small, it cannot be said that the wiring state is good.

  Here, the lead deformation shape according to the specific bending stress ratio α is shown in FIGS. First, when the bonding tool 18 is simply lowered vertically with respect to the initial lead shape before wiring shown in FIG. 76, for example, in the wiring operation of α <0.9, the lead 11 is bent to the tape end 48. Since stress is concentrated, the wiring state is extremely stretched as shown in FIG. For this reason, since the high repetitive stress is applied to the lead 11 during the temperature cycle after wiring, the fatigue life is extremely shortened.

  Further, in the case of the wiring operation of 0.9 ≦ α <1.2 as in the technique studied by the present inventors, bending stress concentrates on the tape end 48 of the lead 11, so that a little as shown in FIG. 78. It becomes a stretched wiring state. For this reason, since the high repetitive stress is applied to the lead 11 during the temperature cycle after wiring, the fatigue life is shortened.

  On the other hand, when the wiring operation is 1.2 ≦ α ≦ 1.5 as in the first embodiment, the bending stress is concentrated in the intermediate portion of the lead 11, so that it is moderate as shown in FIG. The wiring state is bent. For this reason, since the high repetitive stress does not act on the lead 11 during the temperature cycle after wiring, the fatigue life is extended.

  Further, in the wiring operation of 1.5 <α with a large bending stress ratio, the bending stress concentrates only on the intermediate portion of the lead 11, so that the wiring state has a small curvature radius as shown in FIG. For this reason, since the initial strength of a bending part falls, the fatigue life at the time of the temperature cycle after wiring becomes short.

  As a result, by setting the bending stress ratio in the range of 1.2 ≦ α ≦ 1.5 as in the first embodiment, an optimal wiring state in which the wiring shape is flexed gently is obtained, and the temperature of the lead 11 is set. The cycle life can also be extended.

  The bending stress ratio α is defined as the stress σ1 generated at the tape-side corner 49 of the lead 11 when the bonding tool 18 pushes up the lead 11 directly above the bonding pad 7 to the tape end 48 of the lead 11. Divided by the stress σ0 generated in That is, the bending stress ratio α can be expressed by the following equation from the dimensions of the lead 11 characterized by a tapered shape.

α = σ1 / σ0 = b1 × (L2−L1) / (b2 × L2)
As described above, by designing the dimensions and shape of the lead 11 so that the bending stress ratio α is 1.2 to 1.5, as in the technique of the planar S-shaped lead 26, a simple bond with a wire bonder is possible. A stable S-shaped wiring state that is stable by the downward trajectory can be formed. Therefore, a special wire bonder modified by software is not required, and the bonding tool trajectory 25 can be simplified, so that an effect of shortening the tact time during bonding can be expected.

12 In the technical explanation of the Ni plating-less lead, FIG. 54 is a cross-sectional view showing a connection portion of lead connection, FIG. 55 is an enlarged cross-sectional view showing a bent portion of the lead, and FIG. 56 is a bent portion of the Ni plating-less lead. FIG. 57 is an enlarged sectional view showing a crimping portion of a lead, and FIG. 58 is an enlarged sectional view showing a crimping portion of a Ni platingless lead.

  For example, in the technique studied by the present inventor, in the case of the cross-sectional structure of the lead 11 in which the surface is plated with Ni as the Cu core lead instead of the solid Au lead, and the surface thereof is plated with Au, the Ni plating layer is hard and brittle. For this reason, it is conceivable that a crack 51 enters at the bent portion of the lead 11 as shown in FIG. 55 or damage 52 occurs under the bonding pad 7 or below as shown in FIG.

  On the other hand, in the first embodiment, the use of the lead 11 without the Ni plating reduces both hardness and brittleness, so that the crack itself of the lead itself is less likely to occur and is a bonding surface. Damage 52 to the semiconductor chip 1 can also be reduced.

  That is, in the lead 11 connected state as shown in FIG. 54, the lead 11 having the configuration of the Cu core 53 + Ni plating 54 + Au plating 55 as shown in FIG. If the radius of curvature is small, cracks 51 are likely to occur. On the other hand, as shown in FIG. 56, if the surface of the lead 11 is not Ni plating 54, for example, only Au plating 55, the lead 11 can be obtained even when the curvature is the same as in FIG. The crack 51 is less likely to occur at the bent portion.

  Also, in the crimped portion of the lead 11 shown in FIG. 57 showing the B portion of FIG. 54 in an enlarged manner, the lead 11 having the configuration of the Cu core 53 + Ni plating 54 + Au plating 55 causes damage 52 around the bonding pad 7 as shown in the figure. On the other hand, as shown in FIG. 58, if the surface of the lead 11 is made of only the Au plating 55, for example, without the Ni plating 54, the damage 52 hardly occurs even when bonded under the same lead bonding conditions.

  As described above, by forming only the plating layer such as the Au plating 55 on the core material such as the Cu core 53, the formation of the lead 11 is suppressed, and the generation of the crack 51 in the lead 11 is suppressed, and the damage 52 to the semiconductor chip 1 is prevented. It becomes possible to reduce.

  Therefore, according to the semiconductor integrated circuit device of the first embodiment, in the CSP package technology having substantially the same size as that of the semiconductor chip 1, as described in order by comparison with the package structure studied by the present inventors in the above, . Table wiring structure, 2. 2. Tape eaves optimization for elastomers; 3. Optimization of package external dimensions 4. plane S-shaped lead; Beam lead, 6; 6. Peripheral PIQ dimension of bonding pad, Improvement of anchor wiring, 8. 8. Wide elastomer structure, 10. Elastomeric groove filling technology. Inner lead bonding technology, 11. 11. Lead design technology capable of forming S-shape without tool return; An excellent effect can be obtained in each technical item of the Ni plating-less lead.

  In the first embodiment, 1. Although the drawings and the technical contents thereof have been described on the premise of the front wiring structure, the technical items from 2 to 12 are not limited to the front wiring structure, and the back wiring structure as shown in FIG. Therefore, even when applied to a general package structure, it can be expected to obtain the same effect as described for each item.

  In the package structure (FIGS. 1 and 2) of the first embodiment, the case where the elastomer 2 is larger than the outer shape of the semiconductor chip 1 is shown. Conversely, as shown in FIG. 81, the elastomer 2 is a semiconductor chip. In the case where the outer shape is smaller than 1, the moisture resistance and the like can be improved by forming the package structure in which the side surfaces of the semiconductor chip 1 and the elastomer 2 are covered with the sealing material 6.

(Embodiment 2)
59 and 60 are a sectional view and a perspective view showing a back wiring solder resist structure in the semiconductor integrated circuit device according to the second embodiment of the present invention.

  The semiconductor integrated circuit device according to the second embodiment is a ball grid array type semiconductor package as in the first embodiment, and the difference from the first embodiment is that the technology based on the surface wiring structure is used. However, as shown in FIG. 59 and FIG. 60, for example, an elastomer 2 (elastic structure) bonded to the main surface of the semiconductor chip 1 and an elastomer are provided. The solder resist 56 (insulating film) is formed on the back surface of the flexible wiring board 3 in the structure with the flexible wiring board 3 (wiring board) bonded to the main surface of 2.

  That is, the flexible wiring board 3 is composed of a tape 9 (substrate base material) serving as a base material of the flexible wiring board 3 and a wiring 10 bonded on the back surface of the tape 9, and the back surface side of the wiring 10 is soldered. The structure is bonded to the elastomer 2 through a resist 56. The solder resist 56 is made of an insulating material such as a photosensitive epoxy resin as in the first embodiment.

  Here, the characteristics of the package structure of the semiconductor integrated circuit device according to the second embodiment will be described, including the structure and process, by comparison with the package structure as a technique studied by the present inventors.

  For example, as a technique studied by the present inventors, in the back wiring structure as shown in FIG. 7 in the first embodiment, the elastomer 2 is directly formed on the main surface of the wiring 10 of the flexible wiring board 3. When the low molecular weight component 2 bleeds directly on the lead 11 and spreads to the bonding point of the lead 11, there arises a problem that bonding property (wiring bonding strength) is extremely lowered due to the contamination.

  Further, the surface of the tape 9 in which the wiring 10 is etched out between the leads 11 has a meaning of improving the adhesiveness between the tape 9 and the wiring 10 as compared with the plated surface of the direct lead 11. Since the surface of the tape 9 is roughened, the bleed is very intense, and the bleed tends to be intense at the edge portion of the lead 11 due to the effect of surface tension.

  Further, in the back wiring structure in which the elastomer 2 is formed on the surface of the wiring 10 where the wiring 10 is present and where the wiring 10 is not present, voids are likely to remain in the gap between the wiring 10 and the wiring 10 and there is a concern about reliability. It can be considered.

  In contrast, in the second embodiment, in the manufacturing process of the flexible wiring board 3, the solder resist 56 is formed on the wiring 10 after the wiring 10 is formed, so that the elastomer 2 is in direct contact with the wiring 10. Can be prevented. Similarly, the contact of the elastomer 2 with the roughened surface of the tape 9 can also be prevented. Thereby, the bleeding of the low molecular weight component of the elastomer 2 can be suppressed.

  Furthermore, the surface of the wiring 10 is flattened by applying the solder resist 56 to the surface of the wiring 10 having the irregularities of the flexible wiring board 3, and it is possible to avoid problems such as void entrainment when forming the elastomer 2. it can.

  Therefore, according to the semiconductor integrated circuit device of the second embodiment, in the CSP semiconductor package technology based on the back wiring structure, the lead 11 is formed by forming the solder resist 56 on the wiring 10 of the flexible wiring board 3. Thus, the deterioration of the bonding property can be suppressed, and a highly reliable package structure free from voids can be obtained.

(Embodiment 3)
61 is a plan view of a semiconductor integrated circuit device according to a third embodiment of the present invention as seen from the back side of the semiconductor chip, FIG. 62 is a plan view, FIG. 63 is a cross-sectional view, and FIG. FIG. 65 is a plan view for explaining the wiring structure of the wiring board.

  The semiconductor integrated circuit device according to the third embodiment has a peripheral pad structure as shown in FIGS. 61 to 65 in place of the so-called fan-in-center pad structure semiconductor package as in the first and second embodiments. A so-called fan-in-peripheral pad package structure is used in which the semiconductor chip 1a is used and the solder bumps 5a connected to the bonding pads of the semiconductor chip 1a are arranged in the region inside the outer periphery of the semiconductor chip 1a. In the third embodiment as well, the description of 1. From table wiring structure 12. This structure incorporates the technology up to the Ni plating-less lead and the features of the respective technical items of the back wiring solder resist structure described in the second embodiment.

  That is, the semiconductor integrated circuit device according to the third embodiment is a semiconductor package of, for example, a 24-pin ball grid array format, on the main surface of the semiconductor chip 1a on which a plurality of bonding pads 7a (external terminals) are formed. An elastomer 2a (elastic structure), a flexible wiring board 3a (wiring board) in which wiring 10a is formed on a tape 9a, and a solder resist 4a (insulating film) are provided, and solder bumps 5a (in the opening of the solder resist 4a ( Bump electrodes) are formed, and a package structure is formed in which the bonding pad 7a forming portion, the elastomer 2a, and the side surfaces of the flexible wiring board 3a are covered with the sealing material 6a.

  The semiconductor chip 1a has a peripheral pad structure as shown in FIG. 65, for example, and a plurality of bonding pads 7a are arranged in a square shape along the outer periphery of the semiconductor chip 1a. A solder bump 5a joined to a bump land 12a at the other end of the wiring 10a is electrically connected to a bonding pad 7a of the semiconductor chip 1a through a wiring 10a of a flexible wiring board 3a to which a lead 11a at one end is connected. It is connected. The solder bumps 5a are arranged in 6 rows × 4 columns in a region inside the arrangement position of the bonding pads 7a of the semiconductor chip 1a.

  Therefore, the semiconductor integrated circuit device of the third embodiment also has the same differences in the technical items as described in the first and second embodiments, although there is a difference in the semiconductor package structure of the fan-in-peripheral pad. An excellent effect can be obtained. In particular, in this fan-in package structure, a CSP semiconductor package having substantially the same size as that of the semiconductor chip 1a can be obtained as in the first and second embodiments.

(Embodiment 4)
66 is a plan view of the semiconductor integrated circuit device according to the fourth embodiment of the present invention as viewed from the back surface of the semiconductor chip, FIG. 67 is a plan view, FIG. 68 is a sectional view, and FIG. FIG. 70 is a plan view for explaining the wiring structure of the wiring board.

  The semiconductor integrated circuit device according to the fourth embodiment has a peripheral pad structure as shown in FIGS. 66 to 70 in place of the so-called fan-in-center pad semiconductor package as in the first and second embodiments. A package structure of so-called fanout-peripheral pads is used in which the semiconductor chip 1b is used and solder bumps 5b connected to the bonding pads of the semiconductor chip 1b are arranged in a region outside the outer periphery of the semiconductor chip 1b. In the fourth embodiment as well, the items described in the first embodiment are as follows. From table wiring structure 12. This structure incorporates the technology up to the Ni plating-less lead and the features of the respective technical items of the back wiring solder resist structure described in the second embodiment.

  That is, the semiconductor integrated circuit device according to the fourth embodiment is, for example, an 80-pin ball grid array type semiconductor package on the main surface of the semiconductor chip 1b on which a plurality of bonding pads 7b (external terminals) are formed. An elastomer 2b (elastic structure), a flexible wiring board 3b (wiring board) in which wiring 10b is formed on a tape 9b, and a solder resist 4b (insulating film) are provided, and solder bumps 5b (in the openings of the solder resist 4b ( Bump electrodes) are formed, the formation portion of the bonding pad 7b is covered with the sealing material 6b, and the support ring 57b is provided on the side surface portion of the semiconductor chip 1b.

  The semiconductor chip 1b has a peripheral pad structure as shown in FIG. 70, for example, and a plurality of bonding pads 7b are arranged in a square shape along the outer periphery of the semiconductor chip 1b. A solder bump 5b joined to a bump land 12b at the other end of the wiring 10b is electrically connected to a bonding pad 7b of the semiconductor chip 1b via a wiring 10b of a flexible wiring board 3b to which a lead 11b at one end is connected. It is connected. The solder bumps 5b are arranged in two rows in a square shape in a region outside the arrangement position of the bonding pads 7b of the semiconductor chip 1b.

  Therefore, the semiconductor integrated circuit device of the fourth embodiment also has the same technical items as described in the first and second embodiments, although there is a difference in the semiconductor package structure of the fanout-peripheral pad. An excellent effect can be obtained. In particular, in this fan-out package structure, although the size of the semiconductor package is larger than those in the first and second embodiments, a package structure corresponding to the increase in the number of pins can be achieved.

(Embodiment 5)
71 is a plan view of a semiconductor integrated circuit device according to a fifth embodiment of the present invention as viewed from the back side of the semiconductor chip, FIG. 72 is a plan view, FIG. 73 is a cross-sectional view, and FIG. FIG. 75 is a plan view for explaining the wiring structure of the wiring board. In FIG. 75, in order to clarify the routing of wiring, the number of bonding pads, solder bumps, and the like are partially omitted and simplified.

  The semiconductor integrated circuit device according to the fifth embodiment has a peripheral pad structure as shown in FIGS. 71 to 75 in place of the so-called fan-in-center pad structure semiconductor package as in the first and second embodiments. A so-called fan-in / out-peripheral pad package in which the semiconductor chip 1c is used and the solder bumps 5c connected to the bonding pads of the semiconductor chip 1c are arranged in both the inner and outer regions of the semiconductor chip 1c. It has a structure. In the fifth embodiment as well, the items described in the first embodiment are as follows. From table wiring structure 12. This structure incorporates the technology up to the Ni plating-less lead and the features of the respective technical items of the back wiring solder resist structure described in the second embodiment.

  That is, the semiconductor integrated circuit device according to the fifth embodiment is, for example, a 110-pin ball grid array type semiconductor package, on the main surface of the semiconductor chip 1c on which a plurality of bonding pads 7c (external terminals) are formed. An elastomer 2c (elastic structure), a flexible wiring board 3c (wiring board) in which wiring 10c is formed on a tape 9c, and a solder resist 4c (insulating film) are provided. Solder bumps 5c (in the openings of the solder resist 4c) Bump electrodes) are formed, the formation portion of the bonding pad 7c is covered with the sealing material 6c, and the support ring 57c is provided on the side surface portion of the semiconductor chip 1c.

  For example, the semiconductor chip 1c has a peripheral pad structure as shown in FIG. 75 (actual arrangement is FIG. 72), and a plurality of bonding pads 7c are arranged in a square shape along the outer periphery of the semiconductor chip 1c. Yes. A solder bump 5c to be bonded to the bump land 12c at the other end of the wiring 10c is electrically connected to the bonding pad 7c of the semiconductor chip 1c via the wiring 10c of the flexible wiring substrate 3c to which the lead 11c at one end is connected. It is connected. The solder bumps 5c are arranged in 6 rows × 5 columns in a region inside the arrangement position of the bonding pads 7c of the semiconductor chip 1c, and are arranged in two rows in a square shape in the outer region.

  Therefore, in the semiconductor integrated circuit device of the fifth embodiment, although there is a difference in the semiconductor package structure of the fan-in / out-peripheral pad, in each technical item as described in the first and second embodiments. Similar excellent effects can be obtained. In particular, in this fan-in / out package structure, although the size of the semiconductor package is larger than in the first and second embodiments, a package structure corresponding to the increase in the number of pins can be achieved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the first to fifth embodiments of the invention. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say, it can be changed.

  For example, in the above-described embodiment, each of the so-called center pad-fan-in, peripheral pad-fan-in, peripheral pad-fan-out, and peripheral pad-fan-in / out semiconductor packages has been described. The present invention can also be applied to an out or center pad-fan-in / out semiconductor package.

  Also, the number of solder bumps as external connection terminals of the semiconductor package and the number of bonding pads which are external terminals of the semiconductor chip electrically connected to the solder bumps are not limited to those described in the above embodiment. However, it can be appropriately changed according to the package specification of an integrated circuit or the like formed on the semiconductor chip.

  In addition, materials such as elastomers as elastic structures, flexible wiring board tapes as wiring boards, wiring and lead plating, solder resists as insulating films, and solder bumps as bump electrodes also have their respective characteristics. Needless to say, the present invention can be applied to the case of using other materials.

  For example, solder resists include materials such as melamine, acrylic, polystyrene, polyimide, polyurethane, silicone, etc., and they have the property of withstanding soldering temperatures and at the same time being exposed to flux and cleaning solvents. It will be necessary.

1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention. In Embodiment 1 of this invention, it is sectional drawing in the A-A 'cutting line of FIG. It is a top view which shows the mounting state to the mounting board | substrate of the semiconductor integrated circuit device in Embodiment 1 of this invention. It is sectional drawing which shows the mounting state to the mounting board | substrate of the semiconductor integrated circuit device in Embodiment 1 of this invention. It is a flowchart which shows the assembly process of the semiconductor integrated circuit device in Embodiment 1 of this invention. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is principal part sectional drawing which shows a surface wiring structure. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is principal part sectional drawing which shows a back wiring structure. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is principal part sectional drawing which shows a double-sided wiring. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows a window opening part. FIG. 10 is a cross-sectional view showing the window opening of FIG. 9 in a comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing for dimension description of the window opening part and the edge part of a semiconductor chip. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the dent of the elastomer after printing. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the curvature of the tape after semiconductor chip bonding. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows a planar S character lead. FIG. 15 is a cross-sectional view taken along arrow B in FIG. 14 in the comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. FIG. 15 is a cross-sectional view taken along arrow A in FIG. 14 in a comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the locus | trajectory of the bonding tool at the time of standard S-shaped lead formation. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the locus | trajectory of the bonding tool at the time of planar S character lead formation. FIG. 5 is a plan view for explaining notch leads and beam leads in a comparative explanation between the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. FIG. 20 is a plan view showing a notch lead in part A of FIG. 19 in the comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows a beam lead. FIG. 5 is a cross-sectional view showing a lead bonding portion in a comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device examined by the present inventors. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows a lead bonding part. FIG. 23 is a cross-sectional view showing, in an enlarged manner, a landing point of a tool in part A of FIG. 22 in a comparative explanation between the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the bonding part which improved the passivation opening dimension. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the bonding part of a bidirectional | two-way lead. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows a standard anchor wiring. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows improvement anchor wiring. 1 is a perspective view showing a structure of a standard elastomer in a comparative explanation between a semiconductor integrated circuit device according to a first embodiment of the present invention and a semiconductor integrated circuit device studied by the present inventors. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the bonding state of the semiconductor chip in a standard elastomer. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the structure of a wide elastomer. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the bonding state of the semiconductor chip in a wide elastomer. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the bonding state of the semiconductor chip in a wide elastomer. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the structure after affixing the semiconductor chip in a standard elastomer. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the structure after affixing the semiconductor chip with a standard elastomer. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the structure after affixing the semiconductor chip in a wide elastomer. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the structure after affixing the semiconductor chip in a wide elastomer. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the concept of metal mask printing. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the metal mask of a standard elastomer. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the metal mask of a wide elastomer. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention, and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the printing shape of a multiple-hanging wide elastomer. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the potting position for the groove | channel filling of a wide elastomer. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the bonding part by standard lead bonding. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the bonding part using a stud bump. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead connection using solder. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a top view which shows the lead connection using solder. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of the present invention and the semiconductor integrated circuit device examined by the present inventor, it is a sectional view showing lead connection using solder or Au balls. In the comparative description of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the lead connection using a solder or Au ball | bowl. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the connection using Al or a solder wire. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the connection using Au wire. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view for demonstrating lead design. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is a perspective view which shows the lead deformation | transformation after bonding. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is explanatory drawing which shows the relationship between a lead dimension and a bending stress ratio. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the connection part of lead connection. 5 is an enlarged cross-sectional view showing a bent portion of a lead in a comparative explanation between the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device examined by the present inventor. FIG. In the comparative explanation of the semiconductor integrated circuit device in Embodiment 1 of the present invention and the semiconductor integrated circuit device examined by the present inventors, it is an enlarged cross-sectional view showing a bent portion of a Ni platingless lead. FIG. 5 is an enlarged cross-sectional view showing a lead crimping portion in a comparative explanation between the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device examined by the present inventors. FIG. 5 is an enlarged cross-sectional view showing a Ni-plated leadless crimp portion in a comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device studied by the present inventors. In the semiconductor integrated circuit device which is Embodiment 2 of this invention, it is sectional drawing which shows a back wiring soldering resist structure. In the semiconductor integrated circuit device which is Embodiment 2 of this invention, it is a perspective view which shows a back wiring soldering resist structure. It is the top view which looked at the semiconductor integrated circuit device which is Embodiment 3 of this invention from the semiconductor chip back surface. It is a top view which shows the semiconductor integrated circuit device which is Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor integrated circuit device which is Embodiment 3 of this invention. FIG. 64 is an enlarged cross-sectional view showing a portion A of FIG. 63 in the semiconductor integrated circuit device according to the third embodiment of the present invention. In the semiconductor integrated circuit device in Embodiment 3 of this invention, it is a top view for demonstrating the wiring structure of a wiring board. It is the top view which looked at the semiconductor integrated circuit device which is Embodiment 4 of this invention from the semiconductor chip back surface. It is a top view which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. It is sectional drawing which shows the semiconductor integrated circuit device which is Embodiment 4 of this invention. FIG. 69 is an enlarged cross-sectional view showing a portion A of FIG. 68 in the semiconductor integrated circuit device according to the fourth embodiment of the present invention. In the semiconductor integrated circuit device in Embodiment 4 of this invention, it is a top view for demonstrating the wiring structure of a wiring board. It is the top view which looked at the semiconductor integrated circuit device which is Embodiment 5 of this invention from the semiconductor chip back surface. It is a top view which shows the semiconductor integrated circuit device which is Embodiment 5 of this invention. It is sectional drawing which shows the semiconductor integrated circuit device which is Embodiment 5 of this invention. FIG. 74 is an enlarged cross-sectional view showing a portion A of FIG. 73 in the semiconductor integrated circuit device according to the fifth embodiment of the present invention. In the semiconductor integrated circuit device in Embodiment 5 of this invention, it is a top view for demonstrating the wiring structure of a wiring board. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead deformation | transformation shape according to a bending stress ratio. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead deformation | transformation shape according to a bending stress ratio. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead deformation | transformation shape according to a bending stress ratio. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead deformation | transformation shape according to a bending stress ratio. In the comparison explanation of the semiconductor integrated circuit device in Embodiment 1 of this invention and the semiconductor integrated circuit device which this inventor examined, it is sectional drawing which shows the lead deformation | transformation shape according to a bending stress ratio. FIG. 10 is a cross-sectional view showing a modified example of the package structure in the comparative description of the semiconductor integrated circuit device according to the first embodiment of the present invention and the semiconductor integrated circuit device examined by the present inventors.

Explanation of symbols

1, 1a, 1b, 1c Semiconductor chip 2, 2a, 2b, 2c Elastomer (elastic structure)
3, 3a, 3b, 3c Flexible wiring board (wiring board)
4, 4a, 4b, 4c Solder resist (insulating film)
5, 5a, 5b, 5c Solder bump (bump electrode)
6, 6a, 6b, 6c Sealing material 7, 7a, 7b, 7c Bonding pad (external terminal)
8 Adhesive 9, 9a, 9b, 9c Tape (substrate substrate)
10, 10a, 10b, 10c Wiring 11, 11a, 11b, 11c Lead 12, 12a, 12b, 12c Bump land 13 Chip size package 14 General package 15 Mounting substrate 16 External connection terminal 17 Solder ball 18 Bonding tool 19 Dispenser 20 First Wiring 21 Second wiring 22 Via hole 23 Window opening 24 Standard S-shaped lead 25 Bonding tool locus 26 Flat S-shaped lead 27 Notch 28 Beam lead 29 Passivation 30 Passivation opening 31 Standard anchor wiring 32 Expanded anchor wiring 33 Standard elastomer 34 Wide elastomer 35 Adhesive seepage 36 Cutting line 37 Metal mask 38 Print area opening 39 Suspension 40 Groove 41 Squeegee 42 Potting position 43 Stud bump 44 I 45 solder or Au balls 46 Al or solder wire 47 Au wire 48 tape end 49 tape side corner 50 the chip-side corner 51 crack 52 Damage 53 Cu core 54 Ni plating 55 Au plating 56 solder resist (insulating film)
57b, 57c Support ring

Claims (11)

A method for manufacturing a semiconductor integrated circuit device comprising the following steps:
(A) a front surface, a back surface opposite to the front surface, an opening penetrating from the front surface to the back surface, a first bump land formed in a first region adjacent to the opening portion on the back surface, and the first surface on the back surface; One region is a second bump land formed in the second region on the opposite side through the opening, and the first bump land and the second bump land are connected to each other on the back surface, and intersect with the opening. Preparing a wiring board having a first lead formed to perform;
(B) A semiconductor chip having a main surface and a first bonding pad formed on the main surface, the main surface facing the surface of the wiring board, and the first bonding pad being the opening of the wiring board. Mounting on the surface of the wiring board so as to be located in a part;
(C) The first lead is connected to the first bonding pad of the semiconductor chip by pressing a bonding tool against the first lead in the opening of the wiring board, and the first lead is connected to the second lead. Electrically cutting from bump land;
here,
Each width of the first bump land and the second bump land is larger than the width of the first lead. Oite to claim 1,
Each width of the first lead, the first bump land, and the second bump land is a width in a direction intersecting with the extending direction of the first lead in the opening of the wiring board. A method for manufacturing a semiconductor integrated circuit device . In claim 2,
The wiring board connects the first bump land and the second bump land, and is formed so as to intersect the opening, and has a second lead arranged next to the first lead,
In the step (c), the second lead is formed adjacent to the first bonding pad of the semiconductor chip by pressing the bonding tool against the second lead in the opening of the wiring board. 2. A method of manufacturing a semiconductor integrated circuit device, comprising: connecting to a bonding pad and electrically cutting the second lead from the first bump land. In claim 3,
The first bump land is formed across a plurality of rows in the first region,
The method of manufacturing a semiconductor integrated circuit device, wherein the second bump land is formed in a plurality of rows in the second region. In claim 4,
Each of said 1st bonding pad and said 2nd bonding pad is formed in the center part in the said main surface of the said semiconductor chip, The manufacturing method of the semiconductor integrated circuit device characterized by the above-mentioned. In claim 5,
After the step (c), a first joint portion between the first bonding pad and the first lead of the semiconductor chip, and a second joint portion between the second bonding pad and the second lead of the semiconductor chip. And a semiconductor integrated circuit device. In claim 6,
After the first joint and the second joint are sealed with the resin, a bump electrode is formed on each of the first bump land and the second bump land. Method. In claim 2,
A plurality of the first bump lands are formed along the opening in the first region;
A plurality of the second bump lands are formed along the opening in the second region,
In the step (a), a third bump land lead connected to a third bump land of the plurality of first bump lands is formed between the plurality of second bump lands in the second region. A method for manufacturing a semiconductor integrated circuit device, comprising: In claim 8,
The method of manufacturing a semiconductor integrated circuit device, wherein the first bonding pad is formed at a central portion of the main surface of the semiconductor chip. In claim 9,
A method of manufacturing a semiconductor integrated circuit device, wherein after the step (c), a first bonding portion between the first bonding pad and the first lead of the semiconductor chip is sealed with a resin. In claim 10,
After the first joint is sealed with the resin, a bump electrode is formed on each of the first bump land, the second bump land, and the third bump land. Method.

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