JP4397744B2 - 半導体集積回路の高位合成方法 - Google Patents
半導体集積回路の高位合成方法 Download PDFInfo
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- JP4397744B2 JP4397744B2 JP2004188840A JP2004188840A JP4397744B2 JP 4397744 B2 JP4397744 B2 JP 4397744B2 JP 2004188840 A JP2004188840 A JP 2004188840A JP 2004188840 A JP2004188840 A JP 2004188840A JP 4397744 B2 JP4397744 B2 JP 4397744B2
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004188840A JP4397744B2 (ja) | 2004-06-25 | 2004-06-25 | 半導体集積回路の高位合成方法 |
| US11/159,291 US7237220B2 (en) | 2004-06-25 | 2005-06-23 | High level synthesis method for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004188840A JP4397744B2 (ja) | 2004-06-25 | 2004-06-25 | 半導体集積回路の高位合成方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2006011878A JP2006011878A (ja) | 2006-01-12 |
| JP2006011878A5 JP2006011878A5 (enExample) | 2007-04-19 |
| JP4397744B2 true JP4397744B2 (ja) | 2010-01-13 |
Family
ID=35507580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004188840A Expired - Fee Related JP4397744B2 (ja) | 2004-06-25 | 2004-06-25 | 半導体集積回路の高位合成方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7237220B2 (enExample) |
| JP (1) | JP4397744B2 (enExample) |
Families Citing this family (34)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7152217B1 (en) * | 2004-04-20 | 2006-12-19 | Xilinx, Inc. | Alleviating timing based congestion within circuit designs |
| US7769569B2 (en) * | 2004-09-02 | 2010-08-03 | Logiccon Design Automation Ltd. | Method and system for designing a structural level description of an electronic circuit |
| JP4129988B2 (ja) * | 2005-11-10 | 2008-08-06 | インターナショナル・ビジネス・マシーンズ・コーポレーション | リソースのプロビジョニング方法 |
| US7657857B2 (en) * | 2006-03-17 | 2010-02-02 | Altera Corporation | Performance visualization of delay in circuit design |
| US8902231B2 (en) * | 2006-10-20 | 2014-12-02 | Alcatel Lucent | Method and apparatus for displaying graphical representations of graph layouts |
| US8127260B1 (en) * | 2006-11-22 | 2012-02-28 | Cadence Design Systems, Inc. | Physical layout estimator |
| US8356287B2 (en) * | 2007-10-24 | 2013-01-15 | International Business Machines Corporation | Device, system and method of debugging computer programs |
| CN102054109B (zh) * | 2010-12-31 | 2014-03-19 | 北京大学深圳研究生院 | 集成电路下层硬件映射方法、数据控制流生成方法及装置 |
| CN102054107B (zh) * | 2010-12-31 | 2013-11-06 | 北京大学深圳研究生院 | 集成电路下层硬件映射方法、时空图生成方法及装置 |
| US9135037B1 (en) | 2011-01-13 | 2015-09-15 | Google Inc. | Virtual network protocol |
| US8874888B1 (en) | 2011-01-13 | 2014-10-28 | Google Inc. | Managed boot in a cloud system |
| US8862743B1 (en) * | 2011-01-13 | 2014-10-14 | Google Inc. | Resource management |
| US9237087B1 (en) | 2011-03-16 | 2016-01-12 | Google Inc. | Virtual machine name resolution |
| US9063818B1 (en) | 2011-03-16 | 2015-06-23 | Google Inc. | Automated software updating based on prior activity |
| US8533796B1 (en) | 2011-03-16 | 2013-09-10 | Google Inc. | Providing application programs with access to secured resources |
| CN102163248B (zh) * | 2011-04-02 | 2012-12-05 | 北京大学深圳研究生院 | 一种集成电路的高级综合方法 |
| US9075979B1 (en) | 2011-08-11 | 2015-07-07 | Google Inc. | Authentication based on proximity to mobile device |
| US20130046912A1 (en) * | 2011-08-18 | 2013-02-21 | Maxeler Technologies, Ltd. | Methods of monitoring operation of programmable logic |
| US8966198B1 (en) | 2011-09-01 | 2015-02-24 | Google Inc. | Providing snapshots of virtual storage devices |
| US8958293B1 (en) | 2011-12-06 | 2015-02-17 | Google Inc. | Transparent load-balancing for cloud computing services |
| CN102419789B (zh) * | 2011-12-16 | 2013-05-01 | 中山大学 | 一种高层次综合方法以及系统 |
| US8800009B1 (en) | 2011-12-30 | 2014-08-05 | Google Inc. | Virtual machine service access |
| US8983860B1 (en) | 2012-01-30 | 2015-03-17 | Google Inc. | Advertising auction system |
| US8996887B2 (en) | 2012-02-24 | 2015-03-31 | Google Inc. | Log structured volume encryption for virtual machines |
| US8677449B1 (en) | 2012-03-19 | 2014-03-18 | Google Inc. | Exposing data to virtual machines |
| JP5910230B2 (ja) * | 2012-03-26 | 2016-04-27 | 富士通株式会社 | 設計支援プログラム、設計支援方法、および設計支援装置 |
| JP6255880B2 (ja) * | 2013-10-10 | 2018-01-10 | 株式会社ソシオネクスト | 高位合成用データ生成装置、高位合成装置、高位合成用データ生成方法及びプログラム |
| JP5842255B2 (ja) | 2013-12-12 | 2016-01-13 | 国立大学法人東京工業大学 | プログラミング言語による論理回路記述から論理回路を生成するための装置及び方法 |
| CN104981019B (zh) * | 2014-04-03 | 2019-04-26 | 华为技术有限公司 | 调度无线资源的方法、控制节点和系统 |
| US10192014B2 (en) * | 2015-08-27 | 2019-01-29 | Mitsubishi Electric Corporation | Circuit design support apparatus and computer readable medium |
| JP6801460B2 (ja) * | 2017-01-11 | 2020-12-16 | 富士通株式会社 | 情報処理装置、プログラム、および情報処理方法 |
| US10467722B2 (en) * | 2017-11-06 | 2019-11-05 | Basemark Oy | Combined rendering and computing resource allocation management system |
| US20240085967A1 (en) | 2022-09-09 | 2024-03-14 | SambaNova Systems, Inc. | Integrated circuit that mitigates inductive-induced voltage overshoot |
| US12416961B2 (en) | 2022-09-09 | 2025-09-16 | SambaNova Systems, Inc. | Integrated circuit that mitigates inductive-induced voltage droop using compute unit group identifiers |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5553002A (en) * | 1990-04-06 | 1996-09-03 | Lsi Logic Corporation | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface |
| JP2977422B2 (ja) | 1992-10-05 | 1999-11-15 | 松下電器産業株式会社 | 製品仕様推定方法、論理回路の分類評価装置、製品仕様データベース作成装置、製品仕様推定装置および論理回路自動階層生成装置 |
| US5870588A (en) * | 1995-10-23 | 1999-02-09 | Interuniversitair Micro-Elektronica Centrum(Imec Vzw) | Design environment and a design method for hardware/software co-design |
| US6415420B1 (en) * | 1999-04-30 | 2002-07-02 | Incentia Design Systems, Inc. | Synthesizing sequential devices from hardware description languages (HDLS) |
| US6782511B1 (en) * | 1999-05-26 | 2004-08-24 | Cadence Design Systems, Inc. | Behavioral-synthesis electronic design automation tool business-to-business application service provider |
| JP3722351B2 (ja) * | 2000-02-18 | 2005-11-30 | シャープ株式会社 | 高位合成方法およびその実施に使用される記録媒体 |
| US20030006575A1 (en) * | 2001-05-08 | 2003-01-09 | Shane Genis | Side impact friendly running board |
| US6925628B2 (en) * | 2002-10-22 | 2005-08-02 | Matsushita Electric Industrial Co., Ltd. | High-level synthesis method |
-
2004
- 2004-06-25 JP JP2004188840A patent/JP4397744B2/ja not_active Expired - Fee Related
-
2005
- 2005-06-23 US US11/159,291 patent/US7237220B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| US20050289499A1 (en) | 2005-12-29 |
| JP2006011878A (ja) | 2006-01-12 |
| US7237220B2 (en) | 2007-06-26 |
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