JP4389308B2 - Memory control device and control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory control device for reducing power consumption by stopping a clock when a system LSI is in a standby state while preventing destruction of a memory incorporated in the system LSI.
[0002]
[Prior art]
In logic LSIs, microcomputers, and the like, it has often been performed to stop the clock during standby in order to reduce power consumption. The memory mounted on the logic LSI is mainly an SRAM that can be easily mixed with other semiconductors. Since the SRAM is basically composed of flip-flops, no problem occurs even if the clock is stopped during the standby of the LSI.
[0003]
In recent years, with the progress of semiconductor process technology, memories manufactured by different semiconductor processes such as DRAM and flash memory can be built in one LSI. Since the built-in DRAM does not have a protection circuit for the built-in memory due to the limitation of the scale of the LSI, it is necessary to operate according to a predetermined procedure for controlling the DRAM. Therefore, in a system LSI with a built-in DRAM, a method different from that of a logic LSI or microcomputer equipped with an SRAM is required to stop the clock in order to save power.
[0004]
FIG. 4 shows an example of a clock stop control method in a signal processing circuit and a control signal generation circuit for controlling the signal processing circuit in conventional video equipment. Hereinafter, a conventional clock stop control method will be described with reference to FIG. When the horizontal synchronization signal 1 is input, the signal processing circuit 101 performs various signal processing based on the horizontal synchronization signal 1. When the horizontal synchronization signal 1 is input, the control signal generation circuit 102 generates various control signals including the control of the signal processing circuit 101 based on the horizontal synchronization signal 1.
[0005]
A clock control unit for stopping / resuming clock supply for signal processing and control signal generation is provided in the two circuits. These circuits are composed of a logic LSI and an SRAM. The operation of the signal processing circuit 101 and the control signal generation circuit 102 in the conventional video equipment configured as described above will be described below.
[0006]
The signal processing circuit 101 and the control signal generation circuit 102 operate with the horizontal synchronization signal 1 as a reference. Here, when the signal processing circuit 101 and the control signal generation circuit 102 input a clock stop command by the clock supply control signal 2 asynchronous to the horizontal synchronization signal 1, the signal processing circuit 101 immediately controls the clock in response to the command. Stop the clock. Similarly, the control signal generation circuit 102 also stops its internal clock.
[0007]
When the clock is stopped, the signal processing circuit 101 and the control signal generation circuit 102 temporarily stop the operation, and when a clock restart command is input by the supply control signal 2, the clock supply is restarted in response to the command and starts again. To do. In this manner, by simply stopping the clock, the signal processing circuit 101 and the control signal generation circuit 102 can be set in a standby state, and power consumption can be reduced.
[0008]
[Problems to be solved by the invention]
In the conventional clock stop control method, the signal processing circuit and the control signal generation circuit are composed of SRAM and a logic circuit, so that the clock supply is stopped and restarted in response to the clock supply control signal asynchronous to the horizontal synchronization signal. There was no problem even if I did.
[0009]
However, in the case of an LSI or the like with a built-in memory such as a DRAM, when an asynchronous clock supply control signal ignoring the internal state of the memory is input to the LSI and the clock supply is stopped in response to the signal, Memory cells can be destroyed.
[0010]
[Means for Solving the Problems]
The clock stop control device of the present invention can stop / restart the clock supply without destroying the memory element as follows when the memory having the internal state is built in the LSI used for the video equipment or the like. It is characterized by that.
[0011]
1) A clock supply control signal that is asynchronous to the horizontal synchronization signal that is a reference signal is received, and a clock supply control signal that is synchronized with the horizontal synchronization signal is generated.
[0012]
2) The clock is stopped according to the synchronized supply control signal when the internal state of the built-in memory is always in the standby state.
[0013]
3) After restarting the clock supply in response to the synchronized supply control signal, the internal memory is initialized.
[0014]
The memory control device of the present invention includes the following constituent elements in order to control the clock supply to the memory.
[0015]
a) An operation command generation circuit for generating an operation command for controlling the built-in memory based on the input horizontal synchronization signal.
[0016]
b) A control signal generation circuit that receives a clock supply control signal asynchronous to the horizontal synchronization signal and generates various control signals synchronized with the horizontal synchronization signal.
[0017]
c) A power-on sequence command generation circuit that generates a power-on sequence command according to a control signal from the control signal generation circuit.
[0018]
d) A command selector that selects either the output signal from the operation command generation circuit or the output signal from the power-on sequence command generation circuit according to the output signal from the control signal generation circuit and outputs the selected signal to the built-in memory.
[0019]
e) A clock cutoff circuit that shuts off the clock supplied from the clock generation circuit to the built-in memory based on the control signal from the control signal generation circuit.
[0020]
With the above configuration, the present invention has the following characteristics.
[0021]
Even when a clock stop command is input by a clock supply control signal asynchronous to the horizontal synchronization signal in a system LSI having a built-in memory, the clock supply is always stopped when the built-in memory is in a standby state. Therefore, the present invention can realize low power consumption by the clock stop function in the system LSI without destroying the built-in memory.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings. FIG. 2 is an internal state transition diagram of the built-in memory. Hereinafter, the internal state transition of the memory when the clock supply to the built-in memory is interrupted / resumed will be described with reference to FIG.
[0023]
1) As shown in FIG. 2, the internal state of the built-in memory includes an operation state in which data writing / reading operation is performed, a standby state in which data writing / reading operation is not performed, and a clock supply. There are a stopped state that is stopped and an initialization state in which initialization is performed.
[0024]
2) When transitioning from the operation state to the stop state, as shown by the one-dot chain line in FIG. 2, the memory control device sets the built-in memory to the standby state by the No Operation (NOP) command, and then issues a stop command CKS. Interrupt the clock supply.
[0025]
3) When returning the built-in memory to the operating state, a state transition as shown by a dotted line in FIG. 2 is performed. First, after the clock supply to the internal memory in the stopped state is resumed by the supply command CKA to enter the standby state, the internal memory is initialized by the power-on sequence (POS) command. When the initialization is completed, the built-in memory is set in a standby state by a NOP command. Thereafter, the built-in memory transitions to an operation state according to the first operation command of the series of operation commands. In the operating state, the memory performs normal operations such as data reading and writing in accordance with operation commands input one after another.
[0026]
Hereinafter, a memory control device and a control method for controlling the memory that performs the internal state transition as described above when the clock is supplied / stopped will be described. In FIG. 1, a memory control device 60 according to the present invention includes an operation command generation circuit 10, a control signal generation circuit 20, a power-on sequence command (POS) generation circuit 30, a command selector 40, and a clock cutoff circuit 80. The control device 60 and the built-in memory 50 are configured in a one-chip system LSI 55 together with other circuits such as a CPU.
[0027]
The operation command generation circuit 10 generates a memory operation command 3 for controlling the operation state of the built-in memory 50 using the input horizontal synchronization signal 1 as a reference signal. The memory operation command 3 is output with reference to the rising edge of the horizontal synchronization signal 1, and is composed of a NOP command for setting the built-in memory 50 in a standby state and an operation command for performing a normal operation. The operation command includes a plurality of commands for causing the built-in memory 50 to read / write data.
[0028]
The control signal generation circuit 20 receives a supply control signal 2 asynchronous to the input horizontal synchronization signal 1 and generates a plurality of control signals synchronized with the horizontal synchronization signal 1. The plurality of control signals include a synchronized supply control signal 4, a selection signal 5, and a power-on sequence (POS) start signal 6. The synchronized supply control signal 4 is output to the operation command generation circuit 10 and the clock cutoff circuit 80. The selection signal 5 is output to the command selector 40. The power-on sequence (POS) start signal 6 is output to the POS command generation circuit 30. The supply control signal 2 includes a clock stop command CKS1 and a clock supply command CKA1, and the synchronized supply control signal 4 includes a clock stop command CKS2 and a clock supply command CKA2.
[0029]
The POS command generation circuit 30 generates a POS command 7 with the rising edge of the POS start signal 6 as a reference, and initializes the built-in memory 50. The command selector 40 switches between the memory operation command 3 and the POS command 7 according to the selection signal 5 and outputs it as a memory control signal 8 to the built-in memory. The built-in memory 50 operates in response to the memory control signal 8 and transitions to a standby state when a NOP command is input.
[0030]
The command selector 40 inputs the output signal of the memory operation command generation circuit 10 and the output signal of the POS command generation circuit 30, and switches and outputs two input signals according to the selection signal 5.
[0031]
In response to the synchronized supply control signal 4, the clock cutoff circuit 80 passes or blocks the clock 9 a output from the clock generation circuit 70 provided outside the system LSI 55, and outputs the clock 9 b to the built-in memory 50. To do. The synchronized supply control signal 4 includes a supply command CKA2 that instructs the clock cutoff circuit 80 to supply the clock and a stop command CKS2 that instructs the clock cutoff.
The operation of the memory control device of FIG. 1 having the above configuration will be described in more detail below with reference to FIG.
[0032]
1) First, the operation in the operating state will be described.
[0033]
In the operating state, the supply command CKA1 is input as the supply control signal 2, and the synchronized supply control signal 4 is the supply command CKA2 (FIG. 3C). Therefore, the clock is supplied to the built-in memory (FIG. 3D). Since the command selector 40 selects the memory operation command 3 according to the selection signal 5 (FIG. 3F), the memory operation command 3 synchronized with the horizontal synchronization signal (FIG. 3A) is supplied as the memory control signal 8 to the built-in memory. The operation command generation circuit 10 outputs the operation command after a predetermined time has elapsed after receiving the horizontal synchronization signal, but outputs the NOP command before the operation command output starts and after the operation command output ends (FIG. 3G , I). Therefore, the built-in memory 50 is always in a standby state before and after the horizontal synchronization signal in accordance with the NOP command (FIG. 3J).
[0034]
Following the NOP command, a plurality of operation commands are sequentially output, and the built-in memory performs a desired operation. Although omitted in the figure for simplicity, the operation command in FIG. 3G includes a plurality of operation commands.
[0035]
On the other hand, since the POS start signal 6 to be input is in a high state (FIG. 3E), the power-on sequence command generation circuit 30 continuously outputs a NOP command (FIG. 3H).
[0036]
2) Next, the clock cutoff operation will be described.
[0037]
When a clock stop command CKS1 is input at a timing asynchronous to the horizontal synchronization signal 1, the control signal generation circuit 20 outputs the stop command CKS1 as a stop command CKS2 in synchronization with the rising of the horizontal synchronization signal 1 (FIG. 3C). In the figure, when the supply control signal 2 is at the low level, it means the stop command CKS1, and when the supply control signal 4 is at the low level, it means the stop command CKS2.
[0038]
As soon as the stop command CKS2 is input, the clock cutoff circuit 80 shuts off the clock 9a and stops the clock supply to the built-in memory 50 (FIG. 3D). The built-in memory 50 transitions to a stopped state as the clock stops (FIG. 3J). When the clock supply is stopped, the internal memory 50 must be shifted to the standby state by the NOP command. However, in this embodiment, the internal memory 50 is already in the standby state by the NOP command. There is no problem even if the clock is stopped immediately after the input of the command CKS2.
[0039]
Since the selection signal 5 changes to the Low level simultaneously with the output of the stop command CKS2, the command selector 40 selects the output signal of the POS command generation circuit 30 (FIG. 3F) and outputs it to the built-in memory 50. At this time, since the memory operation command 3 input to the command selector 40 and the output signal of the POS command generation circuit 30 are NOP commands (FIG. 3G, H), the NOP command is continuously output to the built-in memory 50. (FIG. 3I). The control signal generation circuit 20 sets the POS start signal 6 to the low level simultaneously with the stop command CKS2 (FIG. 3E). By stopping the clock supply in this way, the power consumption in the standby state of the system LSI 55 is reduced.
[0040]
3) Finally, the clock supply restart operation will be described.
[0041]
When a clock supply command CKA1 is input at a timing asynchronous to the horizontal synchronization signal 1, the control signal generation circuit 20 outputs the supply command CKA1 in synchronization with the rising of the horizontal synchronization signal 1 as a supply command CKA2 (FIG. 3C). . In the figure, when the supply control signal 2 is at a high level, it means the supply command CKA1, and when the supply control signal 4 is at a high level, it means the supply command CKA2.
[0042]
As soon as the supply command CKA2 is input, the clock cutoff circuit 80 passes the clock 9a and starts supplying the clock 9b to the built-in memory 50 (FIG. 3D). The built-in memory 50 transitions to a standby state as the clock supply resumes (FIG. 3J). At this time, the memory control signal 8 is a NOP command output from the POS command generation circuit 30 (FIG. 3I).
[0043]
The control signal generation circuit 20 sets the POS start signal 6 to the high level after a predetermined time since the supply command CKA2 is output (FIG. 3E). The POS command generation circuit 30 outputs a POS command with a POS start signal as a cue (FIG. 3H). The built-in memory 50 is initialized according to the POS command supplied via the command selector 40 (FIG. 3I, J). After the output of the POS command is completed, the POS command generation circuit 30 outputs a NOP command and causes the built-in memory 50 to transition to the standby state.
[0044]
After the clock supply restart and the memory initialization are performed in this manner, the control signal generation circuit 20 changes the selection signal 5 to the high level with reference to the horizontal synchronization signal that gives the timing of the clock supply restart. The command selector 40 switches to select the memory operation command 3 in response to the selection signal 5. At this time, since the memory operation command 3 and the POS command 7 input to the command selector 40 are both NOP commands (FIG. 3G, H), the NOP command continues to be output to the built-in memory 50 even when the signal to be selected is switched. (FIG. 3I).
[0045]
An operation command is output based on the horizontal synchronization signal next to the horizontal synchronization signal given the timing of the supply command CKA2, and the built-in memory 50 starts a data read / write operation.
[0046]
As described in detail above, according to the memory control device of the present invention, the power consumption of the system LSI 55 in the standby state can be reduced without destroying the elements of the built-in memory.
[0047]
In the above embodiment, since the internal memory is guaranteed to be in a standby state at the time of input of the horizontal synchronization signal, the clock supply to the internal memory is stopped immediately after the horizontal synchronization signal is input. ing. However, considering safety, it may be possible to stop the clock supply after outputting the NOP command until a predetermined time elapses.
[0048]
【The invention's effect】
As described above, according to the memory control device of the present invention, in a system LSI or the like having a built-in memory,
(1) Considering the internal state of the internal memory, the clock supply can be stopped without destroying the internal memory.
(2) By stopping the clock supply, the power consumption of the built-in memory in the standby state can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram of a memory control device according to an embodiment of the present invention. FIG. 2 is an internal state transition diagram of a built-in memory. FIG. 4 is a diagram showing an example of a circuit for executing a conventional clock stop control method.
1 horizontal synchronization signal 2 supply control signal 3 memory operation command 4 synchronized supply control signal 5 selection signal 6 POS start signal 7 POS command 8 memory control signal 10 operation command generation circuit 20 control signal generation circuit 30 POS generation circuit 40 command Selector 50 Built-in memory 55 System LSI
60 memory control device 70 clock generation circuit 80 clock cutoff circuit 101 signal processing circuit 102 control signal generation circuit

Claims (12)

A memory control device for controlling a memory,
A control signal generation circuit that synchronizes an input clock stop command and a clock supply command with a reference signal and outputs them as a synchronized stop command and supply command, respectively,
A clock cut-off circuit for receiving the synchronized stop command to stop the clock supply to the memory and receiving the synchronized supply command to start the clock supply to the memory;
In the normal operation, an operation command is output to the memory using a reference signal as a timing reference. When the synchronized stop command is received, the operation command is not output, and when the synchronized supply command is received. A memory control device comprising: an operation command generation circuit for restarting output of an operation command.   2. The memory control device according to claim 1, wherein the clock cutoff circuit stops clock supply when the memory is in a standby state.   3. The memory control device according to claim 2, wherein the operation command generation circuit receives the synchronized stop command and outputs a NOP command, and then the clock cutoff circuit stops the clock supply. A POS command generation circuit that outputs a POS command in response to a POS start signal output from the control signal generation circuit;
And a command selector for selecting either the operation command or the POS command and outputting the selected command to the memory in response to a selection signal synchronized with the synchronized stop command or the synchronized supply command. The memory control device according to claim 1.   5. The memory control device according to claim 4, wherein the control signal generation circuit switches the selection signal at the latest before the generation of the POS command.   The POS command generation circuit outputs a NOP command after the generation of the POS command is completed, and the control signal generation circuit switches a selection signal when the NOP command is output after the generation of the POS command is completed. Item 5. The memory control device according to Item 4.   The memory control device according to claim 1, wherein the memory is a memory having an internal state.   The memory control device according to claim 1, wherein the memory is built in a semiconductor provided with the memory control device. A memory control method for controlling a memory, comprising:
An operation command is output to the memory using a reference signal as a timing reference in normal operation;
A stop command synchronization step for synchronizing an input clock stop command with a reference signal and outputting it as a synchronized stop command;
A clock stop step for receiving the synchronized stop command and stopping the clock supply to the memory;
A supply command synchronization step of synchronizing an input clock supply command with a reference signal and outputting as a synchronized supply command;
And a clock resuming step of receiving a clocked supply to the memory in response to the synchronized supply command.   10. The memory control method according to claim 9, wherein in the clock stop step, the clock supply is stopped when the memory is in a standby state.   11. The memory control method according to claim 10, further comprising a step of outputting a NOP command in response to the synchronized stop command between the stop command synchronization step and the clock stop step.   The memory control method according to claim 9, further comprising a step of outputting a POS command to the memory after the clock restarting step.

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