JP4382136B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine, a coin gaming machine, or a slot machine in which a game is performed according to a player's operation, and particularly, a game is performed according to a player's operation in a gaming area on a gaming board. It relates to gaming machines.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. The game medium is paid out by a payout mechanism. The payout mechanism is controlled by the payout control means. Accordingly, the game control means for controlling the game progress of the gaming machine instructs the payout control board the number of winning balls corresponding to the winning. The payout control means controls to pay out the number of game media according to the instruction from the payout mechanism.

  Further, the player receives a game ball by lending a coin or inserting a prepaid card or the like into a card insertion slot. The payout mechanism of the gaming machine detects coin insertion or card insertion and pays out a predetermined number of game balls to the player. Since the payout mechanism is controlled by the payout control means, the game ball lending control is also executed by the payout control means.

  In general, game balls to be paid out to a player are stored in a game ball storage section on the back of the gaming machine. Since the game ball cannot be paid out when there is no stored ball in the game ball storage unit, a sensor for detecting the game ball is provided in the game ball storage unit or downstream of the storage unit. Then, when it is detected by the sensor that the stored ball has run out, the game control means notifies the payout control means that there has been no stored ball for paying out. Further, when it is detected that game balls for payout have accumulated in the game ball storage unit, the game control means notifies the payout control means to that effect.

  The paid-out game balls are stored in a hitting ball supply tray provided at the lower part of the gaming machine. A surplus ball receiving tray (bottom plate) for storing game balls overflowing from the hitting ball supply tray is provided below the hitting ball supply tray. However, there is a limit to the amount that can be stored in the lower plate, and it is not possible to store the game ball beyond the allowable amount. Therefore, a sensor for detecting the game ball is also provided in the lower plate. Then, when it is detected by the sensor that the stored ball has reached the allowable amount, the game control means notifies the payout control means that the lower pan is full. Further, when it is detected that the lower pan full has been eliminated, the game control means notifies the payout control means accordingly.

Some gaming machines execute a process for saving a control state when power supply is stopped, and execute a state recovery process when power supply is started.

The present invention provides a gaming machine capable of preventing a process for saving a control state from being repeatedly executed when a process for saving a control state is executed when power supply is stopped. With the goal.

The gaming machine according to the present invention is a gaming machine that can give a game result value to a player as a result of performing a predetermined game, and when power is supplied, the content immediately before the power supply is stopped It is possible to perform game state return control for returning the game state based on the stored contents held in the storage means that can be held, and to detect the game control means for controlling the progress of the game and the game medium And a game medium detecting means for monitoring the power supply voltage higher than a voltage supplied to the game medium detecting means, and outputting a voltage drop signal to the game control means when the power supply voltage becomes a predetermined value or less. and a monitoring means, the game control means includes a game control microcomputer, the voltage drop signal from the power supply monitoring means, is inputted to the interrupt terminal of the game control microcomputer, game control Ma The black computer performs a predetermined power-off process based on an interrupt according to the voltage drop signal from the power supply monitoring means, and performs an interrupt process if an interrupt occurs even after executing the power-off process. It is possible to start up, and after executing the power-off process, the power-off process is not executed even when the interrupt is generated again and the interrupt process is started .

According to the present invention, the gaming control microcomputer executes a predetermined power-off process based on an interrupt corresponding to the voltage drop signal from the power supply monitoring means, and executes the power-off process. If an interrupt occurs later, the interrupt process can be started, and even if the interrupt occurs again after executing the power-off process, the power-off process is not executed. Since it comprised as mentioned above, when performing the process for preserve | saving a control state when an electric power supply stops, there exists an effect which can prevent performing the process for preserve | saving a control state redundantly .

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front, FIG. 2 is an overall rear view showing the internal structure of the pachinko gaming machine 1, and FIG. Here, a pachinko gaming machine is shown as an example of a gaming machine, but the present invention is not limited to a pachinko gaming machine and may be, for example, a coin gaming machine or a slot machine.

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray 3. Under the hitting ball supply tray 3, there are provided an extra ball receiving tray 4 for storing a payout ball overflowing from the hitting ball supply tray 3 and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the rear side of the glass door frame 2. A game area 7 is provided in front of the game board 6.

  Near the center of the game area 7, there is provided a variable display device 8 including a variable display unit 9 for variably displaying a plurality of types of symbols and a variable display 10 using 7 segment LEDs. In this embodiment, the variable display section 9 has three symbol display areas of “left”, “middle”, and “right”. A passing gate 11 for guiding a hit ball is provided on the side of the variable display device 8. The hit ball that has passed through the passing gate 11 is guided to the start winning opening 14 through the ball outlet 13. In the passage between the passage gate 11 and the ball exit 13, there is a gate switch 12 that detects a hit ball that has passed through the passage gate 11. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 17. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. In this embodiment, the opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V zone) is detected by the V count switch 22. A winning ball from the opening / closing plate 20 is detected by the count switch 23. At the bottom of the variable display device 8, a start winning memory display 18 having four display units for displaying the number of winning balls that have entered the start winning opening 14 is provided. In this example, with the upper limit being four, each time there is a start prize, the start prize storage display 18 increases the number of lit display units one by one. Then, each time the variable display of the variable display unit 9 is started, the lit display unit is reduced by one.

  The game board 6 is provided with a plurality of winning openings 19, 24, and winning of the game balls to the winning openings 19, 24 is detected by winning opening switches 19a, 24a. Decorative lamps 25 blinking during the game are provided around the left and right sides of the game area 7, and an outlet 26 for absorbing a hit ball that has not won a prize is provided below. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a game effect LED 28a and game effect lamps 28b and 28c are provided.

  In this example, a prize ball lamp 51 that is lit when there is a remaining number of prize balls is provided in the vicinity of one speaker 27, and a sphere that is lit when a supply ball is cut near the other speaker 27. A cut lamp 52 is provided. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 has a usable indicator lamp 151 indicating whether or not it is in a usable state, and when the remaining amount information recorded in the card has a fraction (a number less than 100 yen), the fraction is indicated as a hitting tray. 3, a fraction display switch 152 for displaying on a frequency display LED provided in the vicinity of 3, a connecting table direction indicator 153 indicating which side of the pachinko gaming machine 1 corresponds to the card unit 50, in the card unit 50 Check the card insertion indicator lamp 154 indicating that a card is inserted, the card insertion slot 155 into which a card as a recording medium is inserted, and the mechanism of the card reader / writer provided on the back of the card insertion slot 155. In some cases, a card unit lock 156 is provided for releasing the card unit 50.

  The hit ball fired from the hit ball launching device enters the game area 7 through the hit ball rail, and then descends the game area 7. When the hit ball is detected by the gate switch 12 through the passing gate 11, the display number of the variable display 10 changes continuously. Further, when the hit ball enters the start winning opening 14 and is detected by the start opening switch 17, the symbol in the variable display portion 9 starts to rotate if the variation of the symbol can be started. If it is not in a state where the change of the symbol can be started, the start winning memory is increased by 1.

  The rotation of the image in the variable display unit 9 stops when a certain time has elapsed. If the combination of images at the time of the stop is a combination of jackpot symbols, the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of hit balls wins. When the hit ball enters the specific winning area while the opening / closing plate 20 is opened and is detected by the V count switch 22, a right to continue is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds).

  When the combination of images in the variable display section 9 at the time of stop is a combination of jackpot symbols with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in a high probability state. Further, when the stop symbol on the variable display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the high probability state, the probability that the stop symbol in the variable display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased.

Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG.
On the back surface of the variable display device 8, as shown in FIG. 2, a ball storage tank 38 is provided on the upper part of the mechanism plate 36. The sphere storage tank 38 is supplied. The game balls in the ball storage tank 38 reach the ball payout device through the guide rod 39.

  The mechanism plate 36 includes a variable display control unit 29 for controlling the variable display unit 9 via the relay board 30, a game control board (main board) 31 covered with a board case 32 and mounted with a game control microcomputer, etc. A relay board 33 for relaying a signal between the variable display control unit 29 and the game control board 31, and a payout control board 37 on which a payout control microcomputer for performing the payout control of the game ball is mounted. Yes. Further, at the lower part of the mechanism plate 36, a hitting ball launching device 34 that launches a hitting ball into the game area 7 using the rotational force of the motor, game effect lamps / LEDs 28a, 28b, 28c, a prize ball lamp 51, and a ball break lamp A lamp control board 35 for sending a signal to 52 is installed.

  FIG. 3 is a rear view of the mechanism plate of the pachinko gaming machine 1 as seen from the back. The balls stored in the ball storage tank 38 pass through the guide rod 39 and pass through the ball break detectors (ball break switches) 187a and 187b, as shown in FIG. 3, through the ball supply rods 186a and 186b. Device 97 is reached. The game balls paid out from the ball payout device 97 are supplied to the hitting ball supply tray 3 provided on the front surface of the pachinko gaming machine 1 through the connection port 45. A surplus ball passage 46 communicating with the surplus ball receiving tray 4 provided on the front surface of the pachinko gaming machine 1 is formed on the side of the communication port 45. A lot of prize balls based on the winnings are paid out, the hitting ball supply tray 3 is filled, and when the game balls are finally paid out after reaching the contact hole 45, the game balls are surplus through the surplus ball passage 46. It is guided to the ball receiving tray 4. When the game ball is further paid out, the sensing lever 47 presses the full tank switch 48 and the full tank switch 48 is turned on. In this state, the rotation of the stepping motor in the ball dispensing device 97 is stopped, the operation of the ball dispensing device 97 is stopped, and the driving of the ball hitting device 34 is also stopped.

  In order to perform prize ball payout control, signals from a winning opening switch (not shown), the start opening switch 17 and the V count switch 22 are sent to the main board 31. The CPU 56 of the main board 31 knows that a winning corresponding to six prize ball payout has occurred when the start port switch 17 is turned on. Further, when the count switch 23 is turned on, it is known that a winning corresponding to 15 prize ball payouts has occurred. Then, when the winning opening switch is turned on, it is known that a winning corresponding to ten winning ball payouts has occurred. In this embodiment, for example, a game ball won in the winning opening 24 is detected by a winning opening switch 24 a provided in a winning ball flow path from the winning opening 24 and won in the winning opening 19. Is detected by a winning port switch 19a provided in a winning ball flow path from the winning port 19.

  Next, the configuration of the intermediate base unit installed on the mechanism plate 36 will be described. In the intermediate base unit, ball supply rods 186a and 186b and a ball dispensing device 97 are installed. As shown in FIG. 4, connection concave protrusions 182 are formed on the upper and lower sides of the intermediate base unit. The connection concave protrusion 182 connects and fixes the intermediate base unit and the upper base unit and the lower base unit of the mechanism plate 36.

  A passage body 184 is fixed to the upper part of the intermediate base unit. A ball dispensing device 97 is fixed to the lower part of the passage body 184. The passage body 184 has payout ball passages 186a and 186b for flowing down two rows of game balls whose flow direction has been changed to the left and right directions by a curve rod 174 (see FIG. 3). On the upstream side of the payout ball passages 186a, 186b, ball break switches 187a, 187b are installed. The ball cut switches 187a and 187b detect the presence or absence of a game ball in the payout ball passages 186a and 186b. When the ball cut switches 187a and 187b no longer detect a game ball, The rotation of the ball (not shown in FIG. 4) is stopped and the ball payout is immobilized.

  The ball break switches 187a and 187b are locked by locking pieces 188 at positions where it can be detected that about 27 to 28 game balls are present in the payout ball passages 186a and 186b.

  The central portion of the passage body 184 is formed in a shape that curves to the left and right so as to weaken the ball pressure of the game ball flowing down inside. A stop hole 189 is formed between the payout ball passages 186a and 186b. A mounting boss provided in the intermediate base unit is fitted into the back surface of the stop hole 189. In this state, the set screw is screwed, and the passage body 184 is fixed to the intermediate base unit. The passage body 184 can be aligned by the locking protrusion 185 provided on the intermediate base unit before being screwed.

  Below the passage body 184, a ball stopper 190 is provided for supplying the game ball to the ball payout device 97 and stopping the supply of the game ball to the ball payout device 97 in the event of a failure. A ball payout device 97 installed below the ball stopper 190 is housed in a rectangular parallelepiped case 198. Projections are provided at four places on the left and right sides of the case 198. The lower end of the case 198 is fitted into the elastic engagement piece provided at the lower part of the intermediate base unit in a state where each protrusion is engaged with the positioning protrusion provided on the intermediate base unit.

  FIG. 5 is an exploded perspective view of the ball dispensing device 97. The configuration and operation of the ball dispensing device 97 will be described with reference to FIG. In the ball dispensing device 97 in this embodiment, a stepping motor (dispensing motor) 289 rotates a screw 288 to pay out pachinko balls one by one. Note that the ball payout device 97 pays out not only a prize ball based on a prize but also a game ball to be lent.

  As shown in FIG. 5, the ball dispensing device 97 has two cases 198a and 198b. Engagement protrusions 280 are provided at two positions on the left and right sides of the cases 198a and 198b. In addition, ball supply paths 281a and 281b are formed in the cases 198a and 198b, respectively. The ball supply paths 281a and 281b have curved surfaces 282a and 282b, and ball feed horizontal paths 284a and 284b are formed below the ends of the curved surfaces 282a and 282b. Furthermore, ball discharge paths 283a and 283b are formed at the ends of the ball feed horizontal paths 284a and 284b.

  The ball supply paths 281a and 281b, the ball feed horizontal paths 284a and 284b, and the ball discharge paths 283a and 283b are formed in front of partition walls 295a and 295b that divide the cases 198a and 198b in the front-rear direction. Further, a ball pressure buffering member 285 is sandwiched between the cases 198a and 198b in front of the partition walls 295a and 295b. The ball pressure buffering member 285 distributes the balls supplied to the ball dispensing device 97 to the left and right sides and guides the balls to the ball supply paths 281a and 281b.

  In addition, below the ball pressure buffering member 285, a payout motor position sensor using a light emitting element (LED) 286 and a light receiving element (not shown) is provided. The light emitting element 286 and the light receiving element are provided at a predetermined interval. The tip of the screw 288 is inserted within this interval. The ball pressure buffering member 285 is completely housed and fixed inside the cases 198a and 198b.

  Screws 288 that are rotated by a payout motor 289 are disposed in the ball feed horizontal paths 284a and 284b. The payout motor 289 is fixed to the motor fixing plate 290, and the motor fixing plate 290 is fitted into fixing grooves 291a and 291b formed at the rear of the partition walls 295a and 295b. In this state, the motor shaft of the payout motor 289 protrudes in front of the partition walls 295a and 295b, so that the screw 288 is fixed in front of the protrusion. On the outer periphery of the screw 288, there is provided a spiral projection 288a for moving the game ball placed on the ball feed horizontal paths 284a, 284b forward by the rotation of the payout motor 289.

  A recess is formed at the tip of the screw 288 so as to accommodate the light emitting element 286, and two notches 292 are formed 180 degrees apart from each other on the outer periphery of the recess. Therefore, during one rotation of the screw 288, the light from the light emitting element 286 is detected twice by the light receiving element through the notch 292.

  In other words, the payout motor position sensor including the light emitting element 286 and the light receiving element is for stopping the screw 288 at a fixed position, and detects that the payout operation has been performed. The wiring from the light emitting element 286, the light receiving element, and the payout motor 289 are collectively drawn out from a drawing hole formed below the rear portions of the cases 198a and 198b and connected to the connector.

  When the payout motor 289 rotates in a state where the game ball is placed on the ball feed horizontal paths 284a and 284b, the game ball is moved forward on the ball feed horizontal paths 284a and 284b by the spiral protrusion 288a of the screw 288. Moving. And finally, it falls to the ball discharge paths 283a and 283b from the end of the ball feed horizontal paths 284a and 284b. At this time, the left and right ball feed horizontal paths 284a and 284b are alternately dropped. That is, each time the screw 288 is rotated halfway, one game ball falls from one side. Therefore, each time one game ball falls, the light from the light emitting element 286 is detected by the light receiving element.

  As shown in FIG. 4, a ball sorting member 311 is provided below the ball dispensing device 97. The ball sorting member 311 is driven by the sorting solenoid 310. For example, when the solenoid 310 is on, the ball sorting member 311 falls to the right, and when it is off, the ball sorting member 311 falls to the left. Below the sorting solenoid 310, a prize ball count switch 301A and a ball lending count switch 301B by proximity switches are provided. At the time of a winning ball based on winning, the ball sorting member 311 falls to the right, and the balls from the ball discharge paths 283a and 283b both pass the winning ball count switch 301A. Further, at the time of lending a ball, the ball sorting member 311 falls to the left side, and balls from the ball discharge paths 283a and 283b both pass the ball lending count switch 301B. Accordingly, the ball payout device 97 can change the payout flow path between the winning ball and the ball lending and pay out a predetermined number of game media.

  In this way, by providing the ball sorting member 311, the ball that has fallen through the two ball passages passes only one of the prize ball count switch 301 </ b> A and the ball lending count switch 301 </ b> B. Accordingly, the number of winning balls or the number of balls lent can be immediately grasped from the detection outputs of the winning ball count switch 301A and the ball lending count switch 301B without determining whether the ball is a winning ball or a lending ball.

  FIG. 6 is a block diagram illustrating an example of a circuit configuration in the main board 31. 6 also shows the payout control board 37, the lamp control board 35, the sound control board 70, the launch control board 91, and the display control board 80. The main circuit board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 12, a start port switch 17, a V count switch 22, a count switch 23 winning port switches 19a and 24a, a full switch 48 and a prize. A switch circuit 58 for supplying a signal from the ball count switch 301A to the basic circuit 53, and a solenoid circuit 59 for driving the solenoid 16 for opening / closing the variable winning ball apparatus 15 and the solenoid 21 for opening / closing the opening / closing plate 20 in accordance with a command from the basic circuit 53. And a lamp / LED circuit 60 for turning on and off the start-up memory display 18 and driving the variable display 10 using the 7-segment LED and the decorative lamp 25.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the starting information indicating the number of starting winning balls used for starting the image display of the variable display unit 9, and the probability change indicating that the probability variation has occurred. An information output circuit 64 for outputting information and the like to a host computer such as a hall management computer is included.

  The basic circuit 53 includes a ROM 54 that stores a game control program and the like, a RAM 55 that is an example of storage means used as a work memory, a CPU 56 that performs a control operation in accordance with a control program, and an I / O port unit 57. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to incorporate at least the RAM 55, and the ROM 54 and the I / O port unit 57 may be externally attached or built-in. The I / O port unit 57 is a terminal capable of inputting and outputting information in the microcomputer.

Further, the main board 31 includes an initial reset circuit 65 for resetting the basic circuit 53 when power is turned on, and an address signal supplied from the basic circuit 53 to decode any I / O port 57. An address decode circuit 67 for outputting a signal for selecting the / O port is provided.
In addition, there is switch information input to the main board 31 from the ball dispensing device 97, but these are omitted in FIG.

  A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the firing control board 91 is controlled so that the hit ball is fired at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the CPU 56 of the main board 31 performs display control of the variable display (ordinary symbol display) 18, but the normal symbol display is also controlled by display control means mounted on the display control board 80. You may comprise so that it may be controlled. The lamp control means mounted on the lamp control board 35 may also be configured to control lamps / LEDs in the game area.

  FIG. 7 is a block diagram showing components related to a prize ball, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 7, the detection signal from the full switch 48 is input to the I / O port 57 of the main board 31 through the relay board 71. The full tank switch 48 is a switch for detecting a full tank of the surplus ball receiving tray 4.

  A detection signal from the ball break switch 187 (187a, 187b) is input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The ball break detection switch 167 is a switch for detecting the shortage of replenishment balls in the ball storage tank 38, and the ball break switch 187 is a switch for detecting the presence or absence of a game ball in the payout ball passage.

  When there is a win, a prize ball control command indicating the number of prize balls is input from the main board 31 to the payout control board 37. A prize ball control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373. Each buffer in the input buffer circuit 373 can pass a signal only in the direction from the main board 31 toward the payout control board 37. Therefore, there is no room for signals to be transmitted from the payout control board 37 side to the main board 31 side. Even if unauthorized modification is added to the circuit in the payout control board 37, a signal output by the unauthorized modification is not transmitted to the main board 31 side. In the main board 31, a buffer circuit 68 (irreversible transmission means) is provided outside the output ports 577 and 578 for outputting a prize ball control command. According to such a configuration, since a signal input from the outside to the inside of the main board 31 is blocked, a signal line in which a signal may be given from the payout control board 37 to the main board 31 is more reliably eliminated. be able to.

  The CPU 56 of the main board 31 instructs the ball payout prohibition when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Send out a prize ball control command. When receiving a prize ball control command instructing prohibition of ball payout, the payout control CPU 371 of the payout control board 37 stops the ball payout process.

  Further, detection signals from the prize ball count switch 301A and the ball lending count switch 301B are also input to the I / O port 57 of the main board 31 via the relay board 72 and the relay board 71. The prize ball count switch 301A and the ball lending count switch 301B are provided in the prize ball mechanism portion of the ball payout device 97, and detect the prize balls actually paid out.

  When there is a prize, a prize ball control command indicating the number of prize balls is input to the payout control board 37 from the output ports (ports G and H) 577 and 578 of the main board 31. The output port 577 outputs 8-bit data, and the output port 578 outputs a 1-bit strobe signal (INT signal). A prize ball control command indicating the number of prize balls is input to the I / O port 372a via the input buffer circuit 373. The payout control CPU 371 inputs a prize ball control command via the I / O port 372a and drives the ball payout device 97 in accordance with the prize ball control command to perform a prize ball payout. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  The payout control CPU 371 outputs a ball lending number signal indicating the number of lending balls to the terminal board 160 and a buzzer driving signal to the buzzer board 75 via the output port 372g. A buzzer is mounted on the buzzer substrate 75. Further, an error signal is output to the error display LED 374 via the output port 372e.

  Further, the detection signal of the detection signal of the prize ball count switch 301 </ b> A is input to the input port 372 b of the payout control board 37 via the relay board 72. A drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the prize ball mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72. The drive signal from the dispensing control board 37 to the sorting solenoid 310 is transmitted to the sorting solenoid 310 of the ball dispensing apparatus 97 via the output port 372d and the relay board 72.

  The card unit 50 is equipped with a card unit control microcomputer. Further, the card unit 50 is provided with a fraction display switch 152, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The balance display board 74 is connected with a frequency display LED, a ball lending switch, and a return switch provided in the vicinity of the hitting ball supply tray 3.

  A ball lending switch signal and a return switch signal are given from the balance display board 74 to the card unit 50 via the payout control board 37 in accordance with the player's operation. Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given to the balance display board 74 from the card unit 50 via the payout control board 37. Between the card unit 50 and the payout control board 37, a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal), and a pachinko machine operation signal (PRDY signal) are I / O. Exchanged via port 372f.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37. The payout control CPU 371 of the payout control board 37 turns on the XS signal in response to the BRQ signal and drives the payout motor 289 to pay out a predetermined number of lending balls to the player. When the payout is completed, the payout control CPU 371 sets the EXS signal to the card unit 50 in the OFF state.

  As described above, all signals from the card unit 50 are input to the payout control board 37. Accordingly, with respect to the ball lending control, no signal is input from the card unit 50 to the main board 31, and there is no room for an illegal signal input from the card unit 50 side to the basic circuit 53 of the main board 31. The main board 31 and the payout control board 37 are mounted with driver circuits for driving solenoids, motors and lamps, but these circuits are omitted in FIG.

  In this embodiment, the RAM in the main board 31 and the payout control board 37 is backed up by a backup power source. That is, even if the power supply to the gaming machine is stopped, the contents of the RAM are saved for a predetermined period. When each CPU detects a decrease in power supply voltage, it performs a predetermined process and waits for power recovery. Further, when the power is turned on, each CPU restores the state before the power is turned off based on the stored data when the data is stored in the RAM.

  FIG. 8 is a block diagram showing an example of the configuration around the CPU 56 for power supply monitoring and power supply backup. As shown in FIG. 8, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is connected to the non-maskable interrupt terminal (NMI terminal) of the CPU 56. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is + 30V in this example. Therefore, the CPU 56 can confirm the occurrence of power interruption by the interrupt process. In this embodiment, the first power supply monitoring circuit is mounted on a power supply board described later.

  Although the initial reset circuit 65 is also shown in FIG. 8, in this embodiment, the initial reset circuit 65 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, when the power is turned on, the reset IC 651 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level when the predetermined time has elapsed. That is, the reset signal is raised to a high level to make the CPU 56 operable. The reset IC 651 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit, and the voltage value is a predetermined value (the first power supply monitoring circuit outputs a voltage drop signal). When the voltage is lower than the power supply voltage value), a low level voltage drop signal is generated. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the voltage drop signal from the first power supply monitoring circuit, and then the system is reset. In this embodiment, the reset signal and the voltage drop signal from the second power supply monitoring circuit are the same signal.

  As shown in FIG. 8, the reset signal from the reset IC 651 is input to the NAND circuit 947 and also input to the clear terminal of the counter IC 941 via the inverting circuit (NOT circuit) 944. The counter IC 941 counts the clock signal from the oscillator 943 when the input to the clear terminal becomes low level. The Q5 output of the counter IC 941 is input to the NAND circuit 947 via the NOT circuits 945 and 946. The Q6 output of the counter IC 941 is input to the clock terminal of the flip-flop (FF) 942. The D input of the flip-flop 942 is fixed at a high level, and the Q output is input to an OR circuit (OR circuit) 949. The output of the NAND circuit 947 is introduced into the other input of the OR circuit 949 via the NOT circuit 948. The output of the OR circuit 949 is connected to the reset terminal of the CPU 56. According to such a configuration, since the reset signal (low level signal) is given twice to the reset terminal of the CPU 56 when the power is turned on, the CPU 56 surely starts operation.

  For example, the detection voltage of the first power supply monitoring circuit (voltage that outputs a voltage drop signal) is + 22V, and the detection voltage of the second power supply monitoring circuit is + 9V. In such a configuration, since the first power monitoring circuit and the second power monitoring circuit monitor the voltage of the same power supply VSL, the timing when the first voltage monitoring circuit outputs the voltage drop signal. And the timing at which the second voltage monitoring circuit outputs the voltage drop signal can be reliably set to a desired predetermined period. The desired predetermined period is a period from when the power supply stop process is started in response to the voltage drop signal from the first power supply monitoring circuit until the power supply stop process is reliably completed.

  In this example, the first detection condition for the first power supply monitoring means to output the detection signal is that the + 30V power supply voltage has dropped to + 22V, and the second power supply monitoring means outputs the detection signal. The second detection condition that becomes is that the + 30V power supply voltage is lowered to + 9V. However, the voltage value used here is an example, and other values may be used.

  However, although the monitoring range is narrowed, it is also possible to use a + 5V power supply voltage as the monitoring voltage of the first voltage monitoring circuit and the second voltage monitoring circuit. Also in that case, the detection voltage of the first voltage monitoring circuit is set higher than the detection voltage of the second voltage monitoring circuit.

  While power is not supplied from the + 5V power source that is the driving power source of the CPU 56 or the like, at least a part of the RAM is backed up by the backup power source supplied from the power supply board, and the contents are preserved even if the power source for the gaming machine is cut off. The When the + 5V power supply is restored, a reset signal is issued from the initial reset circuit 65, so that the CPU 56 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to return to the gaming state at the time of the power failure when recovering from the power failure.

  Although FIG. 8 shows a configuration in which a reset signal (low level signal) is given to the reset terminal of the CPU 56 when the power is turned on, the reset is reliably released even if the reset signal rises only once. When using the CPU to be used, the circuit elements denoted by reference numerals 941 to 949 are not necessary. In that case, the output of the reset IC 651 is directly connected to the reset terminal of the CPU 56.

  FIG. 9 is a block diagram illustrating a configuration example of the power supply board 910 of the gaming machine. The power supply board 910 is installed independently of the electric component control boards such as the main board 31, the display control board 80, the voice control board 70, the lamp control board 35, and the payout control board 37, and each electric component control board in the gaming machine and Generates voltage used by mechanical components. In this example, AC24V, VSL (DC + 30V), DC + 21V, DC + 12V, and DC + 5V are generated. A capacitor 916 serving as a backup power supply is charged from a line of power supply for driving DC + 5V, that is, an IC or the like on each substrate.

  The transformer 911 converts AC voltage from the AC power source into 24V. The AC 24V voltage is output to the connector 915. The rectifier circuit 912 also generates a DC voltage of +30 V from AC 24 V and outputs it to the DC-DC converter 913 and the connector 915. The DC-DC converter 913 generates + 22V, + 12V, and + 5V and outputs them to the connector 915. The connector 915 is connected to, for example, a relay board, and power of a voltage necessary for each electric component control board and the mechanism component is supplied from the relay board. Note that a power switch 918 for stopping or starting the power supply to the gaming machine is installed on the input side of the transformer 911.

  The + 5V line from the DC-DC converter 913 branches to form a backup + 5V line. A large-capacitance capacitor 916 is connected between the backup + 5V line and the ground level. Capacitor 916 has power so that the storage state can be maintained with respect to the backup RAM of the electrical component control board when the power supply to the gaming machine is cut off (RAM that is backed up by power, that is, storage means that can be in the storage content storage state). Backup power supply. Further, a backflow preventing diode 917 is inserted between the + 5V line and the backup + 5V line.

  A battery that can be charged from a + 5V power supply may be used as the backup power supply. In the case of using a battery, a rechargeable battery is used in which the capacity disappears when a state in which no power is supplied from the +5 V power source continues for a predetermined time.

  The power supply board 910 is mounted with a power monitoring IC 902 that constitutes the first power monitoring circuit described above. The power monitoring IC 902 detects the occurrence of power interruption by introducing the VSL power supply voltage and monitoring the VSL power supply voltage. Specifically, when the VSL power supply voltage becomes equal to or lower than a predetermined value (+22 V in this example), a voltage drop signal is output because the power supply is cut off. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used. The voltage drop signal from the power monitoring IC 902 is supplied to the main board 31, the payout control board 37, and the like.

  The predetermined value for the power monitoring IC 902 to detect the power-off is lower than the normal voltage, but is a voltage that allows the CPU on each electrical component control board to operate for a while. Further, the power monitoring IC 902 is configured to monitor a voltage that is higher than a voltage for driving a circuit element such as a CPU (+5 V in this example) and immediately after being converted from AC to DC. Therefore, the monitoring range can be expanded for the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop. Therefore, when the voltage of the + 12V power supply decreases, the switch output becomes in the on state. However, if the power supply interruption is recognized by monitoring the + 30V power supply voltage that decreases faster than + 12V, the switch output becomes the power It is possible to enter a state of waiting for recovery and not detect switch output.

  Further, since the power monitoring IC 902 is mounted on the power supply board 910 separate from the electric component control board, the voltage drop signal can be supplied from the first power supply monitoring circuit to the plurality of electric component control boards. Even if there are any number of electrical component control boards that require a voltage drop signal, it is only necessary to provide one first power supply monitoring means. Therefore, each electrical component control means in each electrical component control board performs the return control described later. Even if it goes, the cost of the gaming machine does not rise so much.

  In the configuration shown in FIG. 9, the detection output (voltage drop signal) of the power supply monitoring IC 902 is supplied to the respective electric component control boards (for example, the main board 31 and the payout control board 37) via the buffer circuits 918 and 919. However, for example, a configuration may be adopted in which one detection output is transmitted to the relay board and the same signal is distributed from the relay board to each electric component control board. Further, a buffer circuit corresponding to the number of substrates that require a voltage drop signal may be provided.

Next, the operation of the gaming machine will be described.
FIG. 10 is a flowchart showing main processing executed by the CPU 56 on the main board 31. When the power to the gaming machine is turned on, in the main process, the CPU 56 first confirms whether or not it is a time of recovery from a power failure (step S1). Whether or not the power failure has been recovered is confirmed by, for example, a power-off flag set in the backup RAM area when the power is cut off.

  If it is time to recover from a power failure, a data check (parity check in this example) of the backup RAM area is performed (step S3). In the case of recovery after an unexpected power failure, the data in the backup RAM area should have been saved, so the check result is normal. If the check result is not normal, the internal state cannot be returned to the state when the power is cut off, and therefore an initialization process that is executed when the power is turned on not when the power failure is restored is executed (steps S4 and S2).

  If the check result is normal, the CPU 56 performs a game state recovery process for returning the internal state to the state at the time of power-off (step S5) and clears the power-off flag (step S6).

  If it is not time to recover from a power failure, the CPU 56 executes normal initialization processing (steps S1 and S2). Thereafter, in the main process, the process proceeds to a loop process in which the monitoring of the timer interrupt flag (step S6) is confirmed. In the loop, display random number update processing (step S7) is also executed.

  Here, it is confirmed in step S1 whether or not the recovery from the power failure, and if the recovery from the power failure, the parity check is performed. First, the parity check is performed and the check result is not normal. If it is determined that the power is not recovered from the power failure, the initialization process of step S2 is executed. If the check result is normal, the game state return process may be performed. That is, it may be determined whether or not recovery from a power failure is made based on the result of the parity check.

  Further, when determining whether or not to execute the power failure recovery processing, that is, when determining whether or not to restore the gaming state, according to the special process flag or the like in the stored RAM data or the start winning memory number data, If it is confirmed that the gaming machine is in a game standby state (not changing in design, not in big hit game, not in probable change, and no start winning memory), it is initial without performing game state recovery processing. The process may be executed.

  In the normal initialization process, as shown in FIG. 11, after a register and RAM clear process (step S2a) and a necessary initial value setting process (step S2b) are performed, a timer allocation is periodically performed every 2 ms. Initial setting of the timer register provided in the CPU 56 (setting that the time-out is 2 ms and the timer repeatedly operates) is performed so as to cause a delay (step S2c). That is, in step S2c, processing for activating a timer interrupt and processing for setting a timer interrupt interval are executed.

  Therefore, in this embodiment, the internal timer of the CPU 56 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 12, when a timer interrupt occurs, the CPU 56 sets a timer interrupt flag (step S11).

  When detecting that the timer interrupt flag is set in step S8, the CPU 56 resets the timer interrupt flag (step S9) and executes a game control process (step S10). With the above control, in this embodiment, the game control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the game control process is executed in the main process, but the game control process may be executed in the timer interrupt process.

  FIG. 13 is a flowchart showing the game control process of step S10. In the game control process, the CPU 56 first performs a process of setting a display control command sent to the display control board 80 in a predetermined area of the RAM 55 (display control data setting process: step S21), and then displays the display control command. An output process is performed (display control data output process: step S22).

  Next, a process of outputting the contents of the storage area for various output data to each output port is performed (data output process: step S23). Also, output data setting processing is performed for setting output data such as jackpot information, start information, probability variation information, etc., output to the hall management computer in the storage area (step S24). Further, various abnormality diagnosis processes are performed by the self-diagnosis function provided in the pachinko gaming machine 1, and an alarm is issued if necessary according to the result (error process: step S25).

  Next, a process of updating each counter indicating each determination random number such as a big hit determination random number used for game control is performed (step S26).

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S28). In the normal symbol process, the corresponding process is selected and executed in accordance with the normal symbol process flag for controlling the variable display 10 using the 7-segment LED in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 inputs the states of the gate sensor 12, the start port sensor 17, the count sensor 23, and the winning port switches 19a and 24a via the switch circuit 58, and determines whether or not there has been a winning for each winning port or winning device. (Switch processing: step S29). The CPU 56 further performs a process of updating a display random number such as a random number that determines the type of stop symbol (step S30).

  Further, the CPU 56 performs signal processing with the payout control board 37 (step S31). That is, when a predetermined condition is satisfied, a prize ball control command is output to the payout control board 37. The payout control CPU mounted on the payout control board 37 drives the ball payout device 97 according to the prize ball control command.

  As described above, the main process includes a process for determining whether or not to shift to the game control process, and the timer control process based on the timer interrupt periodically generated by the internal timer of the CPU 56 is used for the game control process. Since a flag for determining whether or not to shift is set, all the game control processes are executed reliably. In other words, until all the game control processes are executed, it is not determined whether or not to shift to the next game control process, so it is guaranteed that all the processes in the game control process are completed. ing.

  Conventional general game control processing is forcibly returned to the initial state by an external interrupt that occurs periodically. If it demonstrates in accordance with the example shown by FIG. 13, for example, even if it was during the process of step S31, it was forcibly returned to the process of step S21. In other words, there is a possibility that the next game control process will be started before all the processes in the game control process are completed.

  Here, the game control process executed by the CPU 56 of the main board 31 is executed according to the flag set in the timer interrupt process based on the timer interrupt that the internal timer of the CPU 56 periodically generates. A hardware circuit that generates a signal periodically (for example, every 2 ms) is provided, a signal from the circuit is introduced into an external interrupt terminal of the CPU 56, and it is determined whether or not to shift to a game control process by the interrupt signal. A flag may be set for this purpose.

  Even in such a configuration, the determination of the flag is not performed until all of the game control processes are executed, so that it is guaranteed that all the processes in the game control process are completed.

  FIG. 14 is a flowchart showing an example of a power failure occurrence NMI process executed in response to the NMI based on the voltage drop signal from the first power supply monitoring circuit of the power supply board 910. In the power failure occurrence NMI process, the CPU 56 first sets the interruption prohibition (step S41). In the power failure occurrence NMI processing, checksum generation processing is performed to ensure the storage of the RAM contents. If another interrupt process is performed during the process, the CPU may not be able to operate before the checksum generation process is completed. Settings are made so that no interruption occurs. Note that steps S43 to S49 in the power failure occurrence NMI process are an example of a process when power supply is stopped.

  Note that the processing in step S41 is not necessary when a CPU having a specification that does not cause other interrupts during the interrupt processing is used.

  Next, the CPU 56 checks whether or not the power-off flag has already been set (step S42). If the power-off flag is already set, the subsequent processing is not performed. If the power-off flag is not set, the following power supply stop process is executed. That is, the processing from step S43 to step S49 is executed.

  First, the contents of each register are stored in the backup RAM area (step S43). Further, an appropriate initial value is set in the backup check data area of the backup RAM area (step S44), the exclusive value is sequentially calculated for the initial value and the data in the backup RAM area (step S45), and the final calculation value is obtained. Is set in the backup parity data area (step S46). Thereafter, a power-off flag is set (step S47). Further, the RAM access is prohibited (step S48). When the power supply voltage is lowered, the level of various signal lines may become unstable and the contents of the RAM may be altered, but if the RAM access is prohibited in this manner, the data in the backup RAM will be altered. There is no. Then, all output ports are turned off (step S49).

  Next, the CPU 56 enters a loop process. That is, no processing is performed. Therefore, before the operation is prohibited from the outside by the reset signal from the reset IC 651 shown in FIG. Therefore, the CPU 56 reliably stops operation when the power is turned off. As a result, the RAM access prohibition control and the operation stop control described above can reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases. .

  In this embodiment, in the power failure occurrence NMI processing, the program is looped at the final part, but a halt (HALT) instruction may be issued.

  Further, as described above, the power-off flag that is set before the RAM access is prohibited is used when determining whether or not to recover from a power failure when the power is turned on. Further, the processing of steps S41 to S49 is completed before the second power supply monitoring unit generates the voltage drop signal. In other words, the detection voltages of the first voltage monitoring means and the second voltage monitoring means are set so that the second power supply monitoring means is completed before generating the voltage drop signal.

  In this embodiment, the power-off flag is confirmed at the start of the power supply stop process. When the power-off flag is already set, the power supply stop process is not executed. As described above, the power-off flag is a flag indicating that the power supply stop process has been completed. Therefore, for example, even if NMI occurs again for some reason in a loop waiting for reset, the power supply stop process is not repeatedly executed.

  However, if a CPU with specifications that do not cause other interrupts during interrupt processing is used, the determination in step S42 is not necessary.

  FIG. 15 is an explanatory diagram for explaining a backup parity data creation method. However, in the example shown in FIG. 15, the size of the data in the backup data RAM area is 3 bytes for simplicity. In the power failure generation process based on the power supply voltage drop, as shown in FIG. 15A, initial data (00H in this example) is set in the backup check data area. Next, an exclusive logical sum of “00H” and “F0H” is taken, and an exclusive logical sum of “16H” is obtained. Further, an exclusive OR of the result and “DFH” is taken. Then, the result (“39H” in this example) is set in the backup parity data area.

  When the power is turned on again, parity diagnosis is performed in the power failure recovery process. FIG. 15B is an explanatory diagram illustrating an example of parity diagnosis. If all the data in the backup area is stored as it is, the data as shown in FIG. 15A is set in the backup area when the power is turned on again.

  In the processing of step S51, the CPU 56 sequentially performs exclusive OR for each data in the backup data area using the data (in this example, “39H”) set in the backup parity data area in the backup RAM area as initial data. Process. If all the data in the backup area is stored as it is, the final calculation result matches “00H”, that is, the data set in the backup check data area. If a bit error has occurred in the data in the backup RAM area, the final calculation result is not “00H”.

  Therefore, the CPU 56 compares the final calculation result with the data set in the backup check data area, and if they match, the parity diagnosis is normal. If they do not match, the parity diagnosis is abnormal.

  As described above, in this embodiment, the game control means is provided with a storage means (a backup RAM in this example) that is backed up for a predetermined period even when the power of the gaming machine is cut off. The CPU 56 (specifically, a program executed by the CPU 56) is configured to perform a game state recovery process (step S5) for recovering the game state based on the backup data if the storage means is in the backup state.

  In this embodiment, the first power supply monitoring means is mounted on the power supply board 910 as shown in FIG. 9, and the second power supply monitoring means is mounted on the main board 31 as shown in FIG. Yes. When the power supply voltage decreases, the second power supply monitoring means (in this example, the reset IC 651) generates the voltage drop signal (system reset signal) in the first power supply monitoring means (in this example). The power monitoring IC 902) is set to be later than the time when the voltage drop signal is generated.

  Then, the CPU 56 enters the loop state after executing the power failure generation processing (processing when the power supply is stopped) based on the voltage drop signal from the first power monitoring means (power monitoring IC 902). Will enter the reset state. That is, the operation of the CPU 56 is completely stopped. In the loop state, the + 5V power supply voltage value gradually decreases and the input / output state becomes indefinite. However, since the CPU 56 is in the reset state, the abnormal operation based on the indefinite data is prevented.

  Thus, in this embodiment, the CPU 56 enters the loop state in response to the detection output input from the first power supply monitoring means, and the system in response to the detection output input from the second power supply monitoring means. Since it is configured to be reset, it is possible to reliably store data when the power is turned off, and to prevent a disadvantage from being brought to the player.

  In this embodiment, the first power supply monitoring circuit and the second power supply monitoring circuit monitor the same power supply voltage, but different power supply voltages may be monitored. For example, the first power supply monitoring circuit on the power supply board 910 may monitor the + 30V power supply voltage, and the second power supply monitoring circuit on the main board 31 may monitor the + 5V power supply voltage. The second power supply of the main board 31 is delayed so that the timing at which the second power supply monitoring circuit generates the low-level voltage drop signal is later than the timing at which the first power supply monitor circuit generates the voltage drop signal. A threshold level (voltage level for generating a voltage drop signal) of the monitoring circuit is set. For example, the threshold is 4.25V. 4.25 V is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while.

  In the above embodiment, the CPU 56 detects the first voltage drop signal from the power supply board (voltage drop signal from the first power supply monitoring means) via the non-maskable interrupt terminal (NMI terminal). However, the first voltage drop signal may be introduced to the maskable interrupt terminal (IRQ terminal). In that case, a power supply stop process is executed in the interrupt process (IRQ process).

  FIG. 16 is a flowchart showing a portion related to prize ball control in the switch process (step S29) in the game control process shown in FIG. In the switch process, the CPU 56 sets a ball break flag when the ball break switch 187 detects a ball break (steps S121 and S122). Further, when it is detected by the ball cut switch 187 that the ball is not cut, the ball cut flag is reset (steps S121 and S123).

  Next, when the lower pan full tank is detected by the full tank switch 48, a full tank flag is set (steps S124 and S125). Further, when it is detected by the full tank switch 48 that the lower pan is not full, the full tank flag is reset (steps S124 and S126).

  Further, when it is detected that the count switch 23 is turned on, the big prize counter is incremented by 1 (steps S131 and S132), and when it is detected that any of the prize mouth switches 19a and 24a is turned on, the counter for the normal prize mouth is displayed. Is incremented by 1 (steps S133 and S134), and when it is detected that the start port switch 17 is turned on, the start winning port counter is incremented by 1 (steps S135 and S136).

  Note that the large winning opening counter, the normal winning opening counter, and the starting winning opening counter are counters for counting the number of winning combinations at each winning opening.

  FIG. 17 is an explanatory diagram showing an example of a bit configuration of a prize ball control command transmitted from the main board 31 to the payout control board 37. As shown in FIG. 17, the upper 4 bits in one byte are used as a control designating unit, and the lower 4 bits are used as an area indicating the number of prize balls.

  As shown in FIG. 18, if bits 7, 6, 5, and 4 are “0, 1, 0, 0” in the control designation unit, this indicates a payout number designation command, and “0, 1, 0, “1” indicates a payout designation command. The payout number designation command is sent to the payout control board 37 as soon as the CPU 56 of the main board 31 detects a winning.

  The payout stop designation command in which bits 7, 6, 5, and 4 are “1, 0, 0, 0” is detected when the supply ball is exhausted or when the surplus ball receiving tray 4 is full. Sometimes transmitted from the main board 31. Also, the payout stop cancellation designation command in which the bits 7, 6, 5, 4 are “1, 0, 1, 0” is when the supply ball is present and the surplus ball receiving tray 4 is full. To the main board 31.

  As shown in FIG. 7, the prize ball control command is transmitted via the output port 577. In this embodiment, as shown in FIG. 19, when the prize ball control commands D7 to D0 are output from the main board 31, the prize ball control INT signal becomes low level for 5 μs or more. The prize ball control INT signal is connected to the interrupt terminal of the payout control CPU 371 on the payout control board 37. Therefore, when there is an interruption, the payout control CPU 371 can recognize that the prize ball control commands D7 to D0 are sent from the main board 31, and perform the prize ball control command reception process in the interruption process.

  Note that the command configuration shown in FIG. 17 is an example, and other configurations may be used. For example, the upper and lower order in one byte may be reversed from the configuration shown in FIG. The length of the command is also an example, and may be a 2-byte configuration, for example.

  20 and 21 are flowcharts showing an example of the winning ball signal process (step S31) in the game control process shown in FIG. In this example, in the winning ball signal processing, first, it is confirmed whether or not the payout is stopped (step S201). The payout stop state is a state after a payout stop instruction command is sent to the payout control board 37. If it is not in the payout stop state, it is confirmed whether or not the above-described ball-out state flag or full tank flag is turned on (step S202).

  When either of them changes to the on state, a prize ball control command indicating a payout stop instruction is output to the output port 577 (see FIG. 7) (step S203), and the INT signal is turned on (step S204). Further, after a delay time of 5 μs (step S205), the INT signal is turned off (step S206). As a result, a prize ball control command indicating a payout stop instruction is sent to the payout control board 37 at the timing shown in FIG. In step S202, when one of the flags is already in the on state and the other flag is in the on state, the control for sending out the prize ball control command indicating the payout stop instruction (steps S204 to S206) is performed. Not done.

  If it is in the payout stop state, it is checked whether both the ball-out state flag and the full tank flag are turned off (step S211). When both are turned on, a prize ball control command indicating a payout stop cancellation instruction is output to the output port 577 (step S212), and the INT signal is turned on (step S213). Further, after a delay time of 5 μs (step S214), the INT signal is turned off (step S215).

  Next, the CPU 56 performs control to send out the number of prize balls according to winning a prize to the payout control board 37. In this embodiment, 15 winning balls are paid out for winning through the big winning opening, 6 winning balls are paid out for winning through the starting winning opening 14, and the other winning openings 24 and winning ball apparatus are passed through. Assume that 10 winning balls are paid out for winning.

  First, the CPU 56 checks the value of the winning prize counter (step S361). As described above, the winning prize counter is counted up when the game ball wins the winning prize and the count switch 23 is turned on. If the value of the big prize winning counter is not 0, a prize ball control command indicating 15 payout number instructions is output to the output port 577 (step S362), and the INT signal is turned on (step S363). Further, after a delay time of 5 μs (step S364), the INT signal is turned off (step S365). Then, the value of the winning prize counter is decremented by -1 (step S366), and 15 is added to the accumulated payout command number (step S367).

  If the value of the big prize counter is 0, the value of the normal prize counter is checked (step S371). As described above, the counter for the normal winning opening is counted up when the game ball wins the winning opening and the winning opening switches 19a and 24a are turned on. When the value of the counter for the normal winning opening is not 0, 10 winning ball control commands indicating the payout number instructions are output to the output port 577 (step S372), and the INT signal is turned on (step S373). Further, after a delay time of 5 μs (step S374), the INT signal is turned off (step S375). Then, the value of the counter for the normal winning a prize mouth is decremented by 1 (step S376), and 10 is added to the cumulative value of the payout command number (step S377).

  If the value of the normal winning port counter is 0, the value of the starting winning port counter is checked (step S381). As described above, the start winning port counter is counted up when the game ball wins the start winning port and the start port switch 17 is turned on. If the value of the start winning opening counter is not 0, 6 winning ball control commands indicating the payout number instructions are output to the output port 577 (step S382), and the INT signal is turned on (step S383). Further, after a delay time of 5 μs (step S384), the INT signal is turned off (step S385). Then, the value of the counter for the normal winning a prize mouth is decremented by -1 (step S386), and 6 is added to the cumulative value of the payout command number (step S387).

  As described above, the prize control command is sent only once from the game control means to the payout control board 37 so that the payout control means can receive the game.

  When determining the number of winning balls, that is, when determining the number of payouts (steps S362, S372, and S382), 15, 10, or 6 may be described in the program executed by the CPU 56. In the embodiment, each number is described in the data area of the ROM 54. Then, when determining the number of prize balls, the data area in the ROM 54 is referred to. FIG. 22 shows an example of a memory map. In this example, the ROM area is allocated to addresses E000 (H) to FFFF (H). In the ROM area, a data area not including a program is allocated to E200 (H) to EDFF (H), and the program area is EE00 ( H) to F7FF (H).

  In the data area, “15”, “6”, and “10” indicating the number of prize balls are set. “AA” is a label of an address for which “15” is set.

  FIG. 23 shows a specific program example when determining the number of winning balls “15”. FIG. 23A shows an example in which the number is described in the program, and FIG. 23B shows an example used in this embodiment. In the example shown in FIG. 23A, the immediate value “15” is loaded into the accumulator, and then the contents of the accumulator are set in the area specified by the label DATA. The area specified by the label DATA is, for example, the output port 577 in steps S362, S372, and S382.

  According to the program configuration shown in FIG. 23A, “15” indicating the number of prize balls is written in the program area. When changing the number of prize balls, it is necessary to rewrite the contents of the program area. The configuration shown in FIG. 23 (A) is a relatively simple example, and errors are unlikely to occur when changing a program. However, when the program structure is complicated in order to save program capacity, the number of prize balls When changing, changes that adversely affect other parts may be made.

  In the example shown in FIG. 23B, the contents of the data area specified by the label SS are loaded into the accumulator, and then the contents of the accumulator are set in the area specified by the label DATA. According to such a program configuration, when changing the number of winning balls, it is only necessary to change the numerical value set in the data area corresponding to the label SS, and it is not necessary to change the contents of the program area. For example, when the number of 15 winning balls is changed to 14, only the numerical value set in the data area corresponding to the label SS needs to be changed to 14.

  If the configuration is such that the value set in the data area is referenced when determining the number of winning balls in this way, the basic game content will not change, but the number of winning balls to be paid out will differ according to the winnings. When developing a gaming machine, there is no room for errors due to program changes. That is, the program can be changed more safely.

  Further, an addition value for adding the payout amount cumulative value in steps S367, S377, and S387 is also determined with reference to the data area.

  In this embodiment, the number of prize balls is notified to the payout control board 37 in order from the largest number of prize balls for winning regardless of the order of winning, but the number of prize balls is notified in order of winning. It may be.

  Next, payout control by the payout control CPU 371 will be described. FIG. 24 is a block diagram showing a configuration example around the payout control CPU 371 for power supply monitoring and power supply backup. As shown in FIG. 24, the voltage drop signal from the first power supply monitoring circuit (first power supply monitoring means) is connected to the non-maskable interrupt terminal (NMI terminal) of the payout control CPU 371 via the buffer circuit 960. Has been. The first power supply monitoring circuit is a circuit that monitors the voltage of any one of the various DC power supplies used by the gaming machine and detects a power supply voltage drop. In this embodiment, the power supply voltage of VSL is monitored, and a low level voltage drop signal is generated when the voltage value falls below a predetermined value. VSL is the largest DC voltage used in gaming machines, and is + 30V in this example. Therefore, the payout control CPU 371 can confirm the occurrence of power interruption by the interrupt process.

  Although the initial reset circuit 975 is also mounted on the payout control board 37, in this embodiment, the initial reset circuit 975 also serves as a second power supply monitoring circuit (second power supply monitoring means). That is, when the power is turned on, the reset IC 976 sets the output to the low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to the high level when the predetermined time elapses. In addition, the reset IC 976 monitors the power supply voltage of VSL, which is the power supply voltage equal to the power supply voltage monitored by the first power supply monitoring circuit mounted on the power supply board 910, and the voltage value falls below a predetermined value (for example, + 9V). Then, a low level voltage drop signal is generated. Therefore, when the power is turned off, the payout control CPU 371 is system-reset by the voltage drop signal from the reset IC 976 becoming low level. As shown in FIG. 24, the voltage drop signal is the same output signal as the reset signal.

  The predetermined value for the reset IC 976 to detect power-off is lower than the normal voltage, but is a voltage that allows the payout control CPU 371 to operate for a while. Further, since the reset IC 976 is configured to monitor a voltage higher than the voltage required by the payout control CPU 371 (in this example, +5 V), the monitoring range for the voltage required by the payout control CPU 371 is set. Can be spread. Therefore, more precise monitoring can be performed.

  While power is not supplied from the + 5V power supply, at least a part of the built-in RAM of the payout control CPU 371 is backed up by connecting the backup power supplied from the power supply board to the backup terminal, and the power to the gaming machine is cut off. The contents are saved. When the +5 V power supply is restored, a reset signal is issued from the initial reset circuit 975, so that the payout control CPU 371 returns to a normal operation state. At that time, since necessary data is backed up, it is possible to return to the gaming state at the time of the power failure when recovering from the power failure.

  As described above, in this embodiment, the first power supply monitoring circuit mounted on the power supply board 910 monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, and When the voltage of the power source falls below a predetermined value, a voltage drop signal (power failure detection signal) is generated. At the timing when the power-off detection signal is output, the IC drive voltage is still a voltage value that can sufficiently drive various circuit elements. Therefore, an operation time is secured for the payout control CPU 371 of the payout control board 37 that operates at the IC drive voltage to perform a predetermined power supply stop process.

  Also in this case, the first power supply monitoring circuit monitors the voltage of the highest power supply VSL among the DC voltages used in the gaming machine, but the timing of generating the power supply interruption detection signal is the IC drive. The monitoring target voltage may not be the voltage of the highest power supply VSL as long as the operation time required for the electric component control means operating at the voltage to perform the predetermined power supply stop process is ensured. That is, if at least a voltage higher than the IC drive voltage is monitored, the power-off detection signal may be generated at such a timing that the operation time for the electric component control means to perform the predetermined power supply stop process is ensured. it can.

  In this case, as described above, since the voltage supplied to various switches of the gaming machine such as the prize ball count switch 301A is + 12V, the monitoring target voltage can be expected to prevent erroneous switch-on detection when the power is turned off. A voltage is preferred. That is, it is preferable that the voltage drop can be detected before the +12 V power supply voltage, which is the voltage supplied to the switch (switch voltage) starts to drop. Therefore, it is preferable to monitor a voltage higher than at least the switch voltage.

  In the configuration shown in FIG. 24, the initial reset circuit 975 outputs a low level during a period determined by the capacitance of the capacitor when power is turned on, and then outputs a high level. That is, the reset release timing is only once. However, as in the case of the main board 31 shown in FIG. 8, a circuit configuration in which a plurality of reset release timings may be used may be used.

  FIG. 25 is a flowchart showing main processing of the payout control CPU 371. In the main process, the payout control CPU 371 first performs an initial value setting process such as clearing the RAM area (step S701). When data is set in the RAM area (backup RAM area) backed up by the power supply of the built-in RAM, the clearing process of those areas is not performed. Thereafter, in this embodiment, the payout control CPU 371 shifts to a loop process for checking the timer interrupt flag (step S702).

  In the initialization process in step S701, the non-backup RAM area is cleared if the values of the total number storage and the lending ball number storage described later are not 0. Then, settings for restarting the prize ball are made. For example, an in-price ball processing flag is set. Even if it is a backup RAM area, if it is an area not related to the number of winning balls, it may be cleared by designating those addresses. In addition to these processes, initial setting of a timer register provided in the payout control CPU 371 so that a timer interrupt is periodically generated every 2 ms (timeout is 2 ms and setting for repeated timer operation) Is done. That is, processing for activating a timer interrupt and processing for setting a timer interrupt interval are executed.

  Therefore, in this embodiment, the internal timer of the payout control CPU 371 is set to repeatedly generate a timer interrupt. In this embodiment, the repetition period is set to 2 ms. Then, as shown in FIG. 26, when a timer interrupt occurs, the payout control CPU 371 sets a timer interrupt flag (step S711).

  When detecting that the timer interrupt flag is set in step S702, the payout control CPU 371 resets the timer interrupt flag (step S703) and executes a payout control process (step S705). With the above control, in this embodiment, the payout control process is started every 2 ms. In this embodiment, only the flag is set in the timer interrupt process, and the payout control process is executed in the main process, but the payout control process may be executed in the timer interrupt process.

  FIG. 27 is an explanatory diagram showing a usage example of the RAM built in the payout control CPU 371. In this example, a total number storage (for example, 2 bytes) and a rental ball number storage are formed in the backup RAM area. The total number storage stores the total number of payouts instructed from the main board 31 side. The rental ball number storage stores the number of balls that have not been paid out. The backup RAM area also has an area for setting various flags. In FIG. 27, a non-backup area is also shown, but all the RAMs built in the payout control CPU 371 may be backed up by power.

  FIG. 28 is a flowchart showing a prize ball control command reception process by an interrupt process. The prize ball control INT signal from the main board 31 is input to the interrupt terminal of the payout control CPU 371. Therefore, when the prize ball control INT signal from the main board 31 is turned on, the payout control CPU 371 is interrupted, and the prize ball control command reception process shown in FIG. 28 is started.

  In the prize ball control command reception process, the payout control CPU 371 first reads 1-byte data from the input port assigned to the prize ball control command data input (step S852). If the read data is a payout number instruction command (step S853), the number specified by the payout number instruction command is added to the total number memory (step S855). Otherwise, a communication end flag is set (step S854). In this example, the communication end flag is a flag indicating that a command other than the payout number instruction command has been received.

  As described above, the payout control CPU 371 mounted on the payout control board 37 stores the number of prize balls included in the payout quantity instruction command sent from the CPU 56 of the main board 31 in the backup RAM area (total number memory). .

  29 to 32 are flowcharts illustrating an example of the payout control process (step S705). In this example, the payout control CPU 371 first checks whether or not payout is stopped (step S471). If the payout is not stopped, it is confirmed whether or not a prize ball control command indicating a payout stop instruction is received from the main board 31 (step S472). If it has been received, the payout motor 289 is stopped (step S473), and the internal state is set to the payout stop state (step S474). That is, the payout control means is in a state where both the award ball payout and the ball lending are stopped.

  In this embodiment, the payout motor 289 is stopped as soon as a payout stop instruction command is received. However, the payout motor 289 may be stopped at a place where the cut is good instead of being controlled as such. For example, the game balls may be paid out in units of 25, and when the payout of one unit is completed, the payout motor 289 may be stopped and the internal state may be set to the payout stop state. As described above, the ball break switches 187a and 187b are installed at positions where it is possible to detect the presence of about 27 to 28 game balls in the payout ball passages 186a and 186b. Even if the control means detects a broken ball, at least 25 payouts are possible from that point. Accordingly, there is no problem even if the payout is stopped when one unit of payout is completed. Further, if the payout is stopped in units of one unit, control at the time of restarting payout becomes easy.

  If it is in the payout stop state, the payout control CPU 371 checks whether or not a prize ball control command indicating a payout stop cancellation instruction has been received from the main board 31 (step S475). If not received, the process returns to step S471. If a prize ball control command indicating a payout stop cancellation instruction has been received, the internal payout stop state is canceled (step S476). That is, the payout control means returns to a state where the prize ball can be paid out and lent out.

  If it is not in the payout stop state, the payout control CPU 371 performs the processing after step S481. In step S481, the payout control CPU 371 checks whether or not the ball is currently being lent. If the ball is being lent, the process proceeds to the process of renting the ball in step S532. If the ball is not being lent, it is confirmed whether or not the prize ball is being processed (step S482). If the prize ball process is in progress, the process proceeds to the process during the prize ball process in step S513.

  If the winning ball processing is not in progress, it is confirmed whether or not the BRQ signal, which is a ball lending request signal from the card unit 50 as an external device of the gaming machine, is turned on (step S483). If the BRQ signal is on, the processing from step S491 is performed. If the BRQ signal is not turned on, that is, if a ball lending request is not generated, it is confirmed whether or not the total number storage is 0 (step S491). If the total number storage is 0, that is, if it is not necessary to start paying out a prize ball, the process is terminated.

  In this embodiment, the ball lending is prioritized over the winning ball processing according to the determinations in steps S481 to S491, but the winning ball processing may be prioritized over the ball lending.

  In step S492, the payout control CPU 371 turns on the ball lending process flag, sets the unit number in the ball lending number counter (step S493), and turns on the EXS signal (step S494). The number of units is, for example, the number (for example, 25) of game balls lent out at a predetermined unit of 100 yen. And then. In order to set the ball distribution member 311 below the ball dispensing device 97 to the ball lending side, the distribution solenoid 310 is driven (step S495). Also, the payout motor 289 is turned on (step S496), and the process proceeds to the ball lending process shown in FIG.

  Strictly speaking, the payout motor 289 is turned on after the BRQ signal is turned off to indicate that the card unit 50 has recognized acceptance. The ball lending number counter is formed in a lending ball number storage in the backup RAM area. A ball lending process flag is also set in the backup RAM area.

  If the total number storage is not 0 in step S491, a process for starting a prize ball payout is performed. That is, the award ball processing flag is turned on (step S505), the ball sorting member 311 below the ball payout device 97 is set to the prize ball side (step S506), and the payout motor 289 is turned on (step S507). Then, the process shifts to a process for paying out a prize ball. The prize ball processing flag is set in the backup RAM area.

  The process after step S513 is a process during payout of a prize ball. In the process of paying out a prize ball, the payout control CPU 371 checks whether or not a game ball has been paid out based on the detection output of the prize ball count switch 301A. When it is confirmed that one payout has been made (step S513), the total number storage value is decremented by 1 (step S514). Further, when the value of the total number storage becomes 0 (step S515), the payout motor 289 is turned off (step S516), and the prize ball processing flag is turned off (step S517).

  The contents of the total number storage are saved by the backup power source of the power supply board 910 for a predetermined period even if the gaming machine is turned off. Therefore, when the power is restored during the predetermined period, the payout control CPU 371 can continue the prize ball payout process based on the contents of the total number storage.

  When the power is turned on, the payout control CPU 371 can determine whether to perform normal initial setting processing or restore the state in the winning ball simply by checking the data in the backup RAM area. In other words, it is possible to resume the prize ball processing for the unpaid prize balls by simple determination.

  The payout control CPU 371 manages the number of prize balls instructed from the main board 31 as the total number in the total number memory, but may manage each prize ball number (for example, 15, 10, or 6). . For example, a number counter corresponding to the number of winning balls is provided, and when a payout number designation command is received, the number counter corresponding to the number designated by the command is incremented by one. When the prize ball payout for each prize ball number is completed, the corresponding number counter is decremented by one. Also in that case, each number counter is formed in the backup RAM area. Therefore, even if the power of the gaming machine is cut off, if the power recovers during a predetermined period, the payout control CPU 371 can continue the prize ball payout process based on the contents of each number counter.

  FIG. 32 is a flowchart showing a ball lending process in the payout control process by the payout control CPU 371. In the ball lending process, the payout control CPU 371 checks whether or not a game ball has been paid out based on the detection output of the ball lending count switch 301B. When it is confirmed that one payout has been made (step S532), the value of the ball lending number counter is decremented by 1 (step S533). When the value of the ball lending counter is 0 (step S534), the EXS signal is turned off to indicate to the card unit 50 that the next ball lending request can be accepted (step S534). S535). Further, the payout motor 289 is turned off (step S535), and the ball lending process flag is turned off (step S537).

  After turning off the EXS signal indicating acceptance of a ball lending request, if the BRQ signal, which is a ball lending request signal, is turned on again within a predetermined period, the ball lending process is continued without turning off the payout motor. Also good. That is, instead of performing the ball lending process for each predetermined unit (100 yen unit in this example), the ball lending process may be executed continuously.

  The contents of the number of lent balls are stored by the backup power source of the power supply board 910 for a predetermined period even if the gaming machine is turned off. Accordingly, when the power is restored during the predetermined period, the payout control CPU 371 can continue the ball lending process based on the contents of the lending ball number storage.

  FIG. 33 is a flowchart showing a power failure occurrence interrupt process executed by the payout control CPU 371 in response to an interrupt from the first power supply monitoring unit. When the power monitoring IC 902 on the power supply board 910 detects a drop in the power supply voltage, the voltage drop signal indicates a voltage drop, and the power failure occurrence interrupt process is started. In the power failure occurrence interrupt process, the payout control CPU 371 sets the interrupt prohibition (step S801), sets the RAM access prohibited state (step S802), turns off the output port (step S803), and performs loop processing. to go into. That is, no processing is performed.

  Therefore, before the operation is prohibited (system reset) from the outside by the reset signal from the reset IC 976 shown in FIG. Therefore, the payout control CPU 371 reliably stops operation when the power is turned off. As a result, it is possible to reliably prevent the RAM contents from being destroyed due to an abnormal operation that may occur as the power supply voltage decreases.

  In this embodiment, in the power failure occurrence interrupt process, the program is looped at the final part, but a halt (HALT) instruction may be issued. Further, when a CPU having a specification that does not cause other interrupts during the interrupt process is used, the process of step S801 is not necessary. Further, in this embodiment, the power failure occurrence interrupt process (power supply stop process) is executed according to the NMI, but the first voltage drop signal from the power supply board (the voltage from the first power supply monitoring means). A reduction signal) may be introduced into the maskable interrupt terminal (IRQ terminal) and the power supply stop process may be executed by the interrupt process (IRQ process).

  FIG. 34 is a flowchart showing a part of the initialization process (step S701) executed by the payout control CPU 371 when the power is turned on. When the power is turned on or the power is restored, the payout control CPU 371 first checks whether the value of the total number storage or the number of rented balls stored in the backup RAM area is not 0 (step S901). . If it is 0, it means that there was no unpaid prize ball at the time of the previous power-off, so normal initial setting processing is performed. That is, the register and the entire RAM area are cleared (step S903), and the stack pointer is initialized (step S904).

  If the value of the total number storage or the lending ball number storage is not 0, an address is designated and the register and the non-backup RAM area are cleared (step S905). Then, a setting for resuming a prize ball or ball lending is performed. For example, a ball lending process flag is set (step S906). Even if it is a backup RAM area, if it is an area not related to the number of winning balls, it may be cleared by designating those addresses.

  As described above, the payout control CPU 371 can determine whether to perform normal initial setting processing or to restore the state in which a prize ball is being paid out or being lent out by simply checking the data in the backup RAM area when the power is turned on. That is, since the number of unpaid game balls and the winning ball processing flag and the ball lending processing flag are stored in the backup RAM, the payout control CPU 371 sets the award ball processing flag or the ball lending processing flag. If so, the processing corresponding to the contents of the total number storage or the rental ball number storage can be continued. That is, processing can be resumed for unpaid prize balls or unpaid lending balls by simple determination.

  In the above embodiment, the information related to the ball lending stored in the lending ball number storage in the backup RAM area is the value of the ball lending number counter. That is, the number of unpaid game balls in one predetermined unit (in this example, the number of units corresponding to 100 yen: 25). However, the number of unpaid lending balls for all of the predetermined units may be stored in the lending ball number storage. In this case, for example, information indicating that the payout control CPU 371 should accept all the lending requests for 500 yen, that is, the lending requests for 5 times in a predetermined unit, and perform lending for 5 times in a predetermined unit. Is stored in the rental ball number storage in the backup RAM area.

  With such control, when a ball lending request is continuously output from the card unit 50 a predetermined number of times, all requests are sequentially accepted. Then, those that have been accepted but have not yet started to be paid out are saved in the value of the ball lending counter.

  Since the value of the ball lending number counter and the ball lending number counter are stored in the lending ball number storage in the backup RAM area, they are stored for a predetermined period even when the power to the gaming machine is cut off. If the power supply is restored within the predetermined period, the payout control CPU 371 can continue the ball lending process based on the stored values of the ball lending number counter and the ball lending number counter. In other words, even when the payout control means is configured to accept all ball lending requests multiple times and then sequentially execute the ball lending process, the player may be disadvantaged with respect to ball lending. No control is realized.

  In addition, it may be configured so that the actual ball lending process is started at the same time as the acceptance of a plurality of ball lending requests is started. The ball lending process may be started.

  In the above embodiment, the RAM access is simply prohibited as the power supply stop process when a power interruption such as a power failure occurs, but the parity data is created for the data in the RAM, The created parity data may also be saved. Then, at the time of power-on processing, confirmation based on the parity data is performed, and if it is confirmed that the data in the RAM is correctly stored, the winning ball payout processing or ball lending processing based on the stored data is continued. You may do it.

  As described above, in this embodiment, even when a shortage of game balls to be paid out is detected (when a ball is out of service), the same command is used when the game ball should not be paid out when the lower plate is full. The payout stop command is notified from the game control means to the payout control means (see FIG. 20). Then, the payout control means stops the prize ball payout according to the payout stop instruction. That is, even if the conditions for stopping the prize ball are different, a common command is sent from the game control means to the payout control means. Therefore, a load related to information transmission from the game control means to the payout control means is reduced. As a result, there is an advantage that the program capacity in the game control means is reduced and the program capacity that can be used for game control is increased.

  In addition, the game control means notifies the payout control means of a payout stop release command, which is the same command for releasing the ball breakage and for solving the lower pan full. Then, the payout control means returns to a state in which the prize ball can be paid out according to the payout stop instruction. That is, even if the cause of the award ball stop cancellation is different, a common command is sent from the game control means to the payout control means. As a result, the load related to information transmission from the game control means to the payout control means is also reduced.

  Further, the payout control means stops the ball lending according to the payout stop instruction. That is, a common command is sent from the game control means to the payout control means even if the conditions for stopping lending are different. Therefore, a load related to information transmission from the game control means to the payout control means is reduced. As a result, there is an advantage that the program capacity in the game control means is reduced and the program capacity that can be used for game control is increased.

  Then, the payout control means returns the ball lending to a possible state according to the payout stop instruction. That is, even if the causes of the ball lending stop cancellation are different, a common command is sent from the game control means to the payout control means. As a result, the load related to information transmission from the game control means to the payout control means is also reduced.

  In the above embodiment, when the payout control means receives the payout stop command, both the ball lending and the prize ball payout are stopped, and both the ball lending and the prize ball payout are possible according to the payout stop cancellation instruction. However, the payout stop instruction for the winning ball and the payout stop instruction for the ball lending may be separate commands, and the payout stop canceling instruction for the prize ball and the payout stop canceling instruction regarding the ball lending may be separate commands. Even in such a case, a common command is sent from the game control means to the payout control means even if the conditions for stopping and releasing the winning ball are different, and common even if the conditions for stopping and releasing the ball rental are different. This command can be sent from the game control means to the payout control means.

  However, when the payout control means receives a payout stop instruction command, both the ball lending and prize ball payout are stopped, and when a payout stop release instruction command is received, both the ball lending and prize ball payout are enabled. That is, with one command, ball lending and prize ball payout are stopped, and if the stop state is canceled, the payout control from the game control means is performed as compared with the case of using the stop instruction command and the stop release instruction command for each. The load related to information transmission to the means is further reduced.

  In the above embodiment, the payout means is configured to be able to lend a ball and a prize ball. However, the present invention is applied even if a mechanism for lending a ball and a mechanism for paying a prize ball are independent. be able to. In that case, even if the mechanism that lends the ball and the mechanism that pays out the prize ball are independent, if the payout control means is configured to control both mechanisms, 1 as in the above embodiment. It is more effective to configure the ball lending and the winning ball payout to be instructed to stop / release with one command.

  In the game control means, when determining the number of winning balls according to the winning, the number is not directly described in the program, and the number of winning balls is determined by referring to the data area. Therefore, data can be easily changed even when developing models with different numbers of winning balls according to winning. In the above embodiment, the first type pachinko gaming machine is taken as an example of the gaming machine, but the present invention is also applicable to other types of pachinko gaming machines and other gaming machines such as slot machines. For example, in a slot machine, if the number of medals to be paid out as a prize ball is described in the data area, it is easy to change data even when developing a model with a different number of prize balls.

It is the front view which looked at the pachinko game machine from the front. It is a whole rear view which shows the internal structure of a pachinko gaming machine. It is the rear view which looked at the mechanism board of the pachinko game machine from the back. It is a front view which shows the structure around the intermediate | middle base unit installed in the mechanism board. It is a disassembled perspective view which shows a ball dispensing apparatus. It is a block diagram which shows the circuit structure of a game control board (main board). It is a block diagram which shows the component relevant to prize balls, such as a component of a payout control board and a ball payout apparatus. It is a block diagram which shows one structural example of CPU periphery for a power supply monitoring and a power supply backup. It is a block diagram which shows one structural example of a power supply board. It is a flowchart which shows the main process which CPU in a main board | substrate performs. It is a flowchart which shows the initialization process. It is a flowchart which shows a 2 ms timer interruption process. It is a flowchart which shows a game control process. It is a flowchart which shows a power failure generation | occurrence | production NMI process. It is explanatory drawing for demonstrating the backup parity data creation method. It is a flowchart which shows the switch process in a game control process. It is explanatory drawing which shows the structural example of a prize ball control command. It is explanatory drawing which shows the bit structure of a prize ball control command. FIG. 10 is a timing chart showing a state of outputting prize ball control command data. It is a flowchart which shows the winning ball signal process in a game control process. It is a flowchart which shows the winning ball signal process in a game control process. It is explanatory drawing which shows the example of a memory map. It is explanatory drawing which shows the example of a specific program when determining the number of prize balls. It is a block diagram which shows the example of 1 structure around the payout control CPU for power supply monitoring and power supply backup. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows 2ms timer interruption processing of CPU for payout control. It is explanatory drawing which shows the example of 1 structure of RAM in the payout control means. It is a flowchart which shows the command reception process which CPU for payout control performs. It is a flowchart which shows payout control processing. It is a flowchart which shows payout control processing. It is a flowchart which shows payout control processing. It is a flowchart which shows payout control processing. It is a flowchart which shows the power failure generation | occurrence | production interruption process which CPU for payout control performs. It is a flowchart which shows an example of the initialization process of CPU for payout control.

Explanation of symbols

31 Game control board (main board)
37 Dispensing control board 53 Basic circuit 56 CPU
97 ball payout device 301A prize ball count switch 301B ball lending count switch 371 payout control CPU

Claims (1)

A gaming machine capable of giving a game result value to a player as a result of performing a predetermined game ,
It is possible to perform gaming state return control for returning the gaming state based on the stored contents held in the storage means capable of holding the contents immediately before the power supply is stopped when the power is supplied. Is possible,
Game control means for controlling the progress of the game;
Game medium detecting means for detecting a game medium;
Power supply monitoring means for monitoring a power supply voltage higher than the voltage supplied to the game medium detection means, and outputting a voltage drop signal to the game control means when the power supply voltage has become a predetermined value or less ,
The game control means includes a game control microcomputer,
The voltage drop signal from the power monitoring means is input to an interrupt terminal of the game control microcomputer,
The game control microcomputer is:
Execute predetermined power-off processing based on the interrupt according to the voltage drop signal from the power monitoring means, and can start the interrupt processing if an interrupt occurs even after the power-off processing is executed And
A gaming machine characterized in that even if an interrupt occurs again after the power-off process is executed and the interrupt process is activated, the power-off process is not executed .

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