JP4379578B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP4379578B2
JP4379578B2 JP2003331001A JP2003331001A JP4379578B2 JP 4379578 B2 JP4379578 B2 JP 4379578B2 JP 2003331001 A JP2003331001 A JP 2003331001A JP 2003331001 A JP2003331001 A JP 2003331001A JP 4379578 B2 JP4379578 B2 JP 4379578B2
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semiconductor device
package
interposer
manufacturing
semiconductor chip
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JP2005101130A (en
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英男 宮坂
将巳 内田
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Seiko Epson Corp
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
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    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a non-defective semiconductor chip from becoming useless. <P>SOLUTION: A semiconductor device has a first package 10, a second package 20 put on the first package 10, and a plurality of junctions 40 bonding the first and second packages 10 and 20 to each other. A sealed section is provided to overlap the plurality of junctions 40. The junctions 40 have contact sections 42 which electrically connect first and second wiring patterns to each other. In addition, the junctions 40 have reinforcing sections 44 which are either one of non-contact sections which do not electrically connect the first and second wiring patterns to each other and redundance contacts which electrically connect the portions electrically connected by means of the contacts 42. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

本発明は、半導体装置及びその製造方法、回路基板並びに電子機器に関する。   The present invention relates to a semiconductor device, a manufacturing method thereof, a circuit board, and an electronic device.

半導体チップの特性検査は、そのままでは行うことが難しい場合があり、多くの場合、インターポーザに搭載してから行っていた。積み重ねられた複数の半導体チップを有するスタックドタイプの半導体装置の製造プロセスでは、全ての半導体チップを積み重ねた後に、それぞれの半導体チップの特性検査を行っていた。したがって、１つでも不良品の半導体チップが見つかると、半導体装置全体が不良品となる。その結果、他の半導体チップが良品であったとしても、これらを廃棄することになり、良品の半導体チップを無駄にしていた。
特開平６−１３５４１号公報 The characteristic inspection of a semiconductor chip may be difficult to perform as it is, and in many cases, it is performed after being mounted on an interposer. In a manufacturing process of a stacked type semiconductor device having a plurality of stacked semiconductor chips, the characteristic inspection of each semiconductor chip is performed after all the semiconductor chips are stacked. Therefore, if even one defective semiconductor chip is found, the entire semiconductor device becomes defective. As a result, even if other semiconductor chips are non-defective products, they are discarded and the non-defective semiconductor chips are wasted.
JP-A-6-13541

本発明の目的は、良品の半導体チップが無駄にならないようにすることにある。   An object of the present invention is to prevent a good semiconductor chip from being wasted.

（１）本発明に係る半導体装置は、第１の配線パターンが形成された第１のインターポーザと、前記第１のインターポーザに搭載されるとともに前記第１の配線パターンと電気的に接続された第１の半導体チップと、を有する第１のパッケージと、
第２の配線パターンが形成された第２のインターポーザと、前記第２のインターポーザに搭載されるとともに前記第２の配線パターンと電気的に接続された第２の半導体チップと、前記第２の半導体チップを封止するように前記第２のインターポーザに設けられた封止部と、を有し、前記第１のパッケージに積み重ねられた第２のパッケージと、
前記第１及び第２のパッケージを接合する複数の接合部と、
を有し、
前記封止部は、前記複数の接合部とオーバーラップするように設けられ、
前記複数の接合部は、前記第１及び第２の配線パターンを電気的に接続するコンタクト部を含み、
前記複数の接合部は、さらに、前記第１及び第２の配線パターンを電気的に接続しないノンコンタクト部と、前記コンタクト部によって電気的に接続される部分を電気的に接続する冗長コンタクト部と、のいずれか一方である補強部を含む。本発明によれば、第１のパッケージを組み立ててその特性検査を行い、第２のパッケージを組み立ててその特性検査を行うことができる。したがって、第１及び第２のパッケージのいずれか一方のみが不良品であっても、他方が良品であればこれを廃棄しなくてもよい。したがって、良品の半導体チップが無駄にならない。また、本発明では、補強部が設けられているので、第１及び第２のパッケージの接合強度が高められる。
（２）この半導体装置において、
前記第１のインターポーザは、矩形をなしており、
前記コンタクト部は、前記矩形のコーナー部を避けて配置され、
前記補強部は、前記コーナー部に配置されていてもよい。
（３）この半導体装置において、
前記封止部は、前記第１のインターポーザよりも熱膨張率が小さくてもよい。
（４）この半導体装置において、
前記補強部は、前記コンタクト部よりも大きい形状を有してもよい。
（５）この半導体装置において、
前記コンタクト部及び前記補強部は、同一材料から形成されていてもよい。
（６）本発明に係る回路基板は、上記半導体装置が実装されてなる。
（７）本発明に係る電子機器は、上記半導体装置を有する。
（８）本発明に係る半導体装置の製造方法は、第１の配線パターンが形成された第１のインターポーザに第１の半導体チップを搭載し、前記第１の配線パターンと前記第１の半導体チップを電気的に接続することを含む、第１のパッケージの組み立て、
第２の配線パターンが形成された第２のインターポーザに第２の半導体チップを搭載し、前記第２の配線パターンと前記第２の半導体チップを電気的に接続し、前記第２の半導体チップを封止するように前記第２のインターポーザに封止部を設けることを含む、第２のパッケージの組み立て、及び、
前記第１及び第２のパッケージを積み重ねて複数の接合部によって接合すること、
を含み、
前記封止部は、前記複数の接合部とオーバーラップするように設け、
前記複数の接合部は、前記第１及び第２の配線パターンを電気的に接続するコンタクト部を含み、
前記複数の接合部は、さらに、前記第１及び第２の配線パターンを電気的に接続しないノンコンタクト部と、前記コンタクト部によって電気的に接続される部分を電気的に接続する冗長コンタクト部と、のいずれか一方である補強部を含む。本発明によれば、第１のパッケージを組み立ててその特性検査を行い、第２のパッケージを組み立ててその特性検査を行うことができる。したがって、第１及び第２のパッケージのいずれか一方のみが不良品であっても、他方が良品であればこれを廃棄しなくてもよい。したがって、良品の半導体チップが無駄にならない。また、本発明では、補強部を設けるので、第１及び第２のパッケージの接合強度を高めることができる。
（９）この半導体装置の製造方法において、
前記第１及び第２のパッケージの接合前に、
前記コンタクト部を形成するための材料及び前記補強部を形成するための材料を、前記第２のパッケージに設けること、
をさらに含んでもよい。
（１０）この半導体装置の製造方法において、
前記第１及び第２のパッケージの接合前に、
前記補強部を形成するための材料を前記第１のパッケージに設けること、及び、
前記コンタクト部を形成するための材料を記第２のパッケージに設けること、
をさらに含んでもよい。
（１１）この半導体装置の製造方法において、
前記補強部を、前記コンタクト部よりも大きい形状になるように形成してもよい。
（１２）この半導体装置の製造方法において、
前記コンタクト部及び前記補強部を、同一材料から形成してもよい。 (1) A semiconductor device according to the present invention includes a first interposer on which a first wiring pattern is formed, and a first interposer mounted on the first interposer and electrically connected to the first wiring pattern. A first package having one semiconductor chip;
A second interposer on which a second wiring pattern is formed; a second semiconductor chip mounted on the second interposer and electrically connected to the second wiring pattern; and the second semiconductor A sealing part provided in the second interposer so as to seal the chip, and a second package stacked on the first package;
A plurality of joints for joining the first and second packages;
Have
The sealing portion is provided so as to overlap the plurality of joint portions,
The plurality of joint portions include contact portions that electrically connect the first and second wiring patterns,
The plurality of joint portions further include a non-contact portion that does not electrically connect the first and second wiring patterns, and a redundant contact portion that electrically connects a portion electrically connected by the contact portion. The reinforcement part which is any one of these is included. According to the present invention, it is possible to assemble the first package and perform its characteristic inspection, and assemble the second package and perform its characteristic inspection. Therefore, even if only one of the first and second packages is defective, it is not necessary to discard it if the other is a non-defective product. Therefore, a good semiconductor chip is not wasted. In the present invention, since the reinforcing portion is provided, the bonding strength of the first and second packages can be increased.
(2) In this semiconductor device,
The first interposer has a rectangular shape;
The contact portion is arranged avoiding the rectangular corner portion,
The reinforcing portion may be disposed at the corner portion.
(3) In this semiconductor device,
The sealing portion may have a smaller coefficient of thermal expansion than the first interposer.
(4) In this semiconductor device,
The reinforcing part may have a larger shape than the contact part.
(5) In this semiconductor device,
The contact part and the reinforcing part may be made of the same material.
(6) A circuit board according to the present invention has the semiconductor device mounted thereon.
(7) An electronic apparatus according to the present invention includes the semiconductor device.
(8) In the method of manufacturing a semiconductor device according to the present invention, a first semiconductor chip is mounted on a first interposer on which a first wiring pattern is formed, and the first wiring pattern and the first semiconductor chip are mounted. Assembling the first package, including electrically connecting
A second semiconductor chip is mounted on a second interposer on which a second wiring pattern is formed, the second wiring pattern and the second semiconductor chip are electrically connected, and the second semiconductor chip is mounted Assembling a second package comprising providing a seal in the second interposer to seal; and
Stacking the first and second packages and joining them by a plurality of joints;
Including
The sealing portion is provided so as to overlap the plurality of joint portions,
The plurality of joint portions include contact portions that electrically connect the first and second wiring patterns,
The plurality of joint portions further include a non-contact portion that does not electrically connect the first and second wiring patterns, and a redundant contact portion that electrically connects a portion electrically connected by the contact portion. The reinforcement part which is any one of these is included. According to the present invention, it is possible to assemble the first package and perform its characteristic inspection, and assemble the second package and perform its characteristic inspection. Therefore, even if only one of the first and second packages is defective, it is not necessary to discard it if the other is a non-defective product. Therefore, a good semiconductor chip is not wasted. Moreover, in this invention, since the reinforcement part is provided, the joint strength of the 1st and 2nd package can be raised.
(9) In this method of manufacturing a semiconductor device,
Prior to joining the first and second packages,
Providing the second package with a material for forming the contact portion and a material for forming the reinforcing portion;
May further be included.
(10) In this method of manufacturing a semiconductor device,
Prior to joining the first and second packages,
Providing the first package with a material for forming the reinforcing portion; and
Providing the second package with a material for forming the contact portion;
May further be included.
(11) In this method of manufacturing a semiconductor device,
You may form the said reinforcement part so that it may become a shape larger than the said contact part.
(12) In this method of manufacturing a semiconductor device,
The contact portion and the reinforcing portion may be formed from the same material.

以下、本発明の実施の形態を、図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図１は、本発明の実施の形態に係る半導体装置を説明する平面図である。図２は、図１に示す半導体装置のII−II線断面図であり、図３は、図１に示す半導体装置のIII−III線断面図である。   FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. 2 is a cross-sectional view taken along line II-II of the semiconductor device shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III of the semiconductor device shown in FIG.

半導体装置は、第１のパッケージ１０を有する。第１のパッケージ１０は、第１のインターポーザ１２を有する。第１のインターポーザ１２は、基板であって、プレートであってもよい。第１のインターポーザ１２は矩形をなしていてもよい。第１のインターポーザ１２は、ポリイミド樹脂などの樹脂で形成されていてもよいし、樹脂などの有機材料及び無機材料の混合材料で形成されてもよいし、金属基板やセラミック基板であってもよい。第１のインターポーザ１２には、第１の配線パターン１４が形成されている。第１の配線パターン１４は、複数点を電気的に接続する配線と、他の部品との電気的な接続部となるランドを有していてもよい。第１の配線パターン１４は、第１のインターポーザ１２の少なくとも一方の面に形成されている。第１の配線パターン１４は、図示しないスルーホールを通して電気的に接続されるように、第１のインターポーザ１２の両面に形成してもよい。   The semiconductor device has a first package 10. The first package 10 has a first interposer 12. The first interposer 12 is a substrate and may be a plate. The first interposer 12 may be rectangular. The first interposer 12 may be formed of a resin such as a polyimide resin, may be formed of a mixed material of an organic material such as a resin and an inorganic material, or may be a metal substrate or a ceramic substrate. . A first wiring pattern 14 is formed on the first interposer 12. The 1st wiring pattern 14 may have the land used as the electrical connection part of the wiring which electrically connects several points, and another component. The first wiring pattern 14 is formed on at least one surface of the first interposer 12. The first wiring pattern 14 may be formed on both surfaces of the first interposer 12 so as to be electrically connected through a through hole (not shown).

第１のパッケージ１０は、第１の半導体チップ１６を有する。第１の半導体チップ１６には、集積回路１８が形成されている。第１の半導体チップ１６は、第１のインターポーザ１２に搭載され、第１の配線パターン１４に電気的に接続されている。図２に示すように、第１の半導体チップ１６を、第１のインターポーザ１２にフェースダウンボンディングしてもよい。その場合、第１の半導体チップ１６の電極となるバンプ１７と第１の配線パターン１４とを対向させて、両者を電気的に接続してもよい。この電気的接続には、異方性導電材料（異方性導電膜又は異方性導電ペースト等）を使用してもよいし、絶縁性接着剤を使用してその収縮力を利用してバンプ１７と第１の配線パターン１４とを圧接させてもよいし、バンプ１７と第１の配線パターン１４とを金属接合してもよい。変形例として、第１の半導体チップ１６を第１のインターポーザ１２にフェースアップボンディングして、電気的接続にワイヤを使用してもよい。   The first package 10 has a first semiconductor chip 16. An integrated circuit 18 is formed on the first semiconductor chip 16. The first semiconductor chip 16 is mounted on the first interposer 12 and is electrically connected to the first wiring pattern 14. As shown in FIG. 2, the first semiconductor chip 16 may be face-down bonded to the first interposer 12. In that case, the bumps 17 serving as the electrodes of the first semiconductor chip 16 and the first wiring pattern 14 may be opposed to each other and electrically connected to each other. For this electrical connection, an anisotropic conductive material (such as an anisotropic conductive film or anisotropic conductive paste) may be used, or an insulating adhesive is used to make a bump by utilizing the shrinkage force. 17 and the first wiring pattern 14 may be press-contacted, or the bump 17 and the first wiring pattern 14 may be metal-bonded. As a modification, the first semiconductor chip 16 may be face-up bonded to the first interposer 12 and a wire may be used for electrical connection.

第１のパッケージ１０は、複数の外部端子（例えばハンダボール）１９を有していてもよい。外部端子１９は、第１のインターポーザ１２の、第１の半導体チップ１６が搭載された面とは反対側に設けられる。外部端子１９は、第１の配線パターン１４の一部となるランド上に設けてもよい。外部端子１９は、軟ろう（soft solder）又は硬ろう（hard solder）のいずれで形成してもよい。軟ろうとして、鉛を含まないハンダ（以下、鉛フリーハンダという。）を使用してもよい。鉛フリーハンダとして、スズー銀（Ｓｎ―Ａｇ）系、スズ−ビスマス（Ｓｎ−Ｂｉ）系、スズ−亜鉛（Ｓｎ−Ｚｎ）系、あるいはスズ−銅（Ｓｎ−Ｃｕ）系の合金を使用してもよいし、これらの合金に、さらに銀、ビスマス、亜鉛、銅のうち少なくとも１つを添加してもよい。   The first package 10 may have a plurality of external terminals (for example, solder balls) 19. The external terminal 19 is provided on the opposite side of the surface of the first interposer 12 on which the first semiconductor chip 16 is mounted. The external terminal 19 may be provided on a land that becomes a part of the first wiring pattern 14. The external terminal 19 may be formed of either soft solder or hard solder. As the soft solder, solder containing no lead (hereinafter referred to as lead-free solder) may be used. As lead-free solder, using tin-silver (Sn-Ag), tin-bismuth (Sn-Bi), tin-zinc (Sn-Zn), or tin-copper (Sn-Cu) alloys Alternatively, at least one of silver, bismuth, zinc, and copper may be added to these alloys.

半導体装置は、第２のパッケージ２０を有する。第２のパッケージ２０は、第２のインターポーザ２２を有する。第２のインターポーザ２２には、第１のインターポーザ１２についての説明が該当する。さらに、第２のインターポーザ２２は、第１のインターポーザ１２と同じ材料で形成してもよいし、同じ厚みで形成してもよいし、同じ熱膨張率を有していてもよい。あるいは、第２のインターポーザ２２は、第１のインターポーザ１２と異なる材料で形成してもよいし、異なる厚みで形成してもよい。また、第１及び第２のインターポーザ１２，２２は、いずれか一方が他方よりも熱膨張率が大きくてもよい。なお、熱膨張率は、加熱時の膨張率であるとともに、冷却時の収縮率でもある。第２のインターポーザ２２には、第２の配線パターン２４が形成されている。第２の配線パターン２４には、第１の配線パターン１４についての説明が該当する。   The semiconductor device has a second package 20. The second package 20 has a second interposer 22. The description of the first interposer 12 corresponds to the second interposer 22. Furthermore, the second interposer 22 may be formed of the same material as the first interposer 12, may be formed with the same thickness, and may have the same coefficient of thermal expansion. Alternatively, the second interposer 22 may be formed of a material different from that of the first interposer 12, or may be formed with a different thickness. In addition, one of the first and second interposers 12 and 22 may have a higher coefficient of thermal expansion than the other. The thermal expansion coefficient is an expansion coefficient during heating and a contraction ratio during cooling. A second wiring pattern 24 is formed in the second interposer 22. The description of the first wiring pattern 14 corresponds to the second wiring pattern 24.

第２のパッケージ２０は、第２の半導体チップ２６を有する。第２の半導体チップ２６には、集積回路２８が形成されている。第２の半導体チップ２６は、第２のインターポーザ２２に搭載され、第２の配線パターン２４に電気的に接続されている。図２に示すように、第２の半導体チップ２６を第２のインターポーザ２２にフェースアップボンディングしてもよい。その場合、第２の半導体チップ２６のパッド２７及び第２の配線パターン２４にワイヤ２９をボンディングしてもよい。変形例として、第２の半導体チップ２６を、第２のインターポーザ２２にフェースダウンボンディングしてもよい。その電気的接続には、第１の半導体チップ１６についての内容を適用することができる。   The second package 20 has a second semiconductor chip 26. An integrated circuit 28 is formed on the second semiconductor chip 26. The second semiconductor chip 26 is mounted on the second interposer 22 and is electrically connected to the second wiring pattern 24. As shown in FIG. 2, the second semiconductor chip 26 may be face-up bonded to the second interposer 22. In that case, a wire 29 may be bonded to the pad 27 and the second wiring pattern 24 of the second semiconductor chip 26. As a modification, the second semiconductor chip 26 may be face-down bonded to the second interposer 22. The contents of the first semiconductor chip 16 can be applied to the electrical connection.

第２のパッケージ２０は、封止部３０を有する。封止部３０は、第２の半導体チップ２６を封止しており、電気的接続部（例えばワイヤ２９）を封止していてもよい。封止部３０は、第２のインターポーザ２２に設けられている。封止部３０は、後述する複数の接合部４０とオーバーラップするように形成されている。封止部３０は、樹脂（例えばモールド樹脂）で形成してもよい。封止部３０は、第１のインターポーザ１２よりも熱膨張率が小さくてもよいし、第２のインターポーザ２２よりも熱膨張率が小さくてもよい。熱膨張率を小さくするために、封止部３０はシリカを含有していてもよい。第１及び第２のインターポーザ１２，２２の熱膨張率が、それぞれ単体としては同じであっても、封止部３０が設けられることで、第２のインターポーザ２２の熱膨張率が、第１のインターポーザ１２よりも小さくなってもよい。   The second package 20 has a sealing portion 30. The sealing portion 30 seals the second semiconductor chip 26 and may seal an electrical connection portion (for example, the wire 29). The sealing unit 30 is provided in the second interposer 22. The sealing part 30 is formed so as to overlap with a plurality of joints 40 described later. The sealing part 30 may be formed of a resin (for example, a mold resin). The sealing part 30 may have a smaller coefficient of thermal expansion than the first interposer 12 or may have a smaller coefficient of thermal expansion than the second interposer 22. In order to reduce the coefficient of thermal expansion, the sealing portion 30 may contain silica. Even if the thermal expansion coefficients of the first and second interposers 12 and 22 are the same as a single body, the sealing section 30 is provided, so that the thermal expansion coefficient of the second interposer 22 is It may be smaller than the interposer 12.

第１及び第２のパッケージ１０，２０は、積み重ねられている。例えば、第１のパッケージ１０の、第１の半導体チップ１６が搭載された側に、第２のパッケージ２０を積み重ねてもよい。第２のパッケージ２０の第２の半導体チップ２６が搭載された側を、第１のパッケージ１０の第１の半導体チップ１６とは反対側に配置してもよい。   The first and second packages 10 and 20 are stacked. For example, the second package 20 may be stacked on the side of the first package 10 on which the first semiconductor chip 16 is mounted. The side of the second package 20 on which the second semiconductor chip 26 is mounted may be disposed on the opposite side of the first package 10 from the first semiconductor chip 16.

本発明は、２つのパッケージのみならず、２つを超える複数のパッケージを積み重ねた形態にも適用可能である。その場合、上下に隣り合うように積み重ねられた２つのパッケージに、本実施の形態に係る第１及び第２のパッケージ１０，２０の内容が適用される。   The present invention can be applied not only to two packages but also to a form in which a plurality of more than two packages are stacked. In that case, the contents of the first and second packages 10 and 20 according to the present embodiment are applied to two packages stacked so as to be adjacent to each other vertically.

第１及び第２のパッケージ１０，２０は、複数の接合部４０によって接合されている。接合部４０は、第１及び第２のパッケージ２０の間に設けられている。複数の接合部４０は、第１及び第２の配線パターン１４，２４を電気的に接続する１つ又は複数のコンタクト部４２を含む。例えば、第１の配線パターン１４の一部（例えばランド）と、第２の配線パターン２４の一部（例えばランド）が相互に対向しており、この対向する部分間にコンタクト部４２を設けてもよい。   The first and second packages 10 and 20 are joined by a plurality of joints 40. The joint 40 is provided between the first and second packages 20. The plurality of joint portions 40 include one or a plurality of contact portions 42 that electrically connect the first and second wiring patterns 14 and 24. For example, a part (for example, land) of the first wiring pattern 14 and a part (for example, land) of the second wiring pattern 24 face each other, and a contact portion 42 is provided between the facing parts. Also good.

複数の接合部４０は、１つ又は複数の補強部４４を含む。補強部４４は、コンタクト部４２と同じ材料で形成してもよいし、異なる材料で形成してもよい。各補強部４４は、第１及び第２の配線パターン１４，２４を電気的に接続しないノンコンタクト部、あるいは、コンタクト部４２によって電気的に接続される部分（第１及び第２の配線パターン１４，２４の部分）を電気的に接続する冗長コンタクト部である。すなわち、補強部４４は、電気的接続に無関係のもの、あるいは、電気的に接続しているが切断されてもかまわないものである。補強部４４は、それがノンコンタクト部である場合、第１又は第２の配線パターン１４，２４に電気的に接続されないランド上に設けてもよい。補強部４４は、それが冗長コンタクト部である場合、第１又は第２の配線パターン１４，２４の一部（ランド）上に設けてもよい。補強部４４を設けることで、第１及び第２のパッケージ１０，２０の接合強度を高めることができる。また、コンタクト部４２にクラックが生じることも防止することができる。   The plurality of joint portions 40 include one or more reinforcing portions 44. The reinforcing portion 44 may be formed of the same material as the contact portion 42 or may be formed of a different material. Each reinforcing portion 44 is a non-contact portion that is not electrically connected to the first and second wiring patterns 14, 24, or a portion that is electrically connected by the contact portion 42 (the first and second wiring patterns 14. , 24) is a redundant contact portion for electrically connecting. That is, the reinforcing portion 44 is irrelevant to electrical connection, or is electrically connected but may be disconnected. When the reinforcing portion 44 is a non-contact portion, the reinforcing portion 44 may be provided on a land that is not electrically connected to the first or second wiring pattern 14, 24. When the reinforcing portion 44 is a redundant contact portion, the reinforcing portion 44 may be provided on a part (land) of the first or second wiring pattern 14, 24. By providing the reinforcing portion 44, the bonding strength of the first and second packages 10 and 20 can be increased. Further, it is possible to prevent the contact portion 42 from being cracked.

第１及び第２のインターポーザ１２，２２の熱膨張率に差があれば、接合部４０に応力が生じる。なお、第１及び第２のインターポーザ１２，２２の熱膨張率は、それ自体を構成する材料に起因するだけでなく、その上に設けられた部材（例えば封止部３０）の影響も受ける。加熱時の膨張又は冷却時の収縮による変位が大きい部分において、接合部４０に生じる応力は大きくなる。第１のインターポーザ１２が矩形をなす場合、そのコーナー部に設けられた接合部４０に応力が集中する。したがって、コーナー部に補強部４４を配置し、コーナー部を避けてコンタクト部４２を配置すれば、コンタクト部４２に生じる応力を減らすことができる。さらに、補強部４４は、コンタクト部４２よりも大きい形状（例えば接合面積において大きい形状又は幅において大きい形状）を有していてもよい。   If there is a difference in the coefficient of thermal expansion between the first and second interposers 12 and 22, stress is generated at the joint 40. Note that the thermal expansion coefficients of the first and second interposers 12 and 22 are not only caused by the material constituting the first interposers 12 and 22, but are also affected by the members (for example, the sealing portion 30) provided thereon. In a portion where displacement due to expansion during heating or contraction during cooling is large, the stress generated in the joint 40 becomes large. When the 1st interposer 12 makes a rectangle, stress concentrates on the junction part 40 provided in the corner part. Therefore, if the reinforcing portion 44 is disposed at the corner portion and the contact portion 42 is disposed away from the corner portion, the stress generated in the contact portion 42 can be reduced. Further, the reinforcing portion 44 may have a shape larger than the contact portion 42 (for example, a shape having a large bonding area or a shape having a large width).

図４は、本発明に係る半導体装置の製造方法の一部を説明する図であり、詳しくは第１のパッケージの組み立てを説明する図である。図５は、図４のＶ−Ｖ線断面の一部拡大図であり、図６は、図４のVI−VI線断面の一部拡大図である。本実施の形態では、第１のインターポーザ５０を使用する。第１のインターポーザ５０は、後の工程で切断されて、複数の第１のインターポーザ１２（図１参照）を提供するものである。すなわち、第１のインターポーザ５０は、複数の第１のインターポーザ１２となる領域を含む。第１のインターポーザ５０には、複数の第１の配線パターン１４が形成されている。変形例として、個々の第１のパッケージの一部となる第１のインターポーザ１２を組み立て工程で使用してもよい。   FIG. 4 is a diagram for explaining a part of the manufacturing method of the semiconductor device according to the present invention, and more specifically, for explaining the assembly of the first package. 5 is a partially enlarged view of the VV line section of FIG. 4, and FIG. 6 is a partially enlarged view of the VI-VI line section of FIG. 4. In the present embodiment, the first interposer 50 is used. The first interposer 50 is cut in a later process to provide a plurality of first interposers 12 (see FIG. 1). That is, the first interposer 50 includes a region to be a plurality of first interposers 12. A plurality of first wiring patterns 14 are formed in the first interposer 50. As a modification, the first interposer 12 that becomes a part of each first package may be used in the assembly process.

第１のインターポーザ１２には、第１の半導体チップ１６を搭載する。本実施の形態では、第１のインターポーザ５０の、複数の第１のインターポーザ１２となる領域のそれぞれに第１の半導体チップ１６を搭載する。また、第１の配線パターン１４と第１の半導体チップ１６を電気的に接続する。本実施の形態では、第１のインターポーザ５０の、複数の第１の配線パターン１４のそれぞれと、第１の半導体チップ１６を電気的に接続する。第１のパッケージの組み立ては、上述した第１のパッケージ１０の説明から導き出すことができるプロセスを含む。さらに、第１のパッケージ１０について、第１の半導体チップ１６の特性検査を行って、良品・不良品の判断をする。不良品と判断された第１のパッケージ１０には、後の工程で、第２のパッケージ２０を積み重ねない。   A first semiconductor chip 16 is mounted on the first interposer 12. In the present embodiment, the first semiconductor chip 16 is mounted on each of the regions of the first interposer 50 to be the plurality of first interposers 12. Further, the first wiring pattern 14 and the first semiconductor chip 16 are electrically connected. In the present embodiment, each of the plurality of first wiring patterns 14 of the first interposer 50 and the first semiconductor chip 16 are electrically connected. The assembly of the first package includes a process that can be derived from the description of the first package 10 described above. Further, the first package 10 is subjected to the characteristic inspection of the first semiconductor chip 16 to determine whether the product is good or defective. In the subsequent process, the second package 20 is not stacked on the first package 10 determined to be defective.

図７及び図８は、本発明に係る半導体装置の製造方法の一部を説明する図であり、詳しくは第２のパッケージの組み立てを説明する図である。本実施の形態では、図７に示すように、第２の配線パターン２４が形成された第２のインターポーザ２２に第２の半導体チップ２６を搭載する。また、第２の配線パターン２４と第２の半導体チップ２６を電気的に接続する。これらのプロセスの詳細は、上述した第２のパッケージ２０の説明から導き出すことができる。変形例として、複数の第２のインターポーザ２２となる領域を含む第２のインターポーザを使用してもよい。その詳細は、第１のインターポーザ５０についての内容が該当する。   7 and 8 are diagrams for explaining a part of the manufacturing method of the semiconductor device according to the present invention, and more specifically for explaining the assembly of the second package. In the present embodiment, as shown in FIG. 7, the second semiconductor chip 26 is mounted on the second interposer 22 in which the second wiring pattern 24 is formed. Further, the second wiring pattern 24 and the second semiconductor chip 26 are electrically connected. Details of these processes can be derived from the description of the second package 20 described above. As a modification, a second interposer including a region to be a plurality of second interposers 22 may be used. The details correspond to the contents of the first interposer 50.

そして、図８に示すように、第２の半導体チップ２６を封止するように第２のインターポーザ２２に封止部３０を設ける。封止部３０は、トランスファーモールドによって形成してもよい。このプロセスの詳細は、上述した第２のパッケージ２０の説明から導き出すことができる。さらに、第２のパッケージ２０について、第２の半導体チップ２６の特性検査を行って、良品・不良品の判断をする。特性検査は、封止部３０の形成後に行ってもよいが、その形成前に行って、不良品と判断された第２の半導体チップ２６には封止部３０を設けないことにしてもよい。   And as shown in FIG. 8, the sealing part 30 is provided in the 2nd interposer 22 so that the 2nd semiconductor chip 26 may be sealed. The sealing part 30 may be formed by transfer molding. Details of this process can be derived from the description of the second package 20 described above. Further, the second package 20 is subjected to a characteristic inspection of the second semiconductor chip 26 to determine whether the product is good or defective. The characteristic inspection may be performed after the sealing portion 30 is formed, but may be performed before the formation, and the second semiconductor chip 26 determined to be defective may not be provided with the sealing portion 30. .

図９（Ａ）及び図９（Ｂ）は、本発明に係る半導体装置の製造方法の一部を説明する図である。本実施の形態では、第１及び第２のパッケージ１０，２０の接合前に、コンタクト部４２の少なくとも一部を形成するための材料５２及び補強部４４の少なくとも一部を形成するための材料５４を、第２のパッケージ２０に設ける。材料５２，５４は、固形であってもよい。材料５２，５４は、軟ろう（soft solder）又は硬ろう（hard solder）であってもよい。軟ろうとして、上述した鉛フリーハンダを使用してもよい。   9A and 9B are diagrams for explaining a part of the manufacturing method of the semiconductor device according to the present invention. In the present embodiment, before joining the first and second packages 10 and 20, a material 52 for forming at least a part of the contact part 42 and a material 54 for forming at least a part of the reinforcing part 44. Are provided in the second package 20. The materials 52 and 54 may be solid. The materials 52, 54 may be soft solder or hard solder. As the soft solder, the above-mentioned lead-free solder may be used.

なお、第１のパッケージ１０に、材料５２，５４に対向する位置に、コンタクト部４２の他の一部を形成するための材料５６及び補強部４４の他の一部を形成するための材料５８を設けてもよい。材料５６，５８は、それぞれ、材料５２，５４と一体化して、コンタクト部４２及び補強部４４となる。材料５６，５８は、ハンダペースト等のペーストであってもよい。ハンダペーストにも鉛フリーハンダを使用することができる。   In the first package 10, a material 56 for forming another part of the contact portion 42 and a material 58 for forming another part of the reinforcing portion 44 at positions facing the materials 52, 54. May be provided. The materials 56 and 58 are integrated with the materials 52 and 54 to form the contact portion 42 and the reinforcing portion 44, respectively. The materials 56 and 58 may be pastes such as solder paste. Lead-free solder can also be used for the solder paste.

そして、第１及び第２のパッケージ１０，２０を積み重ねる。詳しくは、複数の第１のインターポーザ１２となる領域を有する第１のインターポーザ５０を使用し、それぞれの第１のインターポーザ１２となる領域に、第２のパッケージ２０を積み重ねる。なお、不良品と判断された第１のパッケージ１０には、第２のパッケージ２０を積み重ねない。こうすることで、第２のパッケージ２０（第２の半導体チップ２６）が無駄になるのを避けることができる。   Then, the first and second packages 10 and 20 are stacked. In detail, the 1st interposer 50 which has the field used as a plurality of 1st interposers 12 is used, and the 2nd package 20 is stacked in the field used as each 1st interposer 12. Note that the second package 20 is not stacked on the first package 10 determined to be defective. By doing so, it is possible to avoid the waste of the second package 20 (second semiconductor chip 26).

図１０（Ａ）及び図１０（Ｂ）は、第１及び第２のパッケージを接合する工程を説明する図である。例えば、リフロー工程を経て、図９（Ａ）及び図９（Ｂ）に示す材料５２，５４，５６，５８を溶融して、接合部４０（コンタクト部４２及び補強部４４）を形成する。   FIGS. 10A and 10B are diagrams illustrating a process of joining the first and second packages. For example, through the reflow process, the materials 52, 54, 56, and 58 shown in FIGS. 9A and 9B are melted to form the joint portion 40 (the contact portion 42 and the reinforcing portion 44).

図１１（Ａ）及び図１１（Ｂ）は、本発明に係る半導体装置の製造方法の一部を説明する図である。上述した第１のインターポーザ５０を使用した場合、これを複数の第１のインターポーザ１２に切断する。また、外部端子１９を設ける。   11A and 11B are diagrams for explaining a part of the manufacturing method of the semiconductor device according to the present invention. When the first interposer 50 described above is used, it is cut into a plurality of first interposers 12. In addition, an external terminal 19 is provided.

本実施の形態では、以上の工程を経て、半導体装置を製造することができる。このプロセスは、半導体装置の構造についての説明から導き出すことができる内容を含む。   In this embodiment, a semiconductor device can be manufactured through the above steps. This process includes content that can be derived from a description of the structure of the semiconductor device.

図１２は、本発明に係る半導体装置の製造方法の変形例を説明する図である。この変形例では、図９（Ｂ）に示す形態と異なり、第１及び第２のパッケージ１０，２０の接合前に、補強部４４を形成するための材料（固形材料）５４を第１のパッケージ１０に設ける。なお、図９（Ａ）に示す形態と同様に、コンタクト部４２を形成するための材料（ペースト材料）５２は第２のパッケージ２０に設ける。本発明は、この形態も含む。   FIG. 12 is a diagram illustrating a modification of the method for manufacturing a semiconductor device according to the present invention. In this modification, unlike the embodiment shown in FIG. 9B, the material (solid material) 54 for forming the reinforcing portion 44 is applied to the first package before the first and second packages 10 and 20 are joined. 10 is provided. Note that a material (paste material) 52 for forming the contact portion 42 is provided in the second package 20 as in the embodiment shown in FIG. The present invention also includes this form.

図１３は、本発明に係る半導体装置の製造方法の変形例を説明する図である。この変形例では、図９（Ａ）及び図９（Ｂ）に示す形態と異なり、補強部を形成するための複数の固形材料６０を、隣接するように、あるいは溶融したときに一体化する程度に接近するように配置する。各固形材料６０は、コンタクト部４２を形成するための材料（固形材料）５２と同じ形状であってもよい。この場合、材料５２及び固形材料６０として、同じものを使用すれば、使用する部品の種類を減らすことができる。また、コンタクト部４２を形成するための材料（固形材料）５２と、補強部を形成するための固形材料６０と、を同じ側（第１のパッケージ１０又は第２のパッケージ２０）に設けてもよい。その場合、両者を一度に設けることができるので、工程を減らすことができる。   FIG. 13 is a diagram illustrating a modification of the method for manufacturing a semiconductor device according to the present invention. In this modified example, unlike the forms shown in FIGS. 9A and 9B, a plurality of solid materials 60 for forming the reinforcing portion are integrated so as to be adjacent or melted. Arrange to approach. Each solid material 60 may have the same shape as the material (solid material) 52 for forming the contact portion 42. In this case, if the same material 52 and solid material 60 are used, the types of parts to be used can be reduced. Further, the material (solid material) 52 for forming the contact portion 42 and the solid material 60 for forming the reinforcing portion may be provided on the same side (the first package 10 or the second package 20). Good. In that case, since both can be provided at once, the number of steps can be reduced.

図１４には、上述した実施の形態で説明した半導体装置１が実装された回路基板１０００が示されている。この半導体装置を有する電子機器として、図１５にはノート型パーソナルコンピュータ２０００が示され、図１６には携帯電話３０００が示されている。   FIG. 14 shows a circuit board 1000 on which the semiconductor device 1 described in the above embodiment is mounted. As an electronic apparatus having this semiconductor device, FIG. 15 shows a notebook personal computer 2000 and FIG. 16 shows a mobile phone 3000.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。さらに、本発明は、実施の形態で説明した技術的事項のいずれかを限定的に除外した内容を含む。あるいは、本発明は、上述した実施の形態から公知技術を限定的に除外した内容を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment. Furthermore, the present invention includes contents that exclude any of the technical matters described in the embodiments in a limited manner. Or this invention includes the content which excluded the well-known technique limitedly from embodiment mentioned above.

図１は、本発明の実施の形態に係る半導体装置を説明する平面図である。FIG. 1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. 図２は、図１に示す半導体装置のII−II線断面図である。2 is a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line II-II. 図３は、図１に示す半導体装置のIII−III線断面図である。3 is a cross-sectional view taken along line III-III of the semiconductor device shown in FIG. 図４は、本発明に係る半導体装置の製造方法の一部を説明する図である。FIG. 4 is a diagram for explaining a part of the manufacturing method of the semiconductor device according to the present invention. 図５は、図４のＶ−Ｖ線断面の一部拡大図である。FIG. 5 is a partially enlarged view of the VV line cross section of FIG. 図６は、図４のVI−VI線断面の一部拡大図である。6 is a partially enlarged view of a cross section taken along line VI-VI in FIG. 図７は、本発明に係る半導体装置の製造方法の一部を説明する図である。FIG. 7 is a diagram for explaining a part of the manufacturing method of the semiconductor device according to the present invention. 図８は、本発明に係る半導体装置の製造方法の一部を説明する図である。FIG. 8 is a diagram for explaining a part of the manufacturing method of the semiconductor device according to the present invention. 図９（Ａ）及び図９（Ｂ）は、本発明に係る半導体装置の製造方法の一部を説明する図である。9A and 9B are diagrams for explaining a part of the manufacturing method of the semiconductor device according to the present invention. 図１０（Ａ）及び図１０（Ｂ）は、第１及び第２のパッケージを接合する工程を説明する図である。FIGS. 10A and 10B are diagrams illustrating a process of joining the first and second packages. 図１１（Ａ）及び図１１（Ｂ）は、本発明に係る半導体装置の製造方法の一部を説明する図である。11A and 11B are diagrams for explaining a part of the manufacturing method of the semiconductor device according to the present invention. 図１２は、本発明に係る半導体装置の製造方法の変形例を説明する図である。FIG. 12 is a diagram illustrating a modification of the method for manufacturing a semiconductor device according to the present invention. 図１３は、本発明に係る半導体装置の製造方法の変形例を説明する図である。FIG. 13 is a diagram illustrating a modification of the method for manufacturing a semiconductor device according to the present invention. 図１４は、本実施の形態に係る半導体装置が実装された回路基板を示す図である。FIG. 14 is a diagram showing a circuit board on which the semiconductor device according to the present embodiment is mounted. 図１５は、本実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 15 illustrates an electronic device including the semiconductor device according to this embodiment. 図１６は、本実施の形態に係る半導体装置を有する電子機器を示す図である。FIG. 16 illustrates an electronic device having the semiconductor device according to this embodiment.

符号の説明Explanation of symbols

１０…第１のパッケージ １２…第１のインターポーザ １４…第１の配線パターン １６…第１の半導体チップ １７…バンプ １８…集積回路 １９…外部端子 ２０…第２のパッケージ ２２…第２のインターポーザ ２４…第２の配線パターン ２６…第２の半導体チップ ２８…集積回路 ２９…ワイヤ ３０…封止部 ４０…接合部 ４２…コンタクト部 ４４…補強部 ５０…第１のインターポーザ ５２…材料 ５４…材料 ５６…材料 ５８…材料 ６０…固形材料   DESCRIPTION OF SYMBOLS 10 ... 1st package 12 ... 1st interposer 14 ... 1st wiring pattern 16 ... 1st semiconductor chip 17 ... Bump 18 ... Integrated circuit 19 ... External terminal 20 ... 2nd package 22 ... 2nd interposer 24 ... Second wiring pattern 26 ... Second semiconductor chip 28 ... Integrated circuit 29 ... Wire 30 ... Sealing part 40 ... Junction part 42 ... Contact part 44 ... Reinforcement part 50 ... First interposer 52 ... Material 54 ... Material 56 ... Material 58 ... Material 60 ... Solid material

Claims (5)

第１の配線パターンが形成された第１のインターポーザに第１の半導体チップを搭載し、前記第１の配線パターンと前記第１の半導体チップを電気的に接続することを含む、第１のパッケージの組み立て、
第２の配線パターンが形成された第２のインターポーザに第２の半導体チップを搭載し、前記第２の配線パターンと前記第２の半導体チップを電気的に接続し、前記第２の半導体チップを封止するように前記第２のインターポーザに封止部を設けることを含む、第２のパッケージの組み立て、
前記第１及び第２のパッケージの前記第１及び第２の半導体チップの特性検査を行うこと、及び、
前記第１及び第２のパッケージを積み重ねて複数の接合部によって接合すること、
を含み、
前記封止部は、前記複数の接合部とオーバーラップするように設け、
前記複数の接合部は、前記第１及び第２の配線パターンを電気的に接続するコンタクト部を含み、
前記複数の接合部は、さらに、前記第１及び第２の配線パターンを電気的に接続しないノンコンタクト部と、前記コンタクト部によって電気的に接続される部分を電気的に接続する冗長コンタクト部と、のいずれか一方である補強部を含み、
前記補強部を、前記コンタクト部を形成するための複数の固形材料を隣接するように配置し、前記複数の固形材料を溶融し、一体化させて形成する、半導体装置の製造方法。 A first package comprising: mounting a first semiconductor chip on a first interposer on which a first wiring pattern is formed; and electrically connecting the first wiring pattern and the first semiconductor chip. Assembly,
A second semiconductor chip is mounted on a second interposer on which a second wiring pattern is formed, the second wiring pattern and the second semiconductor chip are electrically connected, and the second semiconductor chip is mounted Assembling a second package comprising providing a seal in the second interposer to seal;
Performing a characteristic inspection of the first and second semiconductor chips of the first and second packages; and
Stacking the first and second packages and joining them by a plurality of joints;
Including
The sealing portion is provided so as to overlap the plurality of joint portions,
The plurality of joint portions include contact portions that electrically connect the first and second wiring patterns,
The plurality of joint portions further include a non-contact portion that does not electrically connect the first and second wiring patterns, and a redundant contact portion that electrically connects a portion electrically connected by the contact portion. Including a reinforcing part that is either one of
A method of manufacturing a semiconductor device, wherein the reinforcing portion is formed by arranging a plurality of solid materials for forming the contact portion so as to be adjacent to each other, and melting and integrating the plurality of solid materials . 請求項１記載の半導体装置の製造方法において、
前記第１及び第２のパッケージの接合前に、
前記コンタクト部を形成するための材料及び前記補強部を形成するための材料を、前記第２のパッケージに設けること、
をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 ,
Prior to joining the first and second packages,
Providing the second package with a material for forming the contact portion and a material for forming the reinforcing portion;
A method for manufacturing a semiconductor device further comprising: 請求項１記載の半導体装置の製造方法において、
前記第１及び第２のパッケージの接合前に、
前記補強部を形成するための材料を前記第１のパッケージに設けること、及び、
前記コンタクト部を形成するための材料を記第２のパッケージに設けること、
をさらに含む半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 ,
Prior to joining the first and second packages,
Providing the first package with a material for forming the reinforcing portion; and
Providing the second package with a material for forming the contact portion;
A method for manufacturing a semiconductor device further comprising: 請求項１から請求項３のいずれかに記載の半導体装置の製造方法において、
前記補強部を、前記コンタクト部よりも大きい形状になるように形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-3 ,
The manufacturing method of the semiconductor device which forms the said reinforcement part so that it may become a shape larger than the said contact part. 請求項１から請求項４のいずれかに記載の半導体装置の製造方法において、
前記コンタクト部及び前記補強部を、同一材料から形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device in any one of Claims 1-4 ,
A method of manufacturing a semiconductor device, wherein the contact portion and the reinforcing portion are formed of the same material.
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