JP4371263B2 - Equalizer circuit device - Google Patents

Description

  The present invention relates to an equalizer circuit device, and more particularly to an equalizer circuit device that can be used up to a high frequency.

Conventionally, various equalizer circuits have been proposed as equalization circuits that compensate for distortion of the waveform of a received signal received via a digital transmission line. Patent Document 1 below discloses a transversal filter type equalizer circuit capable of digital processing and analog processing.
JP-A-8-46553

  When the above-described conventional equalizer circuit performs digital signal processing, it is necessary to have a processing device that performs A / D conversion, multiplication, addition, and the like with high accuracy, and when it is realized by analog signal processing, As a multiplier for multiplying coefficients, a variable gain amplifier capable of precise control of gain and having a wide dynamic range is required. When the transmission speed of the transmission line is low, the A / D converter, the processing device, or the variable gain amplifier described above can be easily obtained or manufactured, and both digital processing and analog processing can be realized.

  However, digital signal processing is very difficult for signals in a transmission band of several hundred MHz or more necessary for a high-speed full-duplex digital data transmission line (LAN) having a transmission speed of several gigabps or more. In addition, even with analog processing, there is a problem that a variable gain amplifier that can precisely control gain at a very high frequency and has a wide dynamic range cannot be obtained or manufactured, or is very difficult. there were.

  The present invention has been made to solve the above-described problems. To this end, the equalizer circuit device of the present invention includes a delay unit that delays one signal of a differential signal, the other signal of the differential signal, and the delay. An output signal of the means, and an addition means for outputting a plurality of addition signals obtained by adding two signals at different ratios, a plurality of variable gain amplification means for amplifying each of the plurality of addition signals, And output synthesizing means for adding the output signals of the variable gain amplifying means. Further, the adding means is characterized by comprising a plurality of resistance means connected in series.

  The equalizer circuit device according to the present invention eliminates the need for precise gain control and a large dynamic range in the variable gain amplifier, and an equalizer circuit capable of processing a signal in a transmission band of several hundred MHz or more is now available. There is an effect that it can be easily realized by a simple element or a manufacturing technique.

  The equalizer circuit device of the present invention is developed on the assumption that it is used for an ultrahigh-speed digital data transmission device (LAN) of several Gbps or more using a twisted pair cable or a coaxial cable. Example 1 will be described below.

FIG. 3 is a block diagram showing the configuration of the entire transmission apparatus using the equalizer circuit of the present invention. A transmission apparatus to which the present invention is applied is connected to a counterpart transmission apparatus having the same configuration through a twisted pair cable or a coaxial cable 31.
The transmission apparatus includes four full duplex transmission / reception circuits 30, a data distribution circuit 33, and a data synthesis circuit. The data distribution circuit 33 divides transmission data, for example, every 8 bits, and distributes 2 bits to each of the four full duplex transmission / reception circuits 30. In addition, the data synthesis circuit 34 restores each 2-bit data of 4 channels to the original 8-bit data. Note that, if necessary, the data distributed to the full duplex transmission / reception circuit 30 may be configured to have more than 2 bits so that error detection / correction is possible.

  FIG. 4 is a block diagram showing a configuration of the full duplex transmission / reception circuit 30. As shown in FIG. The transmission data is converted into an analog signal suitable for transmission by, for example, the OFDM system by the transmission circuit 40, amplified to a size suitable for transmission by the amplifier 41, and output to the cable 31 through the hybrid circuit 42. A part of the transmission signal generates an unnecessary signal called “echo” due to reflection at a connection point or the like existing in the cable 31. This unnecessary signal needs to be removed appropriately for accurate data transmission. The cancel signal generation circuit 47 generates a cancel signal for erasing unnecessary signals based on the transmission data.

  The reception signal from the cable 31 is separated from the transmission signal by the hybrid circuit 42 and connected to the equalizer circuit (compensation circuit) 43 of the present invention. The equalizer circuit 43 compensates for waveform deterioration due to the frequency characteristics of the cable 31 by a method described later. In the reception circuit 45, the output signal of the equalizer circuit 43 is OFDM demodulated, distortion and echo are corrected by the interference distortion correction circuit, and converted into a digital signal by the analog-digital converter. Digital signals are collectively subjected to parallel-serial conversion and evaluation signal generation processing to obtain received data and an evaluation signal.

  With respect to the timing of the above series of reception operations, a clock signal is extracted by the clock recovery circuit 46 and various timing signals are generated. The adjustment control circuit 48 incorporates a CPU and adjusts each circuit including the equalizer circuit 43 so that data can be correctly transmitted and received based on the evaluation signal.

  Here, the equalizer circuit will be described. As described in the conventional example, the equalizer circuit can be realized by a transversal filter. As a result of experiments, the inventor has found that the number of delay stages of a transversal filter as an equalizer circuit is one stage, and a plurality of one stage basic forms may be cascaded according to the required characteristics. As a basic form of the transversal filter, it has been found that a filter whose transfer function F is represented by the following formula 1 may be realized.

F = G (1-kZ ^-1 ) Equation 1

However, G = 1 / (1-k) or a value proportional to this value. In the embodiment, the output signal of the equalizer circuit is evaluated by a known method, and the equalizer circuit is adjusted by gain adjustment by a variable gain amplifier, and G is set to an optimum value by this adjustment.
k is a coefficient that varies depending on the length of the cable and the like, and depending on the length of the cable, it is necessary to adjust in a range of approximately 0.9 to 0.95. In the conventional method, when realizing this transfer characteristic, a variable gain amplifier is used to multiply the delayed signal by -k. However, the longer the cable length, the more the signal attenuates and the k value approaches 1. Therefore, the variable gain amplifier requires a low-noise amplifier that can control the gain precisely and has a wide dynamic range. It was. However, there is a problem that such a variable gain amplifier is very difficult to obtain or manufacture at a frequency of several hundred MHz or more. Accordingly, the present inventors have invented the following circuit as a circuit for realizing the above characteristics.

  FIG. 1 is a block diagram showing a configuration of an equalizer circuit according to a first embodiment of the present invention. In the circuit of FIG. 1, the + side signal processing circuit 1 and the − side signal processing circuit 2 have the same configuration. Therefore, only the upper circuit 1 will be described. The + output signal (− output signal) of the differential output signal of the hybrid circuit 42 is input to the upper (lower) circuit 1. The input signal is input to the amplifier 10 and amplified with a predetermined gain.

  The output signal (I) of the amplifier 10 is input to the adder circuit 14 and the delay line 12. The delay line 12 is a delay means for delaying the differential signal, and a coaxial cable having a predetermined length can be used. The output (D) of the delay line 12 is output to the adder circuit 15 of the other signal processing circuit 2. The adder circuit 14 receives the output signal (I) of the amplifier 10 that is the positive signal of the differential signal and the output signal (D) of the delay line 13 that is the negative delay means, and receives two signals at different ratios. An adding means for outputting a plurality of added signals obtained by adding the signals.

FIG. 2 is a functional block diagram and circuit diagram showing the configuration of the adder circuit. FIG. 2A is a functional block diagram showing the function of the adder circuit 14. The input signal I, which is the output signal of the amplifier 10 (11), is directly input to the two adders 52 and 53 (× 1.0). On the other hand, the output signal (D) of the delay line 13 (12) is inputted to two multipliers (attenuators) 50 and 51, and 0.9 times and 0.95 times signals are outputted from the respective multipliers. The two adders 52 and 53 add the outputs of the multipliers 50 and 51 and the signal I and output the result. As a result, output signals of A = (1−0.9Z ⁻¹ ) and B = (1−0.95Z ⁻¹ ) are obtained as outputs from the adder circuit 14.

FIG. 2B is a circuit diagram illustrating a configuration example of the adder circuit 14. The adder circuit 14 of the present invention can be realized by a series circuit of a plurality (three) of resistors as shown in the figure. When the input impedances of the variable gain amplifiers 16 and 17 connected to the output terminal A and the output terminal B are sufficiently large, the ratio of the resistance values of the three resistors, the resistor 54, the resistor 55, and the resistor 56 is set to 95: 2. 5: 102.5, A = [(1−0.9Z ⁻¹ ) × g ₁ ] and B = [(1−0.95Z ⁻¹⁾ ) × g ₂ ] is obtained.
The ratio of the resistance values is not limited to the above, and can be arbitrarily set within a range that can cover the adjustment range of the equalizer circuit.
Since g ₁ and g ₂ are fixed coefficients and g ₁ ≠ g ₂ , the levels of the two output signals of this circuit do not exactly coincide with each other. Since each signal level is adjusted, there is no problem.
Even when the input impedances of the variable gain amplifiers 16 and 17 connected to the output terminal A and the output terminal B are not sufficiently large, the resistance value of the resistor 54: resistor 55: resistor 56 can be designed by a known design method. Output signals corresponding to A = [(1−0.9Z ⁻¹ ) × g ₁ ] and B = [(1−0.95Z ⁻¹ ) × g ₂ ] are obtained at A and the output terminal B.

The variable gain amplifiers 16 and 17 which are variable gain amplifying means are controlled by an adjustment control circuit 48 in FIG. 4 by using a known method such as an equalizer characteristic (relative gain of each variable gain amplifier) so as to minimize the error rate of the received signal. ) Is adjusted. For example, if the gains of the variable gain amplifiers 16 and 19 are maximized and the gains of the variable gain amplifiers 17 and 18 are minimized (0), the characteristic of the filter is (1−0.9Z ⁻¹ ). If the gains of 16 to 19 are all the same (maximum), the characteristics of the filter will be approximately (1-0.925Z ^-1 ). Note that one of the variable gain amplifiers 16 and 17 may have a fixed gain, and only the other may be adjusted. An adder 20 serving as output combining means adds, combines and outputs the output signals of the two variable gain amplifiers 16 and 17.

  When processing a single-ended signal, the + signal processing circuit 1 (excluding the delay line 12) of FIG. 1, only the amplifier 11 and the delay line 13 are used, and a differential amplifier, a common mode choke transformer, etc. are used. The single-ended input signal may be converted into a differential signal and input to the + input and the − input.

  FIG. 5 is a circuit diagram illustrating a circuit example of the first embodiment. Since the upper and lower circuits are the same, only the upper circuit 1 will be described. The + input signal is input to the amplifier 61 via the DC cut capacitor 60. As the amplifier 61, for example, a monolithic amplifier IC ERA-4 manufactured by Mini-Circuits (registered trademark) can be used. Since this IC has an output impedance of 50Ω and supplies power from the output end, in this embodiment, not only the load resistor 62 (for example, 330Ω), but also the resistors 67 to 73, the resistor 64, 65, the delay line 66, and power are supplied through resistors corresponding to the resistors 67 to 73 of the adder circuit 14 in the signal processing circuit 2.

The output of the amplifier 61 is input to a resistor network that constitutes the delay line 66 and the adder circuit 14 via resistors 64 and 65 (for example, 43Ω) for signal distribution and impedance matching. For example, a coaxial cable having a predetermined characteristic impedance of 75Ω can be used as the delay line 66. Among the resistors in the resistor network, resistors corresponding to the resistors 54, 55, and 56 in FIG. 2B are resistors 67, 68, and 69 in this order. The remaining resistors 70 to 73 are resistors for impedance matching or power supply, and are not intended for addition processing.
An example of the resistance value of each resistor constituting the resistor network is shown below. Resistance 67: 138Ω, resistance 68: 2.2Ω, resistance 69: 150Ω, resistance 70: 150Ω, resistance 71: 300Ω, resistance 72: 300Ω, resistance 73: 150Ω. In this case, adjustment can be made in the range of k to 0.9 to 0.95. Capacitors 63, 74, 75, 76, 79, and 80 are DC cut capacitors, and are equivalent to those in which both ends of the capacitor are short-circuited in terms of AC.

  The two variable gain amplifiers 77 and 78 amplify the signal with a gain set from the outside (adjustment control circuit 48). As the variable gain amplifier 77, for example, AD8370 manufactured by ANALOG DEVICES (registered trademark) can be used. This IC can digitally control the gain from the outside. NEC (registered trademark) μPC2712TB can also be used. Since the gain of this IC can be adjusted by changing the power supply voltage, a power supply circuit capable of controlling the voltage is necessary to perform the adjustment.

The three resistors 81 to 83 constituting the adder 20 add and synthesize the output signals of the two variable gain amplifiers 77 and 78 and output the result.
With the above-described configuration, an equalizer circuit that can operate up to a very high frequency can be realized by using only currently available or manufacturable elements. In addition to the delay line, an IC can be formed.

  The second embodiment is an example of the equalizer circuit of the present invention when the number of output signals from the adder circuit is four. FIG. 7 is a circuit diagram showing a circuit configuration of an embodiment 2 of the equalizer circuit of the present invention. In the circuit configuration of the first embodiment, if the wide adjustment range related to the cable length is covered, the accuracy of equalization is deteriorated particularly in the region where the coefficient k is close to 1. Therefore, in the second embodiment, a region where k is close to 1 is subdivided and a plurality of outputs corresponding to each are provided, and the gain of the variable gain amplifier is controlled to synthesize them with desired characteristics.

  In the circuit diagram shown in FIG. 7, the difference from the circuit of the first embodiment shown in FIG. 5 is the configuration after the resistor network constituting the adder circuit 14, and four different output signals are output from the resistor network and are variable. Four gain amplifiers (105 to 108) are also provided.

  FIG. 6 is a circuit diagram illustrating a configuration example of an adder circuit according to the second embodiment. The circuit of the second embodiment is realized by a series circuit of five resistors as shown in the figure. These resistors correspond to the resistors 90 to 94 in FIG. 7, and the remaining resistors 95 to 100 are resistors for impedance matching or power supply, and are not intended for addition processing.

When the input impedance of the variable gain amplifier connected to the output terminals E to H is sufficiently large, the ratio of the resistance values of the five resistors described above, for example, the resistor 90: resistor 91: resistor 92: resistor 93: resistor 94 is 90: 5 : 2.5: 1.5: 101, E = [(1-0.8Z ⁻¹ ) × g ₃ ], F = [(1−0.9Z ⁻¹ ) for the four output terminals. An output signal corresponding to × g ₄ ], G = [(1−0.95Z ⁻¹ ) × g ₅ ], H = [(1−0.98Z ⁻¹ ) × g ₆ ] is obtained. Incidentally, g ₃ to g ₆ are fixed coefficient.
Even when the input impedance of the variable gain amplifier is not sufficiently large, the resistance values of the resistor 90: resistor 91: resistor 92: resistor 93: resistor 94 can be designed by a known design method, and E = [ (1−0.8Z ⁻¹ ) × g ₃ ], F = [(1−0.9Z ⁻¹ ) × g ₄ ], G = [(1−0.95Z ⁻¹ ) × g ₅ ], H = An output signal corresponding to [(1−0.98Z ⁻¹ ) × g ₆ ] is obtained.
An example of the resistance value of each resistor constituting the resistor network of FIG. 7 is shown below. Resistance 90 ... 134Ω, Resistance 91 ... 2.4Ω, Resistance 92 ... 1Ω, Resistance 93 ... 0.68Ω, Resistance 94 ... 150Ω, Resistance 95 ... 150Ω, Resistance 96 ... 300Ω, Resistance 97 ... 300Ω, Resistance 98 ... 300Ω, Resistance 99 ... 300Ω, resistance 100 ... 150Ω.

The four variable gain amplifiers 105 to 108 are controlled so that only at most two amplifiers operate at the same time. That is, when it is desired that the characteristics of the filter be about (1−0.97Z ⁻¹ ), the gain of the variable gain amplifier 107 is set to medium, the gain of the variable gain amplifier 108 is maximized, and the variable gain amplifier 105 is set. , 106 may be minimized (0). With the configuration as described above, it is possible to perform equalization with higher accuracy over a wide adjustment range.

  FIG. 8 is a block diagram illustrating a circuit configuration of the third embodiment. In the first and second embodiments, an example in which an adjustable transversal filter with one delay stage is configured is disclosed. However, the third embodiment is a configuration example when the number of delay stages is two or more (three stages). . The input signal I is delayed by delay lines 150, 151 and 152, and signals D1, D2 and D3 are output. When a negative signal is required according to the characteristics of the filter to be realized, the + signal and the − signal of the differential signal are exchanged.

  The adder circuits 153, 154, and 155 are composed of three blocks having the same configuration. The function of each block is to multiply the respective input signals by coefficients a1 to d1 by multipliers (attenuators) 160 to 163 and add them by an adder 164, respectively. As an actual circuit, a signal having desired filter characteristics corresponding to a specific cable length is synthesized and output by a resistor network.

  The three variable gain amplifiers 156 to 158 correspond to the variable gain amplifiers 16 and 17 of the first embodiment, and their respective gains are relatively controlled so as to obtain desired output characteristics. The adder 159 adds, combines and outputs the output signals of all the variable gain amplifiers. Although the third embodiment is for a single-ended signal, a differential signal circuit can be realized by making the circuit of FIG. 8 a differential configuration. At this time, the variable gain amplifiers 156 to 158 have a differential configuration.

  With such a configuration, a multi-stage equalizer circuit (transversal filter) that can operate up to a very high frequency can be realized by using only elements that can be currently obtained or manufactured.

While the embodiments have been disclosed, the following modifications are also conceivable for the present invention. In the above-described embodiment, the circuits of FIGS. 1, 5 and 7 use signals from the + input and the − input. By inserting a common mode choke transformer at the output terminals of the amplifiers 10 and 11, It is possible to remove in-phase components of noise generated on the + input side and the −input side. Thereby, it is possible to reduce the noise of the equalizer circuit.
In the embodiment, the basic form in which the number of delay stages of the transversal filter is one stage has been disclosed. However, a plurality of basic forms in one stage may be cascaded in accordance with the characteristics required for the equalizer circuit.
The equalizer circuit of the present invention can compensate distortion in transmission of a cable or the like for an arbitrary signal such as a PAM signal as well as an OFDM signal.

1 is a block diagram illustrating a configuration of an equalizer circuit according to a first embodiment of the present invention. It is a functional block diagram and a circuit diagram showing a configuration of an adder circuit. It is a block diagram which shows the structure of the whole transmission apparatus using the equalizer circuit of this invention. 2 is a block diagram showing a configuration of a full duplex transmission / reception circuit 30. FIG. FIG. 3 is a circuit diagram illustrating a circuit example of the first embodiment. FIG. 6 is a circuit diagram illustrating a configuration example of an adder circuit according to a second embodiment. It is a circuit diagram which shows the circuit structure of Example 2 of the equalizer circuit of this invention. 10 is a block diagram illustrating a circuit configuration of Embodiment 3. FIG.

Explanation of symbols

10, 11 Amplifier 12, 13 Delay line 14, 15 Adder circuit 16-19 Variable gain amplifier 20, 21 Adder

Claims (4)

Delay means for delaying one of the differential signals;
Adding means for inputting the other signal of the differential signal and the output signal of the delay means, and outputting a plurality of addition signals obtained by adding the two signals at different ratios;
A plurality of variable gain amplifying means for amplifying each of the plurality of addition signals;
An equalizer circuit device comprising: output combining means for adding the output signals of the plurality of variable gain amplifying means.   2. The equalizer circuit device according to claim 1, wherein the adding means comprises a plurality of resistance means connected in series.   2. The equalizer circuit device according to claim 1, further comprising adjusting means for adjusting gains of the plurality of variable gain amplifying means in order to compensate for frequency characteristics of the transmission line.   An equalizer circuit device comprising a plurality of the equalizer circuit devices according to claim 1 connected in cascade.

Images