JP4371071B2 - Insulating film forming jig and insulating film forming method - Google Patents

Insulating film forming jig and insulating film forming method Download PDF

Info

Publication number
JP4371071B2
JP4371071B2 JP2005084779A JP2005084779A JP4371071B2 JP 4371071 B2 JP4371071 B2 JP 4371071B2 JP 2005084779 A JP2005084779 A JP 2005084779A JP 2005084779 A JP2005084779 A JP 2005084779A JP 4371071 B2 JP4371071 B2 JP 4371071B2
Authority
JP
Japan
Prior art keywords
substrate
jig
insulating film
resist
film forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005084779A
Other languages
Japanese (ja)
Other versions
JP2006269683A (en
Inventor
隆之 広瀬
雅晴 江戸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2005084779A priority Critical patent/JP4371071B2/en
Publication of JP2006269683A publication Critical patent/JP2006269683A/en
Application granted granted Critical
Publication of JP4371071B2 publication Critical patent/JP4371071B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

この発明は、基板を真空ラミネートする際に用いる絶縁膜形成用治具および絶縁膜形成方法に関する。   The present invention relates to an insulating film forming jig and an insulating film forming method used when vacuum laminating a substrate.

半導体基板上に半導体素子が形成された半導体装置、電子部品、あるいは絶縁体基板上にコイルやコンデンサーなどの受動素子、IC(Integrated Circuit)などの半導体素子を実装した電子部品を保護するため、半導体素子表面あるいは絶縁基板に実装された素子をフィルム状の絶縁性有機材料(ドライフィルムレジスト)にて覆って保護する場合が多い。また、半導体基板表面には半導体素子の形成に伴う凹凸が存在し、厚みが数十μm以上の素子が配置された絶縁体基板上もそれらが立体構造を形成している。そのため、通常のラミネート方法では、内部に空気が入り込んでしまう。   In order to protect a semiconductor device in which a semiconductor element is formed on a semiconductor substrate, an electronic component, a passive element such as a coil or a capacitor, or an electronic component in which a semiconductor element such as an IC (Integrated Circuit) is mounted on an insulator substrate, a semiconductor In many cases, an element surface or an element mounted on an insulating substrate is covered with a film-like insulating organic material (dry film resist) for protection. Further, there are irregularities associated with the formation of the semiconductor elements on the surface of the semiconductor substrate, and they form a three-dimensional structure on the insulator substrate on which elements having a thickness of several tens of μm or more are arranged. Therefore, in a normal laminating method, air enters the inside.

そこで、空気の流入を防止する技術として、半導体基板あるいは絶縁体基板上に保護膜となるフィルム上の絶縁性有機材料(ドライフィルムレジスト)をラミネートする方法の一種として、真空ラミネータが知られている。この真空ラミネータは、真空引きによって内部に真空雰囲気を形成することができるチャンバを備えている。   Therefore, as a technique for preventing the inflow of air, a vacuum laminator is known as a kind of method for laminating an insulating organic material (dry film resist) on a film serving as a protective film on a semiconductor substrate or an insulator substrate. . This vacuum laminator includes a chamber in which a vacuum atmosphere can be formed by evacuation.

また、圧力を調整することによってチャンバ内に膨張する加熱可能な膜体を備えており、チャンバに収容できる基板とドライフィルムレジストとを一組ずつ導入してから真空引きをして膨張した膜体をドライフィルムレジストに圧着させる。   Further, the film body is provided with a heatable film body that expands in the chamber by adjusting the pressure, and is expanded by introducing a substrate and a dry film resist that can be accommodated in the chamber one by one and then evacuating the film body. Is bonded to a dry film resist.

また、真空中で基板上に合成樹皮膜を作成する技術として、強磁性を有する可撓性フィルムまたは強磁性金属膜板で作成したマスクを、基板の裏面に設けた電磁石により、基板面に密着させながら蒸発源吹き出し口より合成樹脂モノマーを重合させ、合成樹脂パターンを形成する技術が知られている(たとえば、下記特許文献1参照。)。   In addition, as a technique for creating a synthetic resin coating on a substrate in a vacuum, a mask made of a flexible film or a ferromagnetic metal membrane plate having ferromagnetism is adhered to the substrate surface by an electromagnet provided on the back surface of the substrate. A technique is known in which a synthetic resin monomer is polymerized from an evaporation source outlet while forming a synthetic resin pattern (see, for example, Patent Document 1 below).

また、導電性無機物層−絶縁層−導電性無機物層からなる積層体、または導電性無機物層−絶縁層からなる積層体にドライフィルムをラミネートしてウェットエッチングにより電子部品を製造する技術が知られている(たとえば、下記特許文献2参照。)。   Also known is a technique for laminating a dry film on a laminate comprising a conductive inorganic layer-insulating layer-conductive inorganic layer, or a laminate comprising a conductive inorganic layer-insulating layer, and manufacturing an electronic component by wet etching. (For example, see Patent Document 2 below.)

特開平5−51729号公報JP-A-5-51729 特開2003−69188号公報JP 2003-69188 A

しかしながら、上述した従来技術では、基板の外周部にレジスト材料が集中してしまい、レジストの平坦部よりも10μm以上の盛り上がりが生じてしまう。このレジストが盛り上がった部分の素子は、絶縁膜が厚いため規格外となってしまう。そのため、この外周部の盛り上がりによって、不良素子の数が増加してしまうという問題点があった。   However, in the above-described conventional technology, the resist material concentrates on the outer peripheral portion of the substrate, and the bulge is 10 μm or more than the flat portion of the resist. The element where the resist is raised becomes out of specification because the insulating film is thick. For this reason, there is a problem that the number of defective elements increases due to the rise of the outer peripheral portion.

この発明は、上述した従来技術による問題点を解消するため、真空ラミネートする際に、レジストの盛り上がりを減少させることができる絶縁膜形成用治具および絶縁膜形成方法を提供することを目的とする。   An object of the present invention is to provide an insulating film forming jig and an insulating film forming method capable of reducing the swell of a resist when vacuum laminating, in order to solve the above-described problems caused by the prior art. .

上述した課題を解決し、目的を達成するため、請求項1の発明にかかる絶縁膜形成用治具は、基板を真空ラミネートする際に用いる絶縁膜形成用治具であって、前記基板の外周の形状に対応して形成された前記基板を収容する収容部を有し、前記収容部の内周壁面の厚みは、前記基板の外周壁面の厚みよりも厚いことを特徴とする。   In order to solve the above-described problems and achieve the object, an insulating film forming jig according to the invention of claim 1 is an insulating film forming jig used when vacuum laminating a substrate, and includes an outer periphery of the substrate. And a thickness of the inner peripheral wall surface of the storage portion is greater than a thickness of the outer peripheral wall surface of the substrate.

また、請求項2の発明にかかる絶縁膜形成用治具は、請求項1に記載の発明において、前記絶縁膜形成用治具の前記内周壁面の厚みと前記基板の外周壁面の厚みの差が40〜210μmの範囲であることを特徴とする。   According to a second aspect of the present invention, there is provided the insulating film forming jig according to the first aspect, wherein the difference between the thickness of the inner peripheral wall surface of the insulating film forming jig and the outer peripheral wall surface of the substrate is the difference. Is in the range of 40 to 210 μm.

また、請求項3の発明にかかる絶縁膜形成用治具は、請求項1または2に記載の発明において、前記絶縁膜形成用治具の前記内周壁面は前記基板の外周壁面との間に所定の隙間を有して形成され、前記隙間は0.8mm以下であることを特徴とする。   According to a third aspect of the present invention, there is provided the insulating film forming jig according to the first or second aspect, wherein the inner peripheral wall surface of the insulating film forming jig is between the outer peripheral wall surface of the substrate. It is formed with a predetermined gap, and the gap is 0.8 mm or less.

上述した課題を解決し、目的を達成するため、請求項4の発明にかかる絶縁膜形成方法
は、基板に絶縁膜を形成する絶縁膜形成方法において、前記基板の外周壁面に沿って前記基板を収容する収容部を有し、前記収容部の内周壁面の厚みが前記基板の外周壁面の厚みよりも厚い絶縁膜形成用治具を設置する設置工程と、前記設置工程によって設置された前記絶縁膜形成用治具と、前記基板とを真空ラミネートするラミネート工程と、を含むことを特徴とする。
In order to solve the above-described problems and achieve the object, an insulating film forming method according to a fourth aspect of the present invention is an insulating film forming method for forming an insulating film on a substrate, wherein the substrate is disposed along an outer peripheral wall surface of the substrate. An installation step of installing an insulating film forming jig having an accommodating portion to be accommodated, wherein an inner peripheral wall surface of the accommodating portion is thicker than an outer peripheral wall surface of the substrate; and the insulation installed by the installation step And a laminating step of vacuum laminating the substrate with the film forming jig.

本発明にかかる絶縁膜形成用治具および絶縁膜形成方法によれば、基板外周部に生じるレジストの盛り上がりを減少させることができる。そのため、外周部の不良素子数が減少し、良品率を向上することができる。   According to the insulating film forming jig and the insulating film forming method of the present invention, it is possible to reduce the swell of the resist generated on the outer peripheral portion of the substrate. Therefore, the number of defective elements in the outer peripheral portion is reduced, and the yield rate can be improved.

以下に添付図面を参照して、この発明にかかる絶縁膜形成用治具および絶縁膜形成方法の好適な実施の形態を詳細に説明する。   Exemplary embodiments of an insulating film forming jig and an insulating film forming method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(実施の形態)
(絶縁膜形成用治具の構成について)
まず、この発明の実施の形態にかかる絶縁膜形成用治具と基板について説明する。図1−1は、この発明の実施の形態にかかる絶縁膜形成用治具を示す平面図である。図1−1において、基板101は略円形のシリコン基板である。このシリコン基板101は外周の一部に直線状の指標部110を有している。また、治具102は略円環状に形成された円環部120を有している。この円環部120は、所定径を有する外周壁面121と内周壁面122を有している。
(Embodiment)
(About the structure of the insulating film forming jig)
First, an insulating film forming jig and a substrate according to an embodiment of the present invention will be described. FIG. 1-1 is a plan view showing an insulating film forming jig according to an embodiment of the present invention. In FIG. 1-1, the substrate 101 is a substantially circular silicon substrate. The silicon substrate 101 has a linear indicator 110 on a part of the outer periphery. The jig 102 has an annular portion 120 formed in a substantially annular shape. The annular portion 120 has an outer peripheral wall surface 121 and an inner peripheral wall surface 122 having a predetermined diameter.

図1−2は、図1−1の側断面図である。図1−2において、内周壁面122の内径L1は、シリコン基板101の外径L2よりやや大きい径となるように形成されている。また、シリコン基板101の外周壁面101aの高さはH1であり、治具102の円環部120の内周壁面122の高さはH2である。また、シリコン基板101を治具102に収容したときに、シリコン基板101と治具102の間にはL3の幅の隙間103が形成される。   FIG. 1-2 is a side sectional view of FIG. 1-1. In FIG. 1-2, the inner diameter L1 of the inner peripheral wall surface 122 is formed to be slightly larger than the outer diameter L2 of the silicon substrate 101. Further, the height of the outer peripheral wall surface 101a of the silicon substrate 101 is H1, and the height of the inner peripheral wall surface 122 of the annular portion 120 of the jig 102 is H2. Further, when the silicon substrate 101 is accommodated in the jig 102, a gap 103 having a width L3 is formed between the silicon substrate 101 and the jig 102.

ここで、治具102の内周壁面122の高さH2は、シリコン基板101の外周壁面101aの高さH1よりも高く(H1<H2)形成されている。以下では、シリコン基板101の外周壁面の高さH1および治具102の内周壁面122の高さH2を「厚み」という。   Here, the height H2 of the inner peripheral wall surface 122 of the jig 102 is formed higher than the height H1 of the outer peripheral wall surface 101a of the silicon substrate 101 (H1 <H2). Hereinafter, the height H1 of the outer peripheral wall surface of the silicon substrate 101 and the height H2 of the inner peripheral wall surface 122 of the jig 102 are referred to as “thickness”.

(絶縁膜形成方法について)
つぎに、この発明の実施の形態にかかる治具102を用いた絶縁膜形成方法について説明する。図2は、治具を用いた絶縁膜形成方法の一例を示す説明図である。図2において、シリコン基板101と治具102の上にドライフィルムレジスト201を載せてシリコンラバー(不図示)上に設置する。
(Insulating film formation method)
Next, an insulating film forming method using the jig 102 according to the embodiment of the present invention will be described. FIG. 2 is an explanatory view showing an example of an insulating film forming method using a jig. In FIG. 2, a dry film resist 201 is placed on a silicon substrate 101 and a jig 102 and placed on a silicon rubber (not shown).

また、ドライフィルムレジスト201は、シリコン基板101の外周壁面101aの径よりも大きいものを用いる。なお、通常は、ドライフィルムレジスト201がシリコンラバーに付くのを防止するために、シリコンラバーとシリコン基板101の間にはPETフィルム202を置く。   The dry film resist 201 is larger than the diameter of the outer peripheral wall surface 101a of the silicon substrate 101. Normally, a PET film 202 is placed between the silicon rubber and the silicon substrate 101 in order to prevent the dry film resist 201 from sticking to the silicon rubber.

つぎに、この実施の形態にかかる絶縁膜形成方法の処理手順について説明する。図3は、この発明の実施の形態にかかる絶縁膜形成方法の処理手順の一部を示すフローチャートである。   Next, a processing procedure of the insulating film forming method according to this embodiment will be described. FIG. 3 is a flowchart showing a part of the processing procedure of the insulating film forming method according to the embodiment of the present invention.

図3のフローチャートにおいて、まず、シリコン基板101上に電子回路等の素子を形成する(ステップS301)。つぎに、シリコン基板101の周囲に治具102を設置し(ステップS302)、シリコン基板101を真空ラミネートする(ステップS303)。つぎに、シリコン基板101を露光して(ステップS304)、パターンを現像する(ステップS305)。そして、ポストベークをして(ステップS306)、一連の処理を終了する。このように真空ラミネートは、シリコン基板101を治具102に収容した状態でおこなわれる。また、シリコン基板101の収容に際しては、L3が一定となるようにシリコン基板101を設置することが望ましい。   In the flowchart of FIG. 3, first, an element such as an electronic circuit is formed on the silicon substrate 101 (step S301). Next, the jig | tool 102 is installed around the silicon substrate 101 (step S302), and the silicon substrate 101 is vacuum-laminated (step S303). Next, the silicon substrate 101 is exposed (step S304), and the pattern is developed (step S305). Then, post-baking is performed (step S306), and a series of processing is terminated. Thus, vacuum lamination is performed in a state where the silicon substrate 101 is accommodated in the jig 102. Further, when the silicon substrate 101 is accommodated, it is desirable to install the silicon substrate 101 so that L3 is constant.

上述した例では、シリコン基板101が円形の場合について説明したが、シリコン基板101の形は円形に限らない。治具102は、内径(幅)が基板の外径(幅)よりも大きくなっており、これにより、治具102とシリコン基板101の間に隙間103が形成されれば他の形であってもよい。   In the example described above, the case where the silicon substrate 101 is circular has been described, but the shape of the silicon substrate 101 is not limited to a circle. The jig 102 has an inner diameter (width) larger than the outer diameter (width) of the substrate, so that if the gap 103 is formed between the jig 102 and the silicon substrate 101, the jig 102 has another shape. Also good.

つぎに、この発明の絶縁膜形成方法によって形成したドライフィルムレジスト(以下、「レジスト」という。)の盛り上がりの測定結果を示す。実験例1として、シリコン基板101より厚い治具102を用いて、シリコン基板101と治具102の平均的な段差(厚みの差L4を45〜210μmとした。また、シリコン基板101と治具102の平均的な隙間103は0.25mmとした。シリコン基板101には直径100mmのシリコンウエハを用い、治具102の内径を100.5mmとした。   Next, measurement results of the swell of a dry film resist (hereinafter referred to as “resist”) formed by the insulating film forming method of the present invention are shown. As Experimental Example 1, a jig 102 thicker than the silicon substrate 101 was used, and an average step between the silicon substrate 101 and the jig 102 (thickness difference L4 was set to 45 to 210 μm. Also, the silicon substrate 101 and the jig 102 were used. The silicon substrate 101 was a silicon wafer having a diameter of 100 mm, and the inner diameter of the jig 102 was 100.5 mm.

真空ラミネート装置は、ニチゴーモートン製のダイヤフラム式を用いた。また、真空ラミネート条件は、温度100℃、圧力0.4MPa、加圧時間20秒とした。また、実験例1と比較するために比較例(1〜4)として治具102とシリコン基板101の厚みの差を変えて盛り上がり量の測定をおこなった。   The vacuum laminator used a diaphragm type made by Nichigo Morton. The vacuum lamination conditions were a temperature of 100 ° C., a pressure of 0.4 MPa, and a pressurization time of 20 seconds. Further, in order to compare with Experimental Example 1, as a comparative example (1 to 4), the difference in thickness between the jig 102 and the silicon substrate 101 was changed, and the amount of swelling was measured.

具体的には、真空ラミネートをする際に、治具102を用いずに作成したサンプルを比較例1とする。また、シリコン基板101と治具102の厚みの差L4を285μm(基板<治具)にして作成したサンプルを比較例2とする。そして、シリコン基板101と治具102の厚みの差L4を445μm(基板<治具)として作成したサンプルを比較例3とする。さらに、シリコン基板101よりも治具102を薄くして、厚みの差L4を115μm(基板>治具)として作成したサンプルを比較例4とする。   Specifically, a sample prepared without using the jig 102 when vacuum laminating is referred to as Comparative Example 1. A sample prepared by setting the difference L4 between the thicknesses of the silicon substrate 101 and the jig 102 to 285 μm (substrate <jig) is referred to as Comparative Example 2. A sample prepared by setting the difference L4 in thickness between the silicon substrate 101 and the jig 102 as 445 μm (substrate <jig) is referred to as Comparative Example 3. Further, a sample in which the jig 102 is made thinner than the silicon substrate 101 and the thickness difference L4 is 115 μm (substrate> jig) is referred to as Comparative Example 4.

以上のようにシリコン基板101と治具102との厚みの差L4を変えて、実験例1と同様の条件で真空ラミネートをおこない、レジストの盛り上がりを測定した。レジストの盛り上がりは、触針式段差計を用いて測定をおこなった。   As described above, the thickness difference L4 between the silicon substrate 101 and the jig 102 was changed, and vacuum lamination was performed under the same conditions as in Experimental Example 1, and the swell of the resist was measured. The swell of the resist was measured using a stylus profilometer.

(測定結果1)
つぎに、測定結果について説明する。図4は、治具と基板の段差と、レジストの盛り上がり量の関係について示したグラフである。図4において、縦軸が「盛り上がり量(μm)」、横軸が「基板と治具との段差(μm)」を示している。また、横軸の「基板と治具との段差(μm)」の値が負値になっている場合は、治具102の方が厚いことを示す。以下では、治具102がシリコン基板101よりも厚い場合には負値とし、またシリコン基板101が治具102よりも厚い場合には正値とする。また、縦軸の「盛り上がり量(μm)」の値が負値になっている場合は、レジストにへこみが生じた場合の値を示す。
(Measurement result 1)
Next, measurement results will be described. FIG. 4 is a graph showing the relationship between the level difference between the jig and the substrate and the resist swell amount. In FIG. 4, the vertical axis represents the “swelling amount (μm)” and the horizontal axis represents “the step between the substrate and the jig (μm)”. Further, when the value of “step (μm) between the substrate and the jig” on the horizontal axis is a negative value, it indicates that the jig 102 is thicker. In the following, when the jig 102 is thicker than the silicon substrate 101, a negative value is assumed, and when the silicon substrate 101 is thicker than the jig 102, a positive value is assumed. Further, when the value of the “swelling amount (μm)” on the vertical axis is a negative value, the value when the dent is generated in the resist is shown.

上述したように、実験例1および比較例1〜4の各サンプルについての測定結果をプロットした。なお、実験例1および各比較例1〜4について同様のサンプルを複数作成し、各サンプルについてレジストの盛り上がり量の測定をおこなった。   As above-mentioned, the measurement result about each sample of Experimental example 1 and Comparative Examples 1-4 was plotted. A plurality of similar samples were prepared for Experimental Example 1 and Comparative Examples 1 to 4, and the amount of swell of the resist was measured for each sample.

まず、実験例1の結果について説明する。実験例1の結果を符号401内に示す。実験例1では、段差を−45μm、−125μm、−210μmとして測定をおこなった。段差が−45μmの場合には、レジストの平坦面からの盛り上がり量は3μm以下となった。また、段差が−125μm、−210μmの場合には、レジストの平坦面からの盛り上がり(以下「盛り上がり」という。)は見られなかった。   First, the results of Experimental Example 1 will be described. The result of Experimental Example 1 is shown in reference numeral 401. In Experimental Example 1, measurement was performed with steps of −45 μm, −125 μm, and −210 μm. When the step was −45 μm, the amount of swell from the flat surface of the resist was 3 μm or less. In addition, when the step was −125 μm and −210 μm, no swell from the flat surface of the resist (hereinafter referred to as “swell”) was observed.

つぎに、比較例1〜4について説明する。比較例1(治具なし)では、図示は省略するが、レジスト平坦面からの盛り上がり量は、大きいもので11μm程度であった。また、比較例2(−285μm)の結果を符号402内に示す。比較例2では、レジストの盛り上がりは生じなかった。また、比較例3(−445μm)の結果を符号403内に示す。比較例3では、盛り上がりは生じなかったが、逆にへこみが生じた。へこみの値は、ばらついており、約4μmから大きいもので8μm程度のへこみが生じた。また、比較例4(+115μm)の結果を符号404に示す。比較例4では、レジスト平坦面からの盛り上がり量は大きいもので8μm程度であった。   Next, Comparative Examples 1 to 4 will be described. In Comparative Example 1 (without a jig), although not shown, the amount of swelling from the resist flat surface was about 11 μm at most. Moreover, the result of Comparative Example 2 (−285 μm) is shown in reference numeral 402. In Comparative Example 2, resist swell did not occur. The result of Comparative Example 3 (-445 μm) is indicated by reference numeral 403. In Comparative Example 3, no swell occurred, but concavity occurred. The dent values varied, with dents of about 4 μm to about 8 μm. The result of Comparative Example 4 (+115 μm) is indicated by reference numeral 404. In Comparative Example 4, the amount of bulge from the resist flat surface was about 8 μm at most.

また、基板101に絶縁膜を形成した場合に、レジストの盛り上がり量以外に、シリコン基板101の外周部に規格外となってしまう領域が、どの程度存在するかが重要となる。この規格外となる領域を示す指標として、レジストの平坦面に対するレジストの盛り上がり量が±3μm下がる位置から基板端までの距離を用いた。   In addition, when an insulating film is formed on the substrate 101, it is important how much a region outside the standard exists in the outer peripheral portion of the silicon substrate 101 in addition to the resist swell amount. As an index indicating a region outside the standard, the distance from the position where the bulge amount of the resist with respect to the flat surface of the resist decreases by ± 3 μm to the substrate edge was used.

図5は、レジストの規格外となる領域の一例を示す説明図(その1)である。図5において、レジスト表面501を太線で示す。また、レジスト表面501のうち、レジストの平坦面の高さを点線502で示す。また、h1はレジストの平坦面からレジストが最も盛り上がった位置を示している。具体的には、点線502と点線503の間の長さである。   FIG. 5 is an explanatory diagram (part 1) illustrating an example of a region that is out of resist specifications. In FIG. 5, the resist surface 501 is indicated by a thick line. In addition, the height of the resist flat surface of the resist surface 501 is indicated by a dotted line 502. Further, h1 indicates a position where the resist rises most from the flat surface of the resist. Specifically, the length is between the dotted line 502 and the dotted line 503.

また、h2は、レジストの平坦面から3μm高い位置を示している。具体的には、点線502と点線504の長さを示す。また、h3は、レジストの平坦面から3μm低い位置を示している。具体的には、点線502と点線505の長さである。   H2 indicates a position 3 μm higher than the flat surface of the resist. Specifically, the lengths of the dotted line 502 and the dotted line 504 are shown. H3 indicates a position 3 μm lower than the flat surface of the resist. Specifically, it is the length of the dotted line 502 and the dotted line 505.

また、w1は、基板端506と、レジスト表面501が3μm下がる位置507までの距離を示している。具体的には、基板端506と点線508の長さである。また、w2は、基板端506と、レジスト表面501が3μm上がる位置509までの距離を示している。具体的には、たとえば、基板端506と点線510との長さである。   Further, w1 indicates a distance from the substrate edge 506 to a position 507 where the resist surface 501 is lowered by 3 μm. Specifically, it is the length of the substrate end 506 and the dotted line 508. Further, w2 indicates the distance from the substrate edge 506 to the position 509 where the resist surface 501 rises by 3 μm. Specifically, for example, it is the length between the substrate end 506 and the dotted line 510.

図5に示したように、レジストの盛り上がりが生じる場合にも、シリコン基板101の外周部にはレジストの平坦面よりも低くなる部分が生じる。このような場合には、基板端506からレジスト表面501がレジストの平坦面よりも3μm上がる位置までが、規格外となる。具体的には、たとえば、図5においてw2の基板端506から点線510の領域が規格外である。   As shown in FIG. 5, even when the resist swells, a portion lower than the flat surface of the resist is generated on the outer peripheral portion of the silicon substrate 101. In such a case, the area from the substrate end 506 to the position where the resist surface 501 rises by 3 μm from the flat surface of the resist is out of specification. Specifically, for example, in FIG. 5, the area from the substrate end 506 of w2 to the dotted line 510 is out of specification.

図6は、レジストの規格外となる領域の一例を示す説明図(その2)である。図6において、レジスト表面501を太線で示す。図に示すように、レジストの盛り上がりが生じない場合でも、シリコン基板101の外周部にはレジストが急激に薄くなる部分が生じる。また、レジスト表面501のうち、レジストの平坦面の高さを点線601で示す。   FIG. 6 is an explanatory diagram (part 2) illustrating an example of a region outside the resist standard. In FIG. 6, the resist surface 501 is indicated by a thick line. As shown in the figure, even when resist swell does not occur, a portion where the resist is sharply thinned is formed on the outer peripheral portion of the silicon substrate 101. In addition, the height of the flat surface of the resist surface 501 is indicated by a dotted line 601.

点線602は、点線601から3μm低い位置を示す。そのためh4は3μmである。また、w3は、基板端506と、レジストの平坦面からレジスト表面501が3μm下がる位置603までの距離を示している。具体的には、基板端506と点線604との長さである。上述したように、w3に示す基板端506から点線604が規格外の領域となる。   A dotted line 602 indicates a position 3 μm lower than the dotted line 601. Therefore, h4 is 3 μm. Further, w3 indicates a distance from the substrate end 506 to a position 603 where the resist surface 501 is lowered by 3 μm from the flat surface of the resist. Specifically, it is the length between the substrate end 506 and the dotted line 604. As described above, the dotted line 604 from the substrate end 506 indicated by w3 is a nonstandard region.

(測定結果2)
図7は、基板と治具の段差と、レジストの盛り上がり量が基板端から±3μmになるまでの関係について示したグラフである。図7において、縦軸が「基板端から盛り上がり量が±3μmになるまでの距離(mm)」、横軸が「基板と治具との段差(μm)」を示している。
(Measurement result 2)
FIG. 7 is a graph showing the relationship between the step between the substrate and the jig and the rise of the resist to ± 3 μm from the substrate end. In FIG. 7, the vertical axis indicates “distance (mm) from the edge of the substrate until the swell amount becomes ± 3 μm”, and the horizontal axis indicates “step difference between the substrate and the jig (μm)”.

また、横軸の正負の関係については、図4と同様のため説明を省略する。また、基板端506から3μm下がる位置までの距離(−3μm)を菱形でプロットし、基板端506から3μm上がる位置までの距離(+3μm)を四角でプロットする。   The positive / negative relationship on the horizontal axis is the same as that in FIG. Further, the distance (−3 μm) from the substrate edge 506 to the position 3 μm lower is plotted with a rhombus, and the distance (+3 μm) from the substrate edge 506 to the position 3 μm up is plotted with a square.

図7において、符号701は実験例1の結果を示す。また、符号702は比較例2、符号703は比較例3、符号704は比較例4の結果を示す。図に示すように、治具102がシリコン基板101よりも厚い場合、シリコン基板101と治具102の段差の値の絶対値が大きくなるにしたがって、基板端506から±3μmになるまでの距離が大きくなっている。また、符号702に示す比較例2では、図4に示したように盛り上がりは生じなかったが、基板端506から3μm下がるまでの距離が大きいもので6mm程度と大きくなった。   In FIG. 7, reference numeral 701 indicates the result of Experimental Example 1. Reference numeral 702 indicates the results of Comparative Example 2, reference numeral 703 indicates the results of Comparative Example 3, and reference numeral 704 indicates the results of Comparative Example 4. As shown in the figure, when the jig 102 is thicker than the silicon substrate 101, the distance from the substrate edge 506 to ± 3 μm increases as the absolute value of the level difference between the silicon substrate 101 and the jig 102 increases. It is getting bigger. Further, in Comparative Example 2 indicated by reference numeral 702, the bulge did not occur as shown in FIG. 4, but the distance from the substrate edge 506 to the 3 μm drop was large, which was about 6 mm.

また、符号703に示す比較例3では、基板端506から3μm下がるまでの距離が6mm以上となった。また、符号704に示す比較例4では、基板端506から3μm上がるまでの距離が6mm以上と大きくなった。また、比較例4では、菱形と四角の双方がプロットされている。これは、レジストに盛り上がりが生じ、また、シリコン基板101の外周部ではレジストの平坦面よりも低くなる部分が生じたためである。   Moreover, in the comparative example 3 shown with the code | symbol 703, the distance until it falls 3 micrometers from the board | substrate edge 506 became 6 mm or more. Moreover, in the comparative example 4 shown by the code | symbol 704, the distance from the board | substrate edge 506 to 3 micrometers rise became large with 6 mm or more. Moreover, in the comparative example 4, both the rhombus and the square are plotted. This is because the resist is swelled and a portion of the outer peripheral portion of the silicon substrate 101 is lower than the flat surface of the resist.

以上説明したように、真空ラミネートをする際に、シリコン基板101の周囲に治具102を設置することによって、レジストの盛り上がりを減少させることができる。また、治具102はシリコン基板101よりも厚いものを用いた方が効果的である。さらに、シリコン基板101と治具102の段差を40〜210μmの範囲とすることで、レジストの盛り上がりを3μm以下にすることができ、レジストの盛り上がりが基板端506から3μm下がるまでの距離を3.5mm以下とすることができる。   As described above, when vacuum lamination is performed, the rising of the resist can be reduced by installing the jig 102 around the silicon substrate 101. It is more effective to use a jig 102 thicker than the silicon substrate 101. Furthermore, by setting the level difference between the silicon substrate 101 and the jig 102 in the range of 40 to 210 μm, the resist swell can be reduced to 3 μm or less, and the distance until the resist swell rises from the substrate edge 506 by 3 μm is 3. It can be 5 mm or less.

つぎに、シリコン基板101と治具102間の平均的な隙間を変化させてサンプルの作成をおこなった。真空ラミネートの条件は、実験例1と同様の条件でおこなった。また、シリコン基板101よりも厚い治具102を用い、その段差を125μmとした。   Next, a sample was prepared by changing an average gap between the silicon substrate 101 and the jig 102. The vacuum lamination was performed under the same conditions as in Experimental Example 1. Further, a jig 102 thicker than the silicon substrate 101 was used, and the step was set to 125 μm.

(測定結果1)
図8は、実験例2にかかる治具とシリコン基板の段差と、レジストの盛り上がり量の関係について示したグラフである。図8において、縦軸が「盛り上がり量(μm)」、横軸が「基板と治具の平均隙間(mm)」を示している。また、縦軸の正負の関係については、図4の場合と同様のため説明を省略する。
(Measurement result 1)
FIG. 8 is a graph showing the relationship between the step between the jig and the silicon substrate according to Experimental Example 2 and the swell amount of the resist. In FIG. 8, the vertical axis indicates “swelling amount (μm)” and the horizontal axis indicates “average gap (mm) between substrate and jig”. The positive / negative relationship on the vertical axis is the same as in FIG.

つぎに、実験例2の結果について説明する。符号801は平均隙間が0mmの場合、符号802は平均隙間が約0.25mmの場合、符号803は平均隙間が約0.5mmの場合、符号804は平均隙間が約0.75mmの場合の結果である。図に示すように、シリコン基板101と治具102間の平均隙間が0.5mm以下(符号801,802、803)では、レジストの盛り上がりは生じなかった。また、符号804に示すように、シリコン基板101と治具102間の平均隙間が0.75mmの場合には、盛り上がりが生じ、その値は大きいもので4μm程度であった。   Next, the results of Experimental Example 2 will be described. Reference numeral 801 is the result when the average gap is 0 mm, reference numeral 802 is the average gap is about 0.25 mm, reference numeral 803 is the average gap is about 0.5 mm, and reference numeral 804 is the result when the average gap is about 0.75 mm. It is. As shown in the figure, when the average gap between the silicon substrate 101 and the jig 102 is 0.5 mm or less (reference numerals 801, 802, 803), the resist does not rise. Further, as indicated by reference numeral 804, when the average gap between the silicon substrate 101 and the jig 102 is 0.75 mm, swell occurs, and the value is as large as about 4 μm.

(測定結果2)
図9は、実施例2にかかる基板と治具間の平均隙間と、レジストの盛り上がり量が基板端から±3μmになるまでの関係について示したグラフである。図9において、縦軸が「基板端から盛り上がり量が±3μmになるまでの距離(mm)」、横軸が「基板と治具の平均隙間(mm)」を示している。プロットについては、図7の場合と同様のため説明を省略する。
(Measurement result 2)
FIG. 9 is a graph showing the relationship between the average gap between the substrate and the jig according to Example 2 and the rise of the resist to ± 3 μm from the substrate edge. In FIG. 9, the vertical axis indicates “the distance (mm) from the end of the substrate until the rising amount becomes ± 3 μm”, and the horizontal axis indicates “the average gap (mm) between the substrate and the jig”. The plot is the same as in FIG.

図9において、符号901は平均隙間が0mmの場合、符号902は平均隙間が約0.25mmの場合、符号903は平均隙間が約0.5mmの場合、符号904は平均隙間が約0.75mmの場合の結果である。図8で示したように、平均隙間が0.75mmの場合(符号804)には、盛り上がり量は4μmとなったが、基板端506から±3μmになるまでの距離は3.5mm以下(符号904)となった。以上示したように、シリコン基板101と治具102の平均隙間を0.8mm以下にすることによって、ドライフィルムレジスト201のシリコン基板101外周部の盛り上がり量を減少させることができる。   In FIG. 9, reference numeral 901 is an average gap of 0 mm, reference numeral 902 is an average gap of about 0.25 mm, reference numeral 903 is an average gap of about 0.5 mm, and reference numeral 904 is an average gap of about 0.75 mm. Is the result of. As shown in FIG. 8, when the average gap is 0.75 mm (reference numeral 804), the bulge amount is 4 μm, but the distance from the substrate edge 506 to ± 3 μm is 3.5 mm or less (reference numeral 904). As described above, by setting the average gap between the silicon substrate 101 and the jig 102 to 0.8 mm or less, it is possible to reduce the rising amount of the outer peripheral portion of the dry film resist 201 on the silicon substrate 101.

以上説明したように、絶縁膜形成用治具および絶縁膜形成方法によれば、真空ラミネートする際に、シリコン基板101の周囲に治具102を設置し、治具102をシリコン基板101の厚みより厚くすることにより、基板外周部に生じるレジストの盛り上がりを減少させることができる。   As described above, according to the insulating film forming jig and the insulating film forming method, when vacuum laminating, the jig 102 is installed around the silicon substrate 101, and the jig 102 is made larger than the thickness of the silicon substrate 101. By increasing the thickness, it is possible to reduce the swell of the resist generated on the outer periphery of the substrate.

上述した実施の形態では、シリコン基板101上に保護膜としてドライフィルムレジスト201を真空ラミネートする方法を説明したが、シリコン基板101の代わりに絶縁体基板を用いてもよい。絶縁体基板を用いて、真空ラミネートにより絶縁膜を形成してもレジストの盛り上がりを減少させることができる。   In the above-described embodiment, the method of vacuum laminating the dry film resist 201 as a protective film on the silicon substrate 101 has been described. However, an insulator substrate may be used instead of the silicon substrate 101. Even if an insulating film is formed by vacuum lamination using an insulating substrate, the resist swell can be reduced.

また、半導体基板、絶縁体基板の形状についても、円形の形態について上述したが、形状は円形に限らず方形の基板についても適用可能である。方形の基板を用いる場合、方形の基板の外周より一回り大きく厚さの厚い治具を用いることにより同様にレジストの盛り上がりを減少させることができる。   In addition, the shape of the semiconductor substrate and the insulator substrate has been described above with respect to the circular form, but the shape is not limited to the circular shape, and can be applied to a rectangular substrate. In the case of using a square substrate, the rise of the resist can be similarly reduced by using a jig that is slightly thicker than the outer periphery of the square substrate.

以上のように、本発明にかかる絶縁膜形成用治具および絶縁膜形成方法は、半導体装置または電子部品の製造に有用であり、特に真空ラミネートによる絶縁膜形成装置に適している。   As described above, the jig for forming an insulating film and the method for forming an insulating film according to the present invention are useful for manufacturing a semiconductor device or an electronic component, and are particularly suitable for an insulating film forming apparatus using vacuum lamination.

この実施の形態にかかる絶縁膜形成用治具を示す平面図である。It is a top view which shows the jig | tool for insulating film formation concerning this embodiment. 図1−1の側断面図である。It is a sectional side view of Drawing 1-1. 治具を用いた絶縁膜形成方法の一例を示す説明図である。It is explanatory drawing which shows an example of the insulating film formation method using a jig | tool. この発明の実施の形態にかかる絶縁膜形成方法の処理手順の一部を示すフローチャートである。It is a flowchart which shows a part of process procedure of the insulating film formation method concerning embodiment of this invention. 治具と基板の段差と、レジストの盛り上がり量の関係について示したグラフである。It is the graph shown about the level | step difference of a jig | tool and a board | substrate, and the relationship of the amount of swelling of a resist. レジストの規格外となる領域の一例を示す説明図(その1)である。It is explanatory drawing (the 1) which shows an example of the area | region which becomes a resist outside specification. レジストの規格外となる領域の一例を示す説明図(その2)である。It is explanatory drawing (the 2) which shows an example of the area | region which becomes a resist outside specification. 基板と治具の段差と、レジストの盛り上がり量が基板端から±3μmになるまでの関係について示したグラフである。It is the graph which showed about the level | step difference of a board | substrate and a jig | tool, and the relationship until the swelling amount of a resist becomes +/- 3micrometer from the board | substrate edge. 実験例2にかかる治具とシリコン基板の段差と、レジストの盛り上がり量の関係について示したグラフである。It is the graph shown about the relationship between the jig | tool concerning Experimental example 2, the level | step difference of a silicon substrate, and the amount of swelling of a resist. 実施例2にかかる基板と治具間の平均隙間と、レジストの盛り上がり量が基板端から±3μmになるまでの関係について示したグラフである。It is the graph shown about the average clearance gap between the board | substrate concerning a Example 2, and the relationship until the swelling amount of a resist becomes +/- 3micrometer from the board | substrate end.

符号の説明Explanation of symbols

101 シリコン基板
101a シリコン基板の外周壁面
102 治具
103 隙間
120 円環部
121 外周壁面
122 内周壁面
201 ドライフィルムレジスト
202 PETフィルム

DESCRIPTION OF SYMBOLS 101 Silicon substrate 101a The outer peripheral wall surface of a silicon substrate 102 Jig 103 Crevice 120 Annular part 121 Outer peripheral wall surface 122 Inner peripheral wall surface 201 Dry film resist 202 PET film

Claims (4)

基板を真空ラミネートする際に用いる絶縁膜形成用治具であって、
前記基板の外周の形状に対応して形成された前記基板を収容する収容部を有し、
前記収容部の内周壁面の厚みは、前記基板の外周壁面の厚みよりも厚いことを特徴とする絶縁膜形成用治具。
An insulating film forming jig used when vacuum laminating a substrate,
An accommodating portion for accommodating the substrate formed corresponding to the shape of the outer periphery of the substrate;
An insulating film forming jig , wherein the inner peripheral wall surface of the housing portion is thicker than the outer peripheral wall surface of the substrate .
前記絶縁膜形成用治具の前記内周壁面の厚みと前記基板の外周壁面の厚みの差が40〜210μmの範囲であることを特徴とする請求項1に記載の絶縁膜形成用治具。2. The insulating film forming jig according to claim 1, wherein a difference between a thickness of the inner peripheral wall surface of the insulating film forming jig and a thickness of the outer peripheral wall surface of the substrate is in a range of 40 to 210 μm. 前記絶縁膜形成用治具の前記内周壁面は前記基板の外周壁面との間に所定の隙間を有して形成され、前記隙間は0.8mm以下であることを特徴とする請求項1または2に記載の絶縁膜形成用治具。The inner peripheral wall surface of the jig for forming an insulating film is formed with a predetermined gap between the outer peripheral wall surface of the substrate and the gap is 0.8 mm or less. 2. A jig for forming an insulating film according to 2. 基板に絶縁膜を形成する絶縁膜形成方法において、In an insulating film forming method for forming an insulating film on a substrate,
前記基板の外周壁面に沿って前記基板を収容する収容部を有し、前記収容部の内周壁面の厚みが前記基板の外周壁面の厚みよりも厚い絶縁膜形成用治具を設置する設置工程と、An installation step of installing a jig for forming an insulating film having a housing portion for housing the substrate along an outer peripheral wall surface of the substrate, wherein an inner peripheral wall surface of the housing portion is thicker than an outer peripheral wall surface of the substrate. When,
前記設置工程によって設置された前記絶縁膜形成用治具と、前記基板とを真空ラミネートするラミネート工程と、Laminating step of vacuum laminating the insulating film forming jig installed by the installation step and the substrate;
を含むことを特徴とする絶縁膜形成方法。An insulating film forming method comprising:
JP2005084779A 2005-03-23 2005-03-23 Insulating film forming jig and insulating film forming method Expired - Fee Related JP4371071B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005084779A JP4371071B2 (en) 2005-03-23 2005-03-23 Insulating film forming jig and insulating film forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005084779A JP4371071B2 (en) 2005-03-23 2005-03-23 Insulating film forming jig and insulating film forming method

Publications (2)

Publication Number Publication Date
JP2006269683A JP2006269683A (en) 2006-10-05
JP4371071B2 true JP4371071B2 (en) 2009-11-25

Family

ID=37205334

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005084779A Expired - Fee Related JP4371071B2 (en) 2005-03-23 2005-03-23 Insulating film forming jig and insulating film forming method

Country Status (1)

Country Link
JP (1) JP4371071B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10303229A (en) * 1997-04-24 1998-11-13 Mitsui High Tec Inc Covering of semiconductor device with solder resist
JP3494100B2 (en) * 2000-01-11 2004-02-03 富士通株式会社 Semiconductor device and method of mounting the same
JP4108285B2 (en) * 2000-12-15 2008-06-25 イビデン株式会社 Manufacturing method of multilayer printed wiring board
JP3896017B2 (en) * 2001-08-03 2007-03-22 松下電器産業株式会社 Semiconductor mounting body manufacturing method and semiconductor mounting body manufacturing apparatus

Also Published As

Publication number Publication date
JP2006269683A (en) 2006-10-05

Similar Documents

Publication Publication Date Title
JP4971321B2 (en) Method for protecting a bonding layer of a substrate support adapted for use in a plasma processing system
CN106711184B (en) Display panel manufacturing method, display panel and display device
KR100876273B1 (en) Thin film device and thin film device having thin film pattern on the surface and manufacturing method thereof
TW200931172A (en) Apparatus and method for mounting pellicle
US9761794B2 (en) Magnetoresistive sensor, related manufacturing method, and related electronic device
JP4288133B2 (en) Wafer suction stage and wafer suction method
US20210013415A1 (en) Vapor deposition mask, frame-equipped vapor deposition mask, vapor deposition mask preparation body, method of manufacturing vapor deposition mask, method of manufacturing organic semiconductor element, method of manufacturing organic el display, and method of forming pattern
JP4371071B2 (en) Insulating film forming jig and insulating film forming method
JP6376871B2 (en) Contact exposure system
US6802222B2 (en) Diaphragm-type semiconductor device and method for manufacturing diaphragm-type semiconductor device
US11130671B2 (en) MEMS device and fabrication method thereof
JP4451213B2 (en) Display substrate
US7504330B2 (en) Method of forming an insulative film
KR20080046582A (en) Method and structure of pattern mask for dry etching
US20130330929A1 (en) Seal member, etching apparatus, and a method of manufacturing a semiconductor device
US7987727B2 (en) Semiconductor pressure sensor and fabrication method thereof
IL273198A (en) Bond materials with enhanced plasma resistant characteristics and associated methods
US9806034B1 (en) Semiconductor device with protected sidewalls and methods of manufacturing thereof
JP6873879B2 (en) Sensor element and its manufacturing method
US10033005B2 (en) Stretchable substrate, electronic apparatus having the stretchable substrate, and method of manufacturing the electronic apparatus
US6627466B1 (en) Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer
US20100112820A1 (en) Method for membrane protection during reactive ion/plasma etching processing for via or cavity formation in semiconductor manufacture
US8815333B2 (en) Manufacturing method of metal structure in multi-layer substrate
JP6882850B2 (en) Stress sensor
JP2017181435A (en) Stress sensor

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20070726

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070810

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20070918

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090514

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090519

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090721

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090811

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090824

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4371071

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120911

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130911

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees