JPH10303229A - Covering of semiconductor device with solder resist - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for covering a semiconductor device with solder resist so as to prevent deformation of the semiconductor device and failure of solder resist formation, at a process of forming solder resist on a plurality of semiconductor devices. SOLUTION: A plurality of semiconductor devices 20 are fit-inserted in openings on a plate 100, and placed on a mesh support platen 101. In this state, the plate 100 is set in a lamination device, and a vacuum lamination process is performed. By this arrangement, existence of a dry film 10 between the respective semiconductor devices 20 can be prevented, and further, bubbles remaining between the dry film 10 and the semiconductor devices 20 can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solder resist coating method for a semiconductor device, and more particularly, to a solder resist for a semiconductor device in which a gap between a plurality of semiconductor devices is filled to prevent a dry film from getting into the gap. It relates to a coating method.

[0002]

2. Description of the Related Art In a semiconductor device, especially in a chip size package, a wiring pattern formed on the semiconductor device is coated with a solder resist in a manufacturing process of the semiconductor device for insulation or protection to the outside. You.

[0003] This coating is usually performed by a vacuum lamination method, and a plurality of semiconductor devices are simultaneously processed. The outline of the conventional vacuum lamination method will be described below.

In the vacuum laminating method, first, a plurality of semiconductor devices to be processed are placed on a laminating device via a polyethylene film, and the semiconductor devices are covered with a dry film and housed in the laminating device. here,
The laminating device is composed of a sealing device and a vacuum pump. After the pressure in the sealing device is once reduced by a vacuum pump, the semiconductor device is brought into close contact with the dry film by releasing the air to the atmosphere again, and a wiring pattern of the semiconductor device is formed. A solder resist is formed on the formation surface.

Thereafter, the polyethylene film is removed from each semiconductor device to obtain individual semiconductor devices on which a solder resist is formed. Here, the polyethylene film prevents sticking of the dry film to the laminating device.

[0006]

However, in the conventional vacuum laminating method as described above, the state of coating after the laminating process is such that the dry film 10 enters the gap between the semiconductor devices 20 as shown in FIG. Had been in a state.

For this reason, the dry film 10 applies a downward tension to each semiconductor device 20, deforms the TAB tape 21 and the leads 23 constituting the semiconductor device 20, and breaks the dry film 10 due to the corners of the leads 23. Problem had arisen.

Further, air that has lost its escape during lamination processing remains as air bubbles A between the dry film 10 and the polyethylene film 11, resulting in defective solder resist.

Accordingly, an object of the present invention is to provide a solder resist coating method which does not cause the above problems.

[0010]

According to a first aspect of the present invention, there is provided a method for coating a solder resist on a semiconductor device by forming a solder resist on the semiconductor device by vacuum lamination. A step of inserting the semiconductor device into the opening of a plate having one or a plurality of openings and occupying at least a part of a peripheral edge of the semiconductor device by the plate;

According to a second aspect of the present invention, in the first aspect of the invention, the vacuum laminating is performed by placing the plate on a support, and the support has a plurality of ventilation holes. Is provided.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a method for coating a solder resist on a semiconductor device according to the present invention will be described below in detail with reference to the accompanying drawings.

In the present invention, as shown in FIG. 1, a plurality of semiconductor devices 20 are inserted into a plate 100 with their wiring pattern forming surfaces exposed, thereby filling gaps between the semiconductor devices. Mesh support 10
1 is placed in a laminating apparatus in a state where the dry film 10 is placed in the gap between the semiconductor devices 20 and the air bubbles remaining between the dry film 10 and each semiconductor device 20 by vacuum laminating. To prevent.

Here, as shown in FIG. 2, the plate 100 is provided with a plurality of openings H corresponding to the shape of the semiconductor device 20, and is configured so that the plurality of semiconductor devices 20 are fitted into the openings H. ing. The thickness of the plate 100 is determined according to the height of the semiconductor device and a desired covering area such that only the surface of the fitted semiconductor device is exposed to the outside. Also, in the figure, a plurality of openings H are provided in the plate 100 so that a plurality of semiconductor devices having a chip size can be processed at the same time. When applied to a semiconductor device, only one opening H corresponding to the semiconductor device may be provided.

As shown in FIG. 3, the mesh-like support base 101 is provided with a plurality of air holes through which air can pass.
Further, it is made of a material (for example, Teflon) to which the dry film 10 is not easily stuck. It is preferable that the air holes have such a size that the dry film 10 does not enter the air holes.

The steps of coating a semiconductor device with a solder resist by implementing the present invention having the above-described features will be described in more detail with reference to FIGS. here,
4 to 6 show the Z section in FIG.

As shown in FIGS. 1 and 4, the laminating apparatus used in the present embodiment includes an upper platen 1 and a lower platen 2 which constitute the outer wall of a sealer, and a dry film 10 which is reduced under reduced pressure to a semiconductor device 20. The upper rubber 3 and the lower rubber 4 serving as a support base for making close contact with each other, an O-ring 5 for sealing the air in the sealer from the outside, a vacuum pump 7 for lowering the air pressure in the sealer, and a vacuum pump 7 It is composed of a ventilation path A8 for passing air to be drawn in, and a ventilation path B9 for passing air drawn in or opened by the vacuum pump 7.

Here, the upper rubber 3 is fixed to the bottom surface of the upper platen 1, the ventilation path A8 is provided inside the side wall of the lower platen 2, and the ventilation path B9 is provided at the center of the lower platen 2.
The lower rubber 4 is placed so as to close the ventilation path B9.

When the semiconductor device 20 is accommodated in the laminating apparatus configured as described above, first, the plate 100 is placed on the lower rubber 4 via the mesh-like support 101, and the plate 100 The semiconductor device 20 is inserted into the opening H so that the wiring pattern formation surface is exposed.

After the semiconductor device 20 is housed in the lower platen 2 as described above, the dry film 10 is covered so as to cover the semiconductor device, and the upper platen 1 and the upper rubber 3 are covered from above. Thus, the semiconductor device 20 is hermetically sealed in a sealer including the upper platen 1 and the lower platen 2.

Next, the vacuum pump 7 is operated, and the air passage A
Air in the sealer is drawn in through the air passage 8 and the ventilation path B9, and the pressure in the sealer is reduced. This retraction is performed for 60 seconds as shown in FIG. 7, and the air pressure in the sealer is 760 mmHg.
To 1 mmHg.

Next, the air is released from the air passage B9, and the lower rubber 4 is expanded. This opening is performed as shown in FIG.
Done for seconds. As shown in FIG. 6, the lower rubber 4 is expanded by releasing air from the air passage B9 to create a high-pressure space between the lower rubber 4 and the central portion of the lower platen 2, thereby allowing air to flow from the air passage A8. By drawing in, a space having a low air pressure is created between the lower rubber 4 and the side wall of the lower platen 2 and the upper platen 1. As a result, the semiconductor device is pressed against the upper rubber 3 and the dry film 10
Adhere to

At this time, since the gap between the semiconductor devices is filled with the plate 100, the dry film 10 is exposed from each opening of the semiconductor device 2 through the opening of the plate 100.
0, only the wiring pattern forming surface is covered, and each semiconductor device 2
0 (for example, a semiconductor chip mounting portion). As a result, the conventional dry film 1
The tension in the downward direction due to 0 is reduced, and deformation of the leads and the like constituting the semiconductor device 20 is prevented. Further, since the mesh-like support 101 efficiently releases air between each semiconductor device and the dry film 10, no bubbles remain.

As described above, the pull-in time is 60 seconds,
The laminating process of the semiconductor device is completed through a process of a total of 85 seconds including a lower rubber expansion time of 25 seconds.

[0025]

As described above, according to the present invention,
It is possible to prevent the dry film from entering into the gap between the semiconductor devices during the laminating process, and to prevent air bubbles from remaining between each semiconductor device and the dry film.

[Brief description of the drawings]

FIG. 1 is a three-dimensional view schematically showing a method for coating a solder resist on a semiconductor device according to the present invention.

FIG. 2 is a three-dimensional view showing the structure of a plate.

FIG. 3 is a three-dimensional view showing the structure of a mesh-like support base.

FIG. 4 is a cross-sectional view illustrating a process of housing the semiconductor device in vacuum lamination processing.

FIG. 5 is a Z sectional view showing a dry film adhesion step in vacuum lamination processing.

FIG. 6 is a Z sectional view showing a lower rubber expansion process in vacuum lamination.

FIG. 7 is a time chart of vacuum lamination processing.

FIG. 8 is a cross-sectional view showing a solder resist covered state by a conventional vacuum lamination method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper platen 2 Lower platen 3 Upper rubber 4 Lower rubber 5 O-ring 7 Vacuum pump 8 Airway A 9 Airway B 10 Dry film 11 Polyethylene film 20 Semiconductor device 21 TAB tape or lead frame 22 Semiconductor chip 23 Lead 100 Plate 101 Mesh Support

Claims (2)

[Claims] 1. A method for coating a solder resist on a semiconductor device by forming a solder resist on the semiconductor device by vacuum laminating, wherein the vacuum laminating includes placing the semiconductor device in the opening of a plate having one or more openings. Inset,
A method for coating a semiconductor device with a solder resist, wherein the method is performed in a state where at least a part of the periphery of the semiconductor device is occupied by the plate. 2. The semiconductor device according to claim 1, wherein the vacuum laminating is performed by placing the plate on a support, and the support has a plurality of ventilation holes. Solder resist coating method.