JP4370156B2 - Video signal output circuit - Google Patents

Video signal output circuit Download PDF

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JP4370156B2
JP4370156B2 JP2003417456A JP2003417456A JP4370156B2 JP 4370156 B2 JP4370156 B2 JP 4370156B2 JP 2003417456 A JP2003417456 A JP 2003417456A JP 2003417456 A JP2003417456 A JP 2003417456A JP 4370156 B2 JP4370156 B2 JP 4370156B2
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video signal
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output
capacitor
resistor
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桂子 宮嶋
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New Japan Radio Co Ltd
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本発明は、出力映像信号のサグを補正する機能も併せ持つ映像信号出力回路に関するものである。   The present invention relates to a video signal output circuit having a function of correcting a sag of an output video signal.

従来の映像信号出力回路の構成を図３に示す。図３において、１は入力端子、２は出力バッファ（ドライバ）、３は出力端子である。Ｃ２は映像信号のＡＣ成分のみを抽出するために出力バッファ２の出力側に外付け接続された容量（第１の容量）であり、この容量Ｃ２と負荷抵抗Ｒ４（後段回路の入力インピーダンス：第１の抵抗）とによりハイパスフィルタが構成される。このため、出力映像信号から容量Ｃ２により直流成分が除去されるために、入力端子１に図４(a)に示す映像信号を入力させると、図４(b)に示すように、出力端子３に現れる映像信号が積分波形となり頂部が傾斜したいわゆるサグが発生する。なお、図４(a)において、１１は映像信号期間（２５６H期間）、１２は帰線期間、１３は水平同期信号部を示す。   The configuration of a conventional video signal output circuit is shown in FIG. In FIG. 3, 1 is an input terminal, 2 is an output buffer (driver), and 3 is an output terminal. C2 is a capacitor (first capacitor) externally connected to the output side of the output buffer 2 in order to extract only the AC component of the video signal. This capacitor C2 and the load resistor R4 (input impedance of the subsequent circuit: first impedance) 1 resistor) constitutes a high-pass filter. For this reason, since the DC component is removed from the output video signal by the capacitor C2, when the video signal shown in FIG. 4 (a) is input to the input terminal 1, the output terminal 3 as shown in FIG. 4 (b). The so-called sag in which the top part is inclined is generated by the video signal appearing in the waveform becomes an integrated waveform. In FIG. 4A, 11 is a video signal period (256H period), 12 is a blanking period, and 13 is a horizontal synchronizing signal section.

そこで、このサグの発生を防止するために、通常では映像信号出力回路にサグ補正回路が組み込まれる。図５はそのサグ補正回路を組み込んだ映像信号出力回路の構成を示す回路図である。サグ補正回路は、出力バッファ２の反転入力端子と外付け容量Ｃ２の負荷抵抗Ｒ４の側との間に外付け容量Ｃ３を接続し、さらに出力バッファ２の出力端子と反転入力端子との間に出力バッファ２の出力インピーダンスＺｏよりも抵抗値の十分大きな抵抗Ｒ５を接続して構成されている。   In order to prevent the occurrence of this sag, a sag correction circuit is usually incorporated in the video signal output circuit. FIG. 5 is a circuit diagram showing a configuration of a video signal output circuit incorporating the sag correction circuit. The sag correction circuit connects an external capacitor C3 between the inverting input terminal of the output buffer 2 and the load resistor R4 side of the external capacitor C2, and further, between the output terminal and the inverting input terminal of the output buffer 2. A resistor R5 having a resistance value sufficiently larger than the output impedance Zo of the output buffer 2 is connected.

このサグ補正回路では、容量Ｃ２と負荷抵抗Ｒ４により構成されるハイパスフィルタを通過した信号を、容量Ｃ３を通過して出力バッファ２の反転入力端子に帰還させることにより、サグが補正される。   In this sag correction circuit, the sag is corrected by returning the signal that has passed through the high-pass filter composed of the capacitor C2 and the load resistor R4 to the inverting input terminal of the output buffer 2 through the capacitor C3.

TOKO 半導体セレクションガイド、集積回路、3.3V動作クランプ回路内蔵７５ΩビデオラインドライバIC、「TK15460L」、[平成15年12月10日検索]、インターネット＜URL：http://www.toko.co.jp/products/ctlg/semicon/av_video.html＞TOKO Semiconductor Selection Guide, Integrated Circuit, 75Ω Video Line Driver IC with Built-in 3.3V Operation Clamp Circuit, “TK15460L”, [Searched on December 10, 2003], Internet <URL: http://www.toko.co.jp /products/ctlg/semicon/av_video.html>

しかしながら、上記図５に示したサグ補正回路では、輝度信号およびクロマ信号の周波数帯域では抵抗Ｒ５、容量Ｃ２、Ｃ３で構成されたループのインピーダンスを十分小さくしなければならないが、抵抗Ｒ５はゲイン確保の関係から前記したように出力バッファ２の出力インピーダンスＺｏよりも十分大きな抵抗値に設定しなければならないので、外付けの容量Ｃ２、Ｃ３の容量値を大きくしなければならず、その容量Ｃ２，Ｃ３が大型化するという問題があった。   However, in the sag correction circuit shown in FIG. 5, the impedance of the loop composed of the resistor R5 and the capacitors C2 and C3 must be made sufficiently small in the frequency band of the luminance signal and the chroma signal, but the resistor R5 ensures the gain. As described above, since the resistance value must be set sufficiently larger than the output impedance Zo of the output buffer 2, the capacitance values of the external capacitors C2 and C3 must be increased. There was a problem that C3 increased in size.

本発明の目的は、サグ補正が行われ且つＡＣ成分抽出用およびサグ補正用の外付け容量を小さくできるようにした映像信号出力回路を提供することである。   An object of the present invention is to provide a video signal output circuit in which sag correction is performed and an external capacity for AC component extraction and sag correction can be reduced.

請求項１にかかる発明の映像信号出力回路は、映像信号を入力する出力バッファと、該出力バッファと出力端子との間に接続された第１の容量と、該出力端子と接地間に接続される第１の抵抗とを具備する映像信号出力回路において、入力端子に一方の入力側が接続された加算回路と、該加算回路の出力側と前記出力バッファの入力側に接続された増幅器と、第２の容量と第２の抵抗とからなり前記増幅器の出力側と前記加算回路の他方の入力側との間に接続されたローパスフィルタとを設け、前記増幅器の出力信号の一部を前記ローパスフィルタおよび前記加算回路を介して前記増幅器に帰還し、前記第１の容量と前記第１の抵抗により生成されるサグを補正することを特徴とする。 The video signal output circuit of the invention according to claim 1 is connected to an output buffer for inputting a video signal, a first capacitor connected between the output buffer and the output terminal, and the output terminal to ground. And an amplifier connected to the output side of the adder circuit and the input side of the output buffer; and a first resistor connected to the input terminal. A low-pass filter comprising a capacitor of 2 and a second resistor and connected between the output side of the amplifier and the other input side of the adder circuit, and a part of the output signal of the amplifier is provided in the low-pass filter And feedback to the amplifier via the adder circuit to correct a sag generated by the first capacitor and the first resistor .

請求項２にかかる発明は、請求項１に記載の映像信号出力回路において、前記第２の容量と前記第２の抵抗とで決まるローパスフィルタのカットオフ周波数を、前記第１の容量と前記第１の抵抗とで決まるハイパスフィルタのカットオフ周波数と同じに設定したことを特徴とする。   According to a second aspect of the present invention, in the video signal output circuit according to the first aspect, a cutoff frequency of a low-pass filter determined by the second capacitor and the second resistor is set to the first capacitor and the first capacitor. It is characterized in that it is set to be the same as the cut-off frequency of the high-pass filter determined by the resistance of 1.

請求項３にかかる発明は、請求項１又は２に記載の映像信号出力回路において、前記加算回路の前記他方の入力側にクランプ回路を接続したことを特徴とする。   The invention according to claim 3 is the video signal output circuit according to claim 1 or 2, wherein a clamp circuit is connected to the other input side of the adder circuit.

請求項１および２にかかる発明によれば、ＡＣ成分抽出用の第１の容量と第１の抵抗からなるハイパスフィルタにより映像信号の頂部に生じるサグの傾斜と反対の傾斜を、第２の容量と第２の抵抗からなるローパスフィルタにより予め映像信号に与えるので、そのサグを補正することができる。このとき、第１の容量はＡＣ抽出としての機能を満足すればよいので、小さな容量値に設定できる。また、第２の容量と第２の抵抗からなるローパスフィルタのカットオフ周波数は、第１の容量と第１の抵抗からなるハイパスフィルタのカットオフ周波数と同じに設定すればよいので、第２の抵抗を大きな値に設定することで第２の容量の容量値を小さく設定できる。よって、第１および第２の容量のいずれもその容量値を小さな値に設定でき、小型化が可能となり外付けの場合に好適となる。   According to the first and second aspects of the present invention, a slope opposite to the slope of the sag generated at the top of the video signal by the high-pass filter including the first capacitor for extracting the AC component and the first resistor is set as the second capacitor. Since the image signal is given in advance by a low-pass filter composed of the second resistor, the sag can be corrected. At this time, since the first capacitor only needs to satisfy the function of AC extraction, it can be set to a small capacitance value. Further, the cutoff frequency of the low-pass filter composed of the second capacitor and the second resistor may be set to be the same as the cutoff frequency of the high-pass filter composed of the first capacitor and the first resistor. The capacitance value of the second capacitor can be set small by setting the resistance to a large value. Therefore, both the first and second capacitors can be set to a small capacitance value, and can be reduced in size, which is suitable for an external case.

また、請求項３にかかる発明によれば、第２の容量と第２の抵抗からなるローパスフィルタの出力電圧をクランプ回路でクランプできるので、サグ補正回路を構成する増幅器に入力する信号のバイアスを所望の電圧値に固定できるため、低電圧動作が可能となる利点がある。   According to the invention of claim 3, since the output voltage of the low-pass filter comprising the second capacitor and the second resistor can be clamped by the clamp circuit, the bias of the signal input to the amplifier constituting the sag correction circuit can be reduced. Since it can be fixed to a desired voltage value, there is an advantage that low voltage operation is possible.

図１は本発明の１つの実施例の映像信号出力回路の構成を示す回路図である。図３および図５におけるものと同じものには同じ符号を付けた。４は出力バッファ２の入力側に接続された増幅器、５はその増幅器４と入力端子１との間に接続された抵抗Ｒ１，Ｒ２からなる加算回路、６は増幅器４の出力側と加算回路５との間に接続された抵抗Ｒ３（第２の抵抗）と容量Ｃ１（第２の容量）からなるローパスフィルタ、７はノードｃの電圧をクランプするクランプ回路である。   FIG. 1 is a circuit diagram showing a configuration of a video signal output circuit according to one embodiment of the present invention. The same components as those in FIGS. 3 and 5 are denoted by the same reference numerals. 4 is an amplifier connected to the input side of the output buffer 2, 5 is an adding circuit comprising resistors R 1 and R 2 connected between the amplifier 4 and the input terminal 1, and 6 is an output side of the amplifier 4 and an adding circuit 5. A low-pass filter composed of a resistor R3 (second resistor) and a capacitor C1 (second capacitor) connected between and a clamp circuit for clamping the voltage at the node c.

この映像信号出力回路では、入力端子１に入力された映像信号は、抵抗Ｒ１を経由して増幅器４で増幅され、出力バッファ２に入力すると共にローパスフィルタ６に入力する。入力端子１（ノードａ）の映像信号を図２(a)に、ローパスフィルタ６のノードｃの映像信号を図２(c)に示す。このようにノードｃの映像信号は、増幅器４の出力映像信号からローパスフィルタ６によりDC成分のみが抽出された波形となる。よって、このノードｃの信号をノードａの入力映像信号に加算回路５で加算することにより、増幅器４の入力側のノードｂの映像信号は、図２(b)に示すように、前記した図４に示した波形と反対に頂部が傾斜した波形の信号となる。よって、この信号を増幅器４で増幅して出力バッファ２から出力端子３の方向に出力させれば、容量Ｃ３と負荷抵抗Ｒ４によるハイパスフィルタ（図４(b)に示すようにサグを生じる）によりその頂部の傾斜が逆方向の傾きに修正されて、出力端子３（ノードｄ）には、図２(d)に示すように、サグが補正された映像信号が出力する。   In this video signal output circuit, the video signal input to the input terminal 1 is amplified by the amplifier 4 via the resistor R 1, input to the output buffer 2 and input to the low-pass filter 6. The video signal at the input terminal 1 (node a) is shown in FIG. 2 (a), and the video signal at node c of the low-pass filter 6 is shown in FIG. 2 (c). Thus, the video signal of the node c has a waveform in which only the DC component is extracted from the output video signal of the amplifier 4 by the low-pass filter 6. Therefore, by adding the signal of the node c to the input video signal of the node a by the adder circuit 5, the video signal of the node b on the input side of the amplifier 4 is as shown in FIG. 2 (b). On the contrary to the waveform shown in FIG. Therefore, if this signal is amplified by the amplifier 4 and output from the output buffer 2 toward the output terminal 3, a high-pass filter (causing sag as shown in FIG. 4B) by the capacitor C3 and the load resistor R4. The inclination of the top is corrected to a reverse inclination, and a video signal with the sag corrected is output to the output terminal 3 (node d) as shown in FIG. 2 (d).

ここで、容量Ｃ２と負荷抵抗Ｒ４で構成されたハイパスフィルタのカットオフ周波数と容量Ｃ１と抵抗Ｒ３で構成されたローパスフィルタ６のカットオフ周波数が同一となるようにそれらの定数を設定すれば、サグを精度高く補正することができる。   If these constants are set so that the cut-off frequency of the high-pass filter composed of the capacitor C2 and the load resistor R4 and the cut-off frequency of the low-pass filter 6 composed of the capacitor C1 and the resistor R3 are the same, Sag can be corrected with high accuracy.

このとき、容量Ｃ２はＡＣ抽出としての機能を満足すればよいので、小さな容量値に設定できる。また、容量Ｃ１と抵抗Ｒ３からなるローパスフィルタ６のカットオフ周波数は、容量Ｃ２と負荷抵抗Ｒ４からなるハイパスフィルタのカットオフ周波数と同じに設定すればよいので、抵抗Ｒ３を大きな値に設定することで容量Ｃ１の容量値を小さく設定できる。よって、容量Ｃ１，Ｃ２のいずれもその容量値を小さな値に設定でき、小型化が可能となり外付けの場合に好適となる。   At this time, since the capacitor C2 only needs to satisfy the function of AC extraction, it can be set to a small capacitance value. Further, since the cut-off frequency of the low-pass filter 6 composed of the capacitor C1 and the resistor R3 may be set to be the same as the cut-off frequency of the high-pass filter composed of the capacitor C2 and the load resistor R4, the resistor R3 is set to a large value. The capacitance value of the capacitor C1 can be set small. Therefore, the capacitance values of both capacitors C1 and C2 can be set to a small value, which can be reduced in size and is suitable for an external case.

一方、前記したクランプ回路７により、ノードｃの信号（図２(c)）の最低レベルを所望の電圧値にクランプさせることにより、ノードｂの信号（図２(b)）の信号の振幅を小さな範囲内に抑え、ＡＰＬ（平均映像レベル）の変動に対する影響を緩和することができるので、増幅器４に要求されたダイナミックレンジを小さくすることができる。よって、電源電圧を低くすることができ、低電圧化が可能となる。   On the other hand, the clamp circuit 7 clamps the lowest level of the signal at the node c (FIG. 2C) to a desired voltage value, so that the amplitude of the signal at the node b (FIG. 2B) is increased. Since the influence on the variation of APL (average video level) can be mitigated within a small range, the dynamic range required for the amplifier 4 can be reduced. Therefore, the power supply voltage can be lowered and the voltage can be lowered.

本発明の実施例の映像信号出力回路の回路図である。It is a circuit diagram of the video signal output circuit of the Example of this invention. (a)〜(d)は図１のノードａ〜ｄの信号波形図である。(a)-(d) is a signal waveform diagram of nodes a-d in FIG. 従来の映像信号出力回路の回路図である。It is a circuit diagram of a conventional video signal output circuit. (a)、(b)は図３の映像信号出力回路のノードａ，ｂの信号波形図である。(a), (b) is a signal waveform diagram of nodes a and b of the video signal output circuit of FIG. サグ補正回路を組み込んだ従来の映像信号出力回路の回路図である。It is a circuit diagram of the conventional video signal output circuit incorporating a sag correction circuit.

符号の説明Explanation of symbols

Ｃ２：容量（第１の容量）
Ｒ４：負荷抵抗（第１の抵抗）
Ｃ１：容量（第２の容量）
Ｒ３：抵抗（第２の抵抗）
１：入力端子
２：出力バッファ
３：出力端子
４：増幅器
５：加算回路
６：ローパスフィルタ
７：クランプ回路 C2: Capacity (first capacity)
R4: Load resistance (first resistance)
C1: Capacity (second capacity)
R3: Resistance (second resistance)
1: Input terminal 2: Output buffer 3: Output terminal 4: Amplifier 5: Adder circuit 6: Low pass filter 7: Clamp circuit

Claims (3)

映像信号を入力する出力バッファと、該出力バッファと出力端子との間に接続された第１の容量と、該出力端子と接地間に接続される第１の抵抗とを具備する映像信号出力回路において、
入力端子に一方の入力側が接続された加算回路と、該加算回路の出力側と前記出力バッファの入力側に接続された増幅器と、第２の容量と第２の抵抗とからなり前記増幅器の出力側と前記加算回路の他方の入力側との間に接続されたローパスフィルタとを設け、
前記増幅器の出力信号の一部を前記ローパスフィルタおよび前記加算回路を介して前記増幅器に帰還し、前記第１の容量と前記第１の抵抗により生成されるサグを補正することを特徴とする映像信号出力回路。 A video signal output circuit comprising an output buffer for inputting a video signal, a first capacitor connected between the output buffer and the output terminal, and a first resistor connected between the output terminal and the ground In
An adder circuit having one input side connected to the input terminal, an amplifier connected to the output side of the adder circuit and the input side of the output buffer, a second capacitor and a second resistor, and the output of the amplifier A low-pass filter connected between the side and the other input side of the adder circuit ;
A part of an output signal of the amplifier is fed back to the amplifier via the low-pass filter and the addition circuit, and a sag generated by the first capacitor and the first resistor is corrected. Signal output circuit. 請求項１に記載の映像信号出力回路において、
前記第２の容量と前記第２の抵抗とで決まるローパスフィルタのカットオフ周波数を、前記第１の容量と前記第１の抵抗とで決まるハイパスフィルタのカットオフ周波数と同じに設定したことを特徴とする映像信号出力回路。 The video signal output circuit according to claim 1.
The cut-off frequency of the low-pass filter determined by the second capacitor and the second resistor is set to be the same as the cut-off frequency of the high-pass filter determined by the first capacitor and the first resistor. A video signal output circuit. 請求項１又は２に記載の映像信号出力回路において、
前記加算回路の前記他方の入力側にクランプ回路を接続したことを特徴とする映像信号出力回路。 The video signal output circuit according to claim 1 or 2,
A video signal output circuit, wherein a clamp circuit is connected to the other input side of the adder circuit.
JP2003417456A 2003-12-16 2003-12-16 Video signal output circuit Expired - Fee Related JP4370156B2 (en)

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WO2008069228A1 (en) * 2006-12-08 2008-06-12 Panasonic Corporation Video signal output circuit and semiconductor integrated circuit having same
JP5088099B2 (en) 2007-11-07 2012-12-05 ミツミ電機株式会社 Video signal amplifier circuit and semiconductor integrated circuit for amplification
JP5113503B2 (en) * 2007-12-06 2013-01-09 新日本無線株式会社 Video output circuit
JP5169861B2 (en) * 2009-01-19 2013-03-27 ミツミ電機株式会社 Semiconductor integrated circuit, video signal output circuit
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