JP4358187B2 - 放射線に耐性のある、スタティックramのフィールドプログラマブルゲートアレイにおける誤りの検出と訂正の方法及び装置 - Google Patents
放射線に耐性のある、スタティックramのフィールドプログラマブルゲートアレイにおける誤りの検出と訂正の方法及び装置 Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
- G11C11/4125—Cells incorporating circuit means for protecting against loss of information
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/17764—Structural details of configuration resources for reliability
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/1778—Structural details for adapting physical parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
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- Quality & Reliability (AREA)
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Description
312…EPROM制御ブロック
313…信号ライン
314…行計数器
316…FPGAコア
318…放射線に耐性のある読み取り/書き込み増幅器及び誤り訂正符号回路
320…放射線に耐性のあるシフトレジスタ
324…2入力マルチプレクサ
326…周期的冗長検査回路(CRC)
328…読み取り/書き込み増幅器
330…列計数器
332…制御論理回路
Claims (9)
- 論理モジュールと、
前記論理モジュールに結合される配線資源と、
前記論理モジュールと前記配線資源とを制御する構成データを持った構成データラインと、
前記構成データラインに結合される誤り訂正回路と
を備え、
前記誤り訂正回路は、前記構成データの複数回の読み取りに対して前記構成データ内の誤りを分析し、複数の分析結果からの多数決論理回路の決定に基づく訂正を行うことを特徴とする放射線に耐性のあるプログラマブル論理素子。 - 前記誤り訂正回路は、さらに、
放射線に耐性のある読み取り/書き込み増幅器と、
前記放射線に耐性のある読み取り/書き込み増幅器に結合される、放射線に耐性のあるシフトレジスタと
を備えることを特徴とする請求項1記載の放射線に耐性のあるプログラマブル論理素子。 - 前記誤り訂正回路は、さらに、
前記放射線に耐性のある読み取り/書き込み増幅器と前記構成データラインとの間で結合される多数決ブロックを備えることを特徴とする請求項2記載の放射線に耐性のあるプログラマブル論理素子。 - 前記誤り訂正回路は、さらに、Qcritあるいはより大きな衝突に十分耐えられる大きさの少なくとも1つのトランジスタを持った複数のラッチを備え、前記ラッチは、前記多数決ブロックに結合されることを特徴とする請求項3記載の放射線に耐性のあるプログラマブル論理素子。
- 前記誤り訂正回路は、さらに、
各々が複数の入力と1つの出力とを持った、複数の電子的符号訂正(ECC)ラッチと、
1つの入力と複数の出力とを持った第1マルチプレクサと、
前記複数のECCラッチの少なくとも1つの出力に結合され、また前記マルチプレクサの前記出力の少なくとも1つに結合される入力を持ち、2入力マルチプレクサの第1入力に結合される出力を持った多数決論理回路と、
前記第1マルチプレクサの前記複数の出力の1つに結合され、前記2入力マルチプレクサの第2入力に結合される1つの出力を持つ放射線に耐性のあるシフトレジスタと、
前記2入力マルチプレクサの出力に結合される1つの入力を持った書き込みラッチと、
前記書き込みラッチの出力と、前記第1マルチプレクサの複数の出力の少なくとも1つとに結合される1つの入力を持った読み取り及び書き込み増幅器と
を備えることを特徴とする請求項1記載の放射線に耐性のあるプログラマブル論理素子。 - 前記多数決回路は、さらに
3つの2入力ANDゲートと、
前記3つの2入力ANDゲートの各々の出力に結合される入力を持った3入力ANDゲートと
を備えることを特徴とする請求項5記載の放射線に耐性のあるプログラマブル論理素子。 - 前記読み取り及び書き込み増幅器は、さらに、
複数の入力と複数の出力とを持った書き込み増幅器回路と、
前記書き込み増幅器の前記入力に結合され、複数の出力を持ったプリチャージ回路と、
前記書き込み増幅器回路の前記出力と、前記プリチャージ回路の前記出力とに結合される入力を持ち、1つの出力を持つセンス回路と
を備えることを特徴とする請求項5記載の放射線に耐性のあるプログラマブル論理素子。 - 前記ECCラッチは、さらに、
前記ECCラッチへの入力を作る第1ノードに結合されるソースと、第2ノードに結合されるドレインと、論理モジュール信号ラインに結合されるゲートとを持った、第1公称寸法の第1トランジスタと、
前記第1ノードに結合されるソースと、前記第2ノードに結合されるドレインと、反転された論理モジュール信号ラインに結合されるゲートとを持った公称寸法の第2トランジスタと、
前記第2ノードに結合される第1入力と、リセット信号ラインに結合される第2入力とを持った第1の2入力NANDゲートと、
第1の2入力NANDゲートの出力に結合される第1入力と、一組の信号ラインに結合される第2入力とを持ち、前記ECCラッチの出力への出力を持った第2の2入力NANDゲートと、
第3ノードに結合されるソースと、第4ノードに結合されるドレインと、第2論理モジュール信号ラインに結合されるゲートとを持った、より大きな第2の大きさの第3トランジスタと、
前記第3ノードに結合されるソースと、前記第4ノードに結合されるドレインと、反転された第2論理モジュール信号ラインに結合されるゲートとを持った、より大きな第2の大きさの第4トランジスタと
を備え、
前記第3ノードは、前記第2の2入力NANDゲートの前記出力に結合され、前記第4ノードは、前記第1の2入力NANDゲートの前記第1入力に結合されることを特徴とする請求項5記載の放射線に耐性のあるプログラマブル論理素子。 - プログラマブル論理素子をプログラムするための構成データを持ったプログラマブル論理素子内の誤り訂正の方法において、
構成データのバックグラウンド読み取り段階と、
誤りのための前記構成データを分析する段階と、
もし誤りが見付かれば、前記構成データを訂正する段階と、
もし誤りが見付かれば、前記構成データを書き換える段階と
を備え、
前記構成データのバックグラウンド読み取り段階は、複数回繰り返され、
誤りのための前記構成データを分析する前記段階は、前記複数回読み取られた構成データそれぞれに対する分析結果を用いて、多数決論理回路で実践されることを特徴とする方法。
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US10/335,234 US6838899B2 (en) | 2002-12-30 | 2002-12-30 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array |
PCT/US2003/041359 WO2005067147A1 (en) | 2002-12-30 | 2003-12-23 | Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array |
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JP2006519511A JP2006519511A (ja) | 2006-08-24 |
JP4358187B2 true JP4358187B2 (ja) | 2009-11-04 |
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US (6) | US6838899B2 (ja) |
EP (2) | EP1584138B1 (ja) |
JP (1) | JP4358187B2 (ja) |
AU (1) | AU2003304697A1 (ja) |
DE (1) | DE60329628D1 (ja) |
WO (1) | WO2005067147A1 (ja) |
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US20060145722A1 (en) | 2006-07-06 |
DE60329628D1 (de) | 2009-11-19 |
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