JP4358041B2 - Control device, information processing device, control method, power saving control program, and recording medium - Google Patents

Description

  The present invention relates to a control device that is connected to an arithmetic processing device and a storage unit and controls power saving in the storage unit, an information processing device including the control device, a control method in the control device, and a saving executed by the control device. The present invention relates to a power control program and a recording medium.

  Conventionally, for example, in an information processing apparatus such as a personal computer (PC), an external memory such as a DRAM (Dynamic Random Access Memory) provided outside a CPU (Central Processing Unit) is reduced in power consumption. Has been proposed.

  Here, some CPUs are provided with a high-speed and small-capacity memory called a cache. In this case, the CPU performs each process by appropriately using the cache and the external memory. For example, the CPU normally rewrites only the cache and reflects the rewritten contents of the cache in the external memory as necessary. Perform back control.

  As an example of an information processing apparatus equipped with a CPU that performs such a write-back control, a program necessary for resuming is loaded in advance in the CPU cache, and a check is made that the external memory can be used when returning. There has been proposed an information processing apparatus capable of suppressing power consumption by performing processing using a program written in a cache instead of external hardware (see Patent Document 1).

The electronic device described in Patent Document 2 includes a data storage unit that stores data and a DRAM that is a cache memory of the data storage unit in an electronic device having a sleep function that shifts to a low power consumption mode. If the data to be read is present in the DRAM when the reading of data from the data storage unit is requested when the sleep function is valid, the data is read out from the DRAM. Further, only the data is stored in the data storage unit and the DRAM, and a flash memory for storing various programs is further provided.
JP 11-272347 A (publication date October 8, 1999) JP 2003-186579 A (publication date July 4, 2003)

  However, although the information processing apparatus described in Patent Document 1 stops power supply to the external memory or the like at the time of resume, access to the external memory is required when the CPU performs processing. For this reason, when shifting from the resume time to the normal processing operation time, it is necessary to supply power to the external memory again. As described above, since the power supply stop period to the external memory is only during resumption, there is a problem that power consumption cannot be sufficiently reduced.

  Further, the technique described in Patent Document 1 requires a CPU having a built-in cache memory and provided with a special control circuit for performing processing in the cache memory. Therefore, a commercially available general-purpose CPU cannot be used.

  On the other hand, in the electronic device described in Patent Document 2, since the flash memory storing various programs is necessary when returning from the low power consumption mode, the power consumption required for the flash memory cannot be reduced. In addition, since the data temporarily stored in the second storage means is data read from the first storage means at the normal time before the shift to the low power consumption mode, it is used when the next recovery is performed. It is not necessarily the data that is created If there is no free space in the second storage means, the data in the second storage means is cleared. Therefore, when shifting from the low power consumption mode to the normal time, there is a problem that the frequency of returning the first storage means is high, and the power consumption cannot be sufficiently reduced.

  The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a control device, an information processing device, a general-purpose CPU, and a power saving effect that can be improved as compared with the conventional one. An information processing apparatus control method, a power saving control program, and a recording medium are provided.

  In order to solve the above problems, a control device according to the present invention is connected to an arithmetic processing device and a first storage unit that stores a program and data. When the arithmetic processing device performs processing, the arithmetic processing device Is connected to a second storage unit having a smaller capacity than the first storage unit, and the first storage unit can normally read at least stored contents. A first power switching means for switching to a state or a power saving state that consumes less power than the normal state, and before the first power switching means switches the first storage unit from the normal state to the power saving state, Copying means for copying a predetermined part of the program and data stored in one storage unit to the second storage unit; and the arithmetic processing unit when the first storage unit is in a power saving state. There when processing, as long as the program and data used for the process is copied by said copying means, characterized by comprising an access control means for accessing said processor in the second storage unit.

  In order to solve the above problems, a control method according to the present invention is connected to an arithmetic processing unit, a first storage unit that stores a program and data, and a second storage unit that has a smaller capacity than the first storage unit. And a control method in the control device for switching the first storage unit between a normal state in which at least stored contents can be read and a power saving state in which the power consumption is smaller than the normal state, wherein the first storage unit Before switching from the normal state to the power saving state, a predetermined part of the program and data stored in the first storage unit is copied to the second storage unit, and the first storage unit saves power. When the arithmetic processing unit performs processing in a state, if the program and data used for the processing are copied, the arithmetic processing unit is made to access the second storage unit. .

  According to the above configuration or method, before the first storage unit switches from the normal state to the power saving state, a part of the program and data stored in the first storage unit is copied to the second storage unit. . When the arithmetic processing unit performs processing when the first storage unit is in the power saving state, if the program and data used for the processing are copied, the arithmetic processing unit is made to access the second storage unit. Thereby, when the arithmetic processing unit wants to access the copied program and data, it is not necessary to restore the first storage unit from the power saving state, and the second storage unit has a smaller capacity and lower power consumption than the first storage unit. Processing can be executed only by the storage unit.

  A predetermined program and data are copied. Accordingly, by setting in advance as a copy of a program that is frequently started when the first storage unit is in the power saving state and data necessary for the program, the arithmetic processing unit can be used only by the second storage unit. Processing can be executed, and the frequency with which the first storage unit returns from the power saving state to the normal state can be further reduced. Therefore, power consumption can be reduced. Further, since it is not necessary to provide a special cache memory as described in Patent Document 1 in the arithmetic processing device, there is an effect that a general-purpose arithmetic processing device (for example, a CPU) can be used.

  Further, in addition to the above configuration, the control device according to the present invention may be configured such that, after the first power switching unit returns the first storage unit from the power saving state to the normal state, the copying unit includes the second storage unit. The program and data stored in the storage unit are copied again to the storage area of the first storage unit that is the copy source when the first storage unit is copied before the first storage unit is switched from the normal state to the power saving state.

  According to the above configuration, the copying unit copies the program and data copied to the second storage unit to the original storage area of the first storage unit when the first storage unit returns from the power saving state. fix. Therefore, when the first storage unit is in the power saving state, the program and data including the latest information when the arithmetic processing device accesses the second storage unit are copied to the first storage unit. As a result, after the first storage unit returns to the normal state, the arithmetic processing unit can execute processing with the program and data including the latest information by accessing the first storage unit. In addition, in a state where the first storage unit is restored to the normal state, the arithmetic processing device executes processing by accessing the first storage unit, and therefore the second storage unit can be used for other purposes. There is an effect that can be done.

  Furthermore, in addition to the above-described configuration, the control device according to the present invention is provided with an address for designating the storage area in the storage areas of the first storage unit and the second storage unit. An address receiving means for receiving an access destination address for designating an access destination storage area from the processing device, and an address for designating a copy source storage area for the program and data copied by the copying means, for designating the copy destination storage area Address conversion means for converting into an address, wherein the access control means causes the address conversion means to convert the access destination address received by the address receiving means when the first storage unit is in a power saving state, The arithmetic processing unit is made to access a storage area specified by the converted address.

  According to the above configuration, when the first storage unit is in the power saving state, the access destination address received by the address receiving unit is converted by the address converting unit.

  For example, consider a case where the copying means transfers the program P from the address A of the first storage unit to the address B of the second storage unit. In this case, the address conversion unit converts the address A as the access destination address into the address B when the first storage unit is in the power saving state. Therefore, when the address A is designated as the access destination from the arithmetic processing device when the first storage unit is in the power saving state, the access control means causes the arithmetic processing device to access the address B. Thus, from the viewpoint of the arithmetic processing unit, the program and data copied to the second storage unit can be accessed by designating the address of the first storage unit. Therefore, the arithmetic processing unit has an effect that it is not necessary to change the access destination address depending on whether or not the first storage unit is in the power saving state.

  Furthermore, in addition to the above-described configuration, the control device according to the present invention is characterized in that the copying means copies a program and data according to a direct memory access method.

  According to the above configuration, since the program and data are copied between the first storage unit and the second storage unit by the direct memory access method, it is necessary to perform processing for executing the copy by the arithmetic processing unit. Disappears. As a result, the load on the arithmetic processing unit can be reduced.

  Furthermore, in addition to the above configuration, the control device according to the present invention is provided with an address for specifying the storage area in the storage area of the first storage unit and the second storage unit, and the copy The means designates a copy source address and a copy destination address, and copies the program and data according to the direct memory access method. The copy means transfers the program and data from the second storage unit to the first storage unit. In the case of copying, an address conversion means for exchanging the copy source address and the copy destination address designated by the copy means is provided.

  According to the above configuration, the copying unit specifies the copy source address and the copy destination address, and copies the program and data according to the direct memory access method. Further, the address conversion means replaces the copy source address and the copy destination address designated by the copy means when the copy means copies the program and data from the second storage section to the first storage section.

  Here, for example, it is assumed that the program P is stored at the address A of the first storage unit. Before changing the first storage unit from the normal state to the power saving state, the direct memory access type copying means uses the address A of the first storage unit as the copy source address and the address B of the second storage unit as the copy destination address. And the program P stored at the address A is copied to the address B.

  On the other hand, when the first storage unit is returned from the power saving state to the normal state, the direct memory access type copying means copies the program P from the address B of the second storage unit to the address A of the first storage unit. At this time, the address conversion unit exchanges the copy source address and the copy destination address designated by the copy unit. Therefore, when the copying means designates address A as a copy source address and designates address B as a copy destination address, the copy source is actually address B and the copy destination is address A and is stored in address B. Program P is copied to address A.

  As described above, the direct memory access type copying means copies the predetermined program and data from the first storage unit to the second storage unit, and stores the program and data from the second storage unit to the first storage unit. The desired copy can be performed with the same setting (in the above case, the address A is designated as the copy source address and the address B is designated as the copy destination address). This produces an effect that the copying program in the copying means can be simplified.

  Furthermore, in addition to the above-described configuration, the control device according to the present invention sets the second storage unit to a normal state in which at least stored contents can be read, or to a power saving state in which power consumption is smaller than the normal state. A second power switching unit for switching, wherein the second power switching unit sets the second storage unit in a power saving state after the copying unit copies the program and data from the first storage unit to the second storage unit; Thereafter, the second storage unit is brought into a normal state when the arithmetic processing unit performs processing.

  According to the above configuration, the second storage unit can be set in the power saving state after the first storage unit is set in the power saving state until the next time the arithmetic processing unit performs processing, and further power saving is achieved. There is an effect that can be achieved.

  Furthermore, in addition to the above configuration, the control device according to the present invention further includes an access switching unit that switches whether the arithmetic processing unit can access the second storage unit, and the access switching unit includes at least a first switch. When one storage unit is in a power saving state, the arithmetic processing device can access the second storage unit.

  According to the above configuration, the arithmetic processing device can access the second storage unit while the first storage unit is in the power saving state. When the first storage unit is not in the power saving state, access from the arithmetic processing unit to the second storage unit can be disabled, and the second storage unit is used as a storage unit dedicated to devices other than the arithmetic processing unit. There is an effect that can be done.

  In order to solve the above-described problem, an information processing apparatus according to the present invention includes an arithmetic processing device, a first storage unit that stores a program and data, and a second storage having a smaller capacity than the first storage unit. And a control device according to any one of claims 1 to 7.

  According to the above configuration, when the arithmetic processing unit performs processing when the first storage unit is in the power saving state, if the program and data used for the processing are copied by the copying unit, the arithmetic processing unit is The second storage unit is accessed. Thus, when the arithmetic processing device accesses the copied program and data, it is not necessary to restore the first storage unit from the power saving state, and the second storage unit has a smaller capacity and lower power consumption than the first storage unit. Processing can be executed only by the storage unit.

  Further, the program and data to be copied are a predetermined part of the program and data stored in the first storage unit. Therefore, the copying means copies the same program and data. Therefore, the CPU sets the first storage unit from the power saving state by presetting a program that starts frequently when the first storage unit is in the power saving state and data necessary for the program. The frequency with which the processing is executed only by the second storage unit without returning is increased. Therefore, power consumption can be reduced. Further, since it is not necessary to provide a special cache memory in the arithmetic processing unit, there is an effect that a general-purpose arithmetic processing unit (for example, CPU) can be used.

  Each unit in the control device can be executed on a computer by a control program. Furthermore, the control program can be executed on any computer by storing the control program in a computer-readable recording medium.

  As described above, the control device according to the present invention is connected to the second storage unit having a smaller capacity than the first storage unit, and the first storage unit is in a normal state in which at least stored contents can be read out. A first power switching unit that switches between a power saving state that consumes less power than the normal state, and the first memory before the first power switching unit switches the first storage unit from the normal state to the power saving state. Copying means for copying a predetermined part of the program and data stored in the storage unit to the second storage unit, and the arithmetic processing unit performs processing when the first storage unit is in a power saving state. When performing, if the program and data used for the processing are copied by the copying unit, the processing unit includes an access control unit for accessing the second storage unit.

  Therefore, when the arithmetic processing unit wants to access the copied program and data, there is no need to restore the first storage unit from the power saving state, and the second storage unit has a smaller capacity and lower power consumption than the first storage unit. Processing can be executed only by the storage unit.

  A predetermined program and data are copied. Accordingly, by setting in advance as a copy of a program that is frequently started when the first storage unit is in the power saving state and data necessary for the program, the arithmetic processing unit can be used only by the second storage unit. Processing can be executed, and the frequency with which the first storage unit returns from the power saving state to the normal state can be further reduced. Therefore, power consumption can be reduced. Further, since it is not necessary to provide a special cache memory as described in Patent Document 1 in the arithmetic processing device, there is an effect that a general-purpose arithmetic processing device (for example, a CPU) can be used.

  In the following embodiments, an information processing apparatus (here, a printer controller) provided in a printer which is an example of an electronic apparatus will be described as an example. However, the information processing apparatus according to the present invention is not limited to the printer controller. The present invention relates to an information processing apparatus generally provided in electronic devices such as PCs, AV devices, and control devices, that is, a CPU, a main memory for storing various programs representing operation procedures in the CPU, and data used in the programs, and a main memory The present invention can be applied to any information processing apparatus having a sub memory independent of the above.

Embodiment 1
An embodiment of an information processing apparatus and a control apparatus according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram illustrating the configuration of a printer controller (information processing apparatus) 1 according to the present embodiment and the relationship between a printer 2 including the printer controller 1 and a personal computer 3.

  As shown in FIG. 1, the personal computer 3 and the printer 2 are connected by a communication network 4 such as a LAN (local area network). The personal computer 3 transmits various instructions and data to the printer 2. For example, when the printer 2 performs print output, the personal computer 3 outputs printer language data representing a document to be printed and the print output request to the printer 2. Further, the personal computer 3 outputs to the printer 2 a status notification request for inquiring whether or not the printer 2 is usable (a request for instructing notification of whether or not the printer 2 can operate normally).

  The printer 2 includes a printer controller 1 and a printer engine 5.

  The printer controller 1 receives printer language data sent from the personal computer 3 via the communication network 4, converts it into print output data (bitmap data, etc.), and sends it to the printer engine 5. In response to a status notification request from the computer 3, various processes such as status notification processing for notifying the personal computer 3 of the status of the printer 2 are performed. In addition, the printer controller 1 has a steady state mode in which predetermined power is supplied to each block for performing a normal processing operation, and a low power consumption state in which the power consumption is reduced as compared with the steady state mode. Mode. The state of each block in the low power consumption mode will be described later.

  The printer engine 5 prints out the print output data sent from the printer controller 1 on a recording medium such as paper.

  Next, a detailed configuration of the printer controller 1 will be described. As shown in FIG. 1, the printer controller 1 includes a CPU 11, a system controller 12, a main memory 13, a sub memory 14, and a ROM / I / O 15 that is another device.

  The CPU 11 performs information processing such as data conversion processing and various arithmetic processing. The CPU 11 accesses the main memory 13, reads programs and data from the main memory 13, and performs various processes. At this time, the CPU 11 can also write data into the main memory 13 and the sub memory 14.

  Further, when there is no instruction from the personal computer 3 for a certain period of time, the CPU 11 determines to shift the printer controller 1 to the low power consumption mode with low power consumption. At this time, the CPU 11 sends to the system controller 12 an address conversion ON instruction (to be described later) together with a copy instruction for copying a part of the program data stored in the main memory 13 to the sub memory 14. Further, the CPU 11 sends to the system controller 12 a power saving mode instruction for setting the main memory 13 and the sub memory 14 to a power saving mode (described later), and the CPU 11 itself has a CPU power saving mode in which the number of clocks is reduced. To do.

  When the system controller 12 receives an instruction from the personal computer 3 in the low power consumption mode, the CPU 11 receives a return request signal from the system controller 12, sends a return instruction to the system controller 12, and itself The number of clocks is returned to the normal state and the CPU power saving mode is restored. At this time, the CPU 11 receives a main memory return notification (to be described later) from the system controller 12, and issues an address conversion off instruction (to be described later) together with a copy instruction to return the program data copied to the sub memory 14 to the main memory 13. 12 to send.

  The main memory 13 is a memory for storing various control programs in the printer controller 1 and predetermined data necessary for the control programs, as well as storing printer language data and print output data sent from the personal computer 3. The main memory 13 is, for example, a 512 MB DRAM, and its area is defined by an address of 0000_0000h to less than 1000_0000h. The main memory 13 also has a normal operation mode in which writing / reading is possible, and a memory power saving mode in which stored data can be stored but cannot be written / read, and consumes less power than the normal operation mode. (SelfRefresh mode).

  Various control programs stored in the main memory 13 include, for example, a printing operation program that controls printing operation processing, a status notification program for performing status notification processing, and the like. Each of these programs has a required program capacity and a data capacity required for execution thereof. The printing operation program has a relatively large program capacity, and the status notification program has a smaller program capacity and data capacity than the printing operation program. Each program and data necessary for it are stored in a predetermined area of the main memory 13. For example, a program that can be executed with a relatively small capacity, such as a status notification program, is stored in an area of the main memory 13 at an address from 0000_0000h to less than 0400_0000h, and a printing operation program is from the address of the main memory 13 from 0400_0000h to less than 1000_0000h. Stored in the area.

  The sub memory 14 is a memory having a smaller capacity than the main memory 13 and is, for example, a 64 MB DRAM. The sub memory 14 can be written from the CPU 11. The sub memory 14 also has a normal operation mode in which writing / reading is possible, and a memory power saving mode in which the stored contents cannot be written / read but can be held, and consumes less power than the normal operation mode. And have.

  The ROM / I / O 15 is a storage device such as an HDD or ROM, or an input / output device such as a keyboard.

  The system controller 12 controls each connected device and transfers data and programs between the devices, and is configured by an LSI, for example. As will be described later, the system controller 12 causes the CPU 11 to access the main memory 13 or the sub memory 14 when the CPU 11 performs processing.

  As shown in FIG. 1, the system controller 12 includes a CPU interface 21, a DMA (Direct Memory Access) controller 22, an engine interface 23, a network interface 24, a ROM / I / O interface 25, and a main memory controller 26. A sub memory controller 27 and an internal bus 29.

  The CPU interface 21, the engine interface 23, the network interface 24, and the ROM / I / O interface 25 are connected to the CPU 11, the printer engine 5, the communication network 4, and the ROM / I / O 15, respectively. Sends and receives instructions and data to and from the device.

  In response to a copy instruction from the CPU 11, the DMA controller 22 sets a program and data stored in an area of the main memory 13 (or sub memory 14) corresponding to a predetermined address to a predetermined address. A copy process for copying to the area of the corresponding sub memory 14 (or main memory 13) is performed. That is, the copy instruction is an instruction to cause the DMA controller 22 to copy the program and data stored at a predetermined address to a predetermined address.

  Here, the CPU interface 21, the DMA controller 22, and the engine interface 23 have a function of starting transfer of programs and data. That is, in response to an instruction from the CPU 11, the CPU interface 21 receives the program and data stored in the main memory 13, the sub memory 14, and the ROM / I / O 15 and the printer language data received by the network interface 24 to a predetermined device. Let it be transferred. The engine interface 23 activates transfer of print output data from the sub memory 14 to the printer engine 5. Further, the DMA controller 22 activates transfer of programs and data between the main memory 13 and the sub memory 14. As described above, the CPU interface 21, the DMA controller 22, and the engine interface 23 having a function of starting transfer are referred to as a bus master.

  The main memory controller 26 and the sub memory controller 27 are connected to the main memory 13 and the sub memory 14, respectively, and read / write programs and data to / from the connected memory. Further, the main memory controller 26 and the sub memory controller 27 switch between the memory power saving mode and the normal operation mode in the main memory 13 and the sub memory 14, respectively.

  Here, the network interface 24, the ROM / I / O interface 25, the main memory controller 26, and the sub memory controller 27 receive a program and data transfer in response to an instruction from the bus master, and are referred to as a bus target.

  The internal bus 29 connects a bus master and a bus target. The internal bus 29 has an address space (address map) uniquely mapping each device, selects a bus target corresponding to an address designated by the bus master, and transmits a program and data transfer request. .

  The internal bus 29 has an address conversion circuit 29a that performs address conversion. The address conversion circuit 29a converts a predetermined address into another address. Here, the address conversion circuit 29a has an address conversion function for converting a copy source address when the DMA controller 22 executes a copy process into a copy destination address and converting the copy destination address into a copy source address. When the address conversion function in the address conversion circuit 29a is valid and the address specified by the bus master is the copy destination address or the copy source address, the internal bus 29 uses the address conversion circuit 29a to convert the specified address. The address is converted, and the bus target corresponding to the converted address (the converted address) is accessed.

  The address conversion circuit 29a validates the address conversion function when receiving an address conversion ON instruction from the CPU 11. On the other hand, when the address conversion circuit 29a receives an address conversion off instruction from the CPU 11, the address conversion circuit 29a invalidates the address conversion function. That is, the address conversion on / off instruction is an instruction for switching the function of the address conversion circuit 29a between valid and invalid.

  Next, the copy processing in the DMA controller 22 and the functions in the address conversion circuit 29a will be specifically described with reference to FIGS.

  FIG. 2 is a diagram showing address mapping when the address translation function of the address translation circuit 29a is invalid, and FIG. 3 is a diagram showing address mapping when the address translation function is valid.

  As shown in the figure, the areas of the main memory 13, the sub memory 14 and the ROM / I / O 15 on the bus target side have different addresses. For example, the area of the main memory 13 has an address 0000_0000h. The area of the sub memory 14 is specified with an address of 1000_0000h or more and less than 1400_0000h.

  As shown in FIG. 2, when the address conversion function is invalid, the internal bus 29 accesses the area of the bus target corresponding to the address designated on the bus master side. That is, when the address 0000_0000h is designated on the bus master side, the internal bus 29 accesses an area corresponding to the address 0000_0000h (here, the top of the main memory 13). As a result, the bus master side can perform processing such as reading or transfer for the program or data in the designated area.

  Next, a case where the address conversion function is effective will be described with reference to FIG. As will be described later, the address conversion circuit 29a switches the validity / invalidity of the address conversion function when the DMA controller 22 executes a copy process. In other words, when the function of the address conversion circuit 29a is effectively switched, as shown in FIG. 3, the DMA controller 22 determines that the copy source address (here, the address 0000_0000h or more and less than 0400_0000h) and the copy destination address (here, Address from 1000_0000h to less than 1400_0000h), and a predetermined program and data are copied from the main memory 13 to the sub memory. Here, the program and data to be copied are stored in advance in an address 0000_0000h or more and less than 0400_0000h in the main memory 13, and are a program that can be executed only by the capacity of the area specified by the address and data necessary for the program. is there. For example, the status notification program that can be executed with a relatively small capacity and the status data necessary for the program. Hereinafter, a program and data to be copied by the DMA controller 22 are referred to as copy target program data.

  The address conversion circuit 29a converts the copy source address in the copy process into a copy destination address. When the copy destination address is specified, the address conversion circuit 29a converts the copy source address into the copy source address. Convert. Specifically, the address conversion circuit 29a converts the leading 0 to 1 when the address 0000_0000h or more and less than 0400_0000h is specified, and converts the leading 1 to 0 when the address 1000_0000h or more and less than 1400_0000h is specified. . For example, when 0000_0000h is designated, the address conversion circuit 29a converts the leading 0 of the address to 1 and sets it to the address 1000_0000h.

  In this case, the internal bus 29 converts the predetermined address designated on the bus master side by the address conversion circuit 29a, and accesses the area of the bus target corresponding to the converted address (converted address). For example, as shown in FIG. 3, when a predetermined address (here, for example, address 0000_0000h) is designated on the bus master side, the address conversion circuit 29a converts the address to a predetermined address (here, for example, address 1000_0000h). Convert to Then, the internal bus 29 accesses an area corresponding to the converted address (here, the top area of the sub memory 14).

  Next, the flow of processing in the printer 2 will be described with reference to the flowchart of FIG.

  First, when the main power supply to the printer 2 is turned on, power is supplied to each device including the CPU 11, the main memory 13 and the sub memory 14 of the printer controller 1, and each process is performed in the steady state mode (S1). When the main power is turned on, as shown in FIG. 2, the function of the address conversion circuit 29 a is invalid and the copy target program data is stored in a predetermined area of the main memory 13. Both the main memory 13 and the sub memory 14 are in the normal operation mode.

  Here, each process includes a print operation process and a status notification process. Here, the print operation process will be described.

  First, the network interface 24 receives printer language data corresponding to a document to be printed out from the personal computer 3 via the communication network 4. When the network interface 24 receives the printer language data, the CPU 11 causes the printer language data to be transferred from the network interface 24 to the main memory 13. As a result, the printer language data received by the network interface 24 is stored in the main memory 13.

  Next, the CPU 11 reads the printer language data from the main memory 13, converts it into print output data by arithmetic processing, and stores it in the sub memory 14.

  The engine interface 23 reads out the print output data stored in the sub memory 14 and outputs it to the print engine 23, thereby realizing a print operation. Thus, the printing process is completed (S2).

  Here, when the printer 2 is a laser printer, when the print engine 23 starts reading the print output data of a certain page, the print engine 23 needs to continue outputting the print output data at a constant speed until the printing of the page is finished. . For this reason, it is necessary to ensure the reading speed of the print output data.

  When the print output data is stored in the main memory 13, it is necessary to access the main memory 13 from the CPU 11 in order to ensure the reading speed of the print output data from the main memory 13 and to operate the system control program. Furthermore, in order to operate the printer at high speed, it is necessary to simultaneously operate the process of receiving the printer language data of the next page and converting it into the print output data during the reading of the print output data. The load on the memory 13 is further increased. That is, if the printer 2 is to be operated at high speed, the load on the main memory 13 is increased, and the speeding up of the printer is limited.

  However, in the present embodiment, the print output data is stored not in the main memory 13 but in the sub memory 14 as described above. As a result, when printing output data is read, the load on the main memory 13 is reduced, and the speed at which the CPU 11 accesses the main memory 13 to generate printing output data for the next page can be improved. Can be improved.

  In the normal operation mode, the program and data for controlling the printer controller are stored on the large-capacity main memory 13, and the sub-memory 14 stores only temporary data such as print output data. used.

  When each process including the printing process is completed, the CPU 11 starts measuring an elapsed time from the completion time (S3).

  Next, the CPU 11 determines whether or not the network interface 24 has received any instruction via the communication network 4 (S4). When any instruction is received (Yes in S4), the CPU 11 returns to the processing step (S1) in the steady state mode according to the instruction received by the network interface 24. At this time, the CPU 11 resets the elapsed time measured in S3.

  When the instruction is not received (No in S4), the CPU 11 determines whether or not the elapsed time starting measurement in S3 has reached a preset time (for example, 30 minutes) (S4). If the designated time has not been reached (No in S5), the process returns to S4.

  When the designated time has been reached (Yes in S5), the CPU 11 determines to shift to the low power consumption mode.

  When the CPU 11 determines to shift to the low power consumption mode, it first outputs a copy instruction to the system controller 12.

  Upon receiving the copy instruction, the DMA controller 22 causes the main memory 13 to execute a copy process of the copy target program data (status notification program, status data, etc.). In this embodiment, the copy target program data is stored, for example, in an area of the main memory 13 at addresses 0000_0000h to 0400_0000h. That is, the DMA controller 22 designates the address from 0000_0000h to less than 0400_0000h as the copy source address, designates the address from 1000_0000h to less than 1400_0000h in the sub memory 14 as the copy destination address, and copies the copy target program data (S6).

  Next, the CPU 11 outputs to the system control 12 an address translation on instruction that validates the function of the address translation circuit 29a (S7). The address conversion circuit 29a that has received the address conversion ON instruction converts the leading 0 of the address 0000_0000h to less than 0400_0000h specified on the bus master side, and converts the leading 0 to 1 and less than 1400_0000h specified on the bus master side. Convert leading 1 to 0. That is, the address conversion circuit 29a exchanges the copy source address and the copy destination address for which the DMA controller 22 has performed the copy process. If an address other than the address 0000_0000h to less than 0400_0000h and the address 1000_0000h to less than 1400_0000h are designated on the bus master side, the address conversion circuit 29a does not convert the designated address.

  Next, the CPU 11 outputs a main memory power saving mode shift instruction for setting the main memory 13 to the memory power saving mode to the system controller 12. The main memory controller 26 that has received the instruction to shift to the main memory power saving mode switches the main memory 13 to the memory power saving mode (S8).

  Subsequently, the CPU 11 outputs to the system controller 12 a sub memory power saving mode transition instruction for setting the sub memory 14 to the memory power saving mode. The sub memory controller 27 that has received the instruction to shift to the sub memory power saving mode switches the sub memory 14 to the memory power saving mode (S9).

  Further, the CPU 11 confirms that the main memory 13 and the sub memory 14 have been switched to the memory power saving mode, and itself reduces the number of clocks and shifts to the CPU power saving mode (S10). As a result, the printer controller 1 enters the low power consumption mode.

  Next, the CPU 11 determines whether or not there is a return request signal from the network interface 24 (S11). The return request signal is a signal generated when the network interface 24 detects that an instruction or data has been transmitted from the personal computer 3 via the communication network 4, and is sent from the network interface 24 to the CPU 11.

  If there is no return request signal (No in S11), the process of S11 is repeated.

  On the other hand, when the return request signal is received (Yes in S11), the CPU 11 increases its own clock number and returns from the CPU power saving mode (S12). Then, the CPU 11 sends a return instruction to the system controller 12.

  In the system controller 12 that has received the return instruction from the CPU 11, the sub memory controller 27 returns the sub memory 14 to the normal operation mode (S13).

  Next, the CPU 11 starts processing according to the instruction received by the network interface 24 (S14). That is, the CPU 11 designates an address and sends it to the system controller 12 in order to take out the program and data for executing the processing from the main memory 13 or the sub memory 14.

  Next, the system controller 12 determines whether or not the process executed by the CPU 11 is completed only in the sub memory 14 (S15).

  Specifically, when the area accessed corresponding to the address designated by the CPU 11 is the sub memory 14, the system controller 12 determines that the process is completed only in the sub memory 14 (Yes in S15), and the CPU 11 When the area accessed corresponding to the address designated by is the main memory 13, it is determined that the process is not completed only in the sub memory 14 (No in S15).

  A case where the system controller 12 determines that the process is completed only in the sub memory 14 (Yes in S15) will be described. When the processing performed by the CPU 11 can be executed only with the copy target program data as in the status notification processing, the CPU 11 reads the status notification program and status data included in the copy target program data. However, the copy target program data stored in the addresses 0000_0000h to 0400_0000h of the main memory 13 is copied to the sub memory 14 by the process of S6. However, since the address conversion function is enabled by the process of S7, as shown in FIG. 4, the CPU 11 assigns the area from the address 0000_0000h to the address less than 0400_0000h as in the case before the copy process is performed. Thus, the internal bus 29 accesses the sub memory 14 by the conversion function of the address conversion circuit 29a.

  In this way, when viewed from the bus master side including the CPU 11, the sub memory 14 can be accessed by designating the address of the main memory 13. That is, the CPU 11 can access desired program data by designating the address of the main memory 13 even if the copy target program data is copied to the sub memory 14. Since the sub memory 14 has been restored in S13, the CPU 11 can perform processing normally. When the process ends, the CPU 11 determines to shift to the low power consumption mode again and returns to S9.

  On the other hand, a case where the system controller 12 determines that the processing is not completed only in the sub memory 14 (No in S15) will be described. When the processing performed by the CPU 11 cannot be executed only by the copy target program data as in the printing operation processing, the CPU 11 reads the print program not included in the copy target program data within addresses 0400_0000h to 1000_0000h. The predetermined area is designated address. Since the designated address is not converted by the address conversion circuit 29a, it becomes the access destination address as it is. The access destination addresses 0400_0000h to 1000_0000h are areas in the main memory 13. However, the main memory controller 26 cannot access the main memory 13 because the main memory 13 is still in the memory power saving mode. As a result, the system controller 12 can determine that the processing is not completed only in the sub memory 14.

  When the system controller 12 determines that the processing is not completed only in the sub memory 14 (No in S15), the main memory controller 26 returns the main memory 13 to the normal operation mode (S16). At this time, the main memory controller 26 sends a main memory return notification that notifies the CPU 11 that the main memory 13 has returned to the normal operation mode.

  Upon receiving the main memory return notification from the main memory controller 26, the CPU 11 outputs a copy instruction to the system controller 12 in order to return the copy target program / data copied to the sub memory 14 to the main memory 13. Upon receiving the copy instruction, the DMA controller 22 performs a process of returning the copy target program data to the original main memory 13 address 0000_0000h to 0400_0000h (S17).

  At this time, since the function of the address conversion circuit 29a is valid, the DMA controller 22 copies the program and data stored in the area of addresses 0000_0000h to 0400_0000h to the area of addresses 1000_0000h to 1400_0000h, as in S6 above. You can tell the internal bus to do it. As a result, the internal bus 29 converts the designated address and copies the program data stored in the area of addresses 1000_0000h to 1400_0000h to the area of addresses 0000_0000h to 0400_0000h. This is transmitted to the controller 27. As a result, the copy target program data that has been copied to the sub memory 14 is restored again to a predetermined area of the main memory 13 (S17).

  Thus, the latest information such as status data edited in the sub memory 14 while the main memory 13 is in the memory power saving mode can be reflected in the main memory 13, and the main memory 13 Updated to Therefore, the CPU 11 can execute processing based on the latest information copied to the main memory 13.

  Thereafter, the CPU 11 outputs an address translation off instruction to the system controller 12 in order to switch the function of the address translation circuit 29a from valid to invalid. As a result, the address conversion circuit 29a disables the address conversion function (S18). Thereafter, the process returns to the processing step (S1) in the normal operation mode of S1.

  As described above, the system controller 12 of this embodiment is connected to the CPU 11 and the main memory 13 that stores programs and data. When the CPU 11 performs processing in the steady state mode, the CPU 11 is connected to the main memory 13. To access. The system controller 12 is connected to a sub memory 14 having a smaller capacity than the main memory 13. Further, the main memory controller 26 switches the main memory 13 between a normal operation mode (normal state) in which at least stored contents can be read and a memory power saving mode (power saving state) in which power consumption is lower than the normal state. DMA in which a predetermined part of the program and data stored in the main memory 13 is copied to the sub memory 14 before the main memory controller 26 switches the main memory 13 from the normal operation mode to the memory power saving mode. When the CPU 11 performs processing when the controller 22 and the main memory 13 are in the memory power saving mode, if the program and data used for the processing are copied by the DMA controller 22, the CPU 11 accesses the sub memory 14. An internal bus 29

  Thereby, when the main memory 13 is in the memory power saving mode and the CPU 11 wants to access the copied program and data, it is not necessary to return the main memory 13 from the memory power saving mode. Processing can be executed only by the sub memory 14 having a small capacity and low power consumption.

  A predetermined program and data are copied. Therefore, the CPU 11 executes processing only in the sub memory 14 by presetting a program that is frequently started when the main memory 13 is in the memory power saving mode and data necessary for the program. The frequency at which the main memory 13 returns from the memory power saving mode to the normal operation mode can be further reduced. Therefore, power consumption can be reduced. Further, since it is not necessary to provide a special cache memory as described in Patent Document 1 in the CPU 11, a general-purpose CPU can be used.

  Further, after the main memory controller 26 returns the main memory 13 from the memory power saving mode to the normal operation mode, the DMA controller 22 stores the program and data stored in the sub memory 14 in the original storage area of the main memory 13. Re-copy.

  Therefore, the program and data including the latest information when the CPU 11 accesses the sub memory 14 when the main memory 13 is in the memory power saving mode are copied to the main memory 13. As a result, after the main memory 13 returns to the normal operation mode, the CPU 11 can execute processing with the program and data including the latest information by accessing the main memory 13. Further, the sub memory 14 can be used for other purposes while the main memory 13 is restored to the normal operation mode.

  Further, the storage areas of the main memory 13 and the sub memory 14 are given addresses for designating the storage areas. Then, the system controller 12 receives an access destination address for designating an access destination storage area from the CPU 11, and an address conversion for converting a copy source address of a program and data copied by the DMA controller 22 into a copy destination address. Circuit 29a. When the main memory 13 is in the memory power saving mode, the internal bus 29 converts the access destination address received by the CPU interface 21 by the address conversion circuit 29a, and accesses the CPU 11 to the storage area designated by the converted address. Let Therefore, the CPU 11 does not need to change the access destination address depending on whether or not the main memory 13 is in the memory power saving mode.

  The copy process is performed by the DMA controller 22. Therefore, there is no need for the CPU 11 to perform the copy process, and the burden on the CPU 11 can be reduced.

  The sub memory controller 27 sets the sub memory 14 in the power saving mode (power saving state) after the DMA controller 22 copies the program and data from the main memory 13 to the sub memory 14. Thereafter, when the CPU 11 performs processing, the sub memory 14 is returned to the normal operation mode. Therefore, power consumption in the sub memory 14 can be reduced and further power saving can be achieved between the time when the main memory 13 shifts to the memory power saving mode and the time when the CPU 11 performs processing next time.

[Embodiment 2]
In the above embodiment, the sub-memory 14 for temporarily storing the print output data in the steady state mode, the program executable by the capacity of the sub-memory 14 alone and the necessary data thereof are transferred to the main memory at the time of shifting to the low power consumption mode. It was set as the structure copied from 13. In the steady state mode, the sub memory 14 stores the print output data subjected to the data conversion processing by the CPU 11, so the CPU 11 needs to access the sub memory 14. Therefore, as shown in FIG. 1, the sub memory 14 is connected to the internal bus 29.

  However, there is an information processing apparatus that does not have a sub memory directly connected to the internal bus 29 and has a sub memory not connected to the internal bus 29. For example, an information processing apparatus included in a printer is configured to have only a sub memory that is directly connected to an engine interface and used as a memory dedicated to the printer engine. In this case, since the sub memory is dedicated to the engine interface and is not connected to the internal bus, the CPU 11 and the DMA controller 22 cannot directly access the sub memory.

  In the present embodiment, even if the sub memory cannot be directly accessed by the CPU or the DMA controller in the steady state mode as described above, the sub memory is used in the low power consumption mode to save power.

  The following describes the present embodiment with reference to FIGS. 5 and 6. For convenience of explanation, members having the same functions as those in the drawings described in the first embodiment are given the same reference numerals, and descriptions thereof are omitted.

  FIG. 5 is a block diagram showing the configuration of the printer controller (information processing apparatus) 101 in this embodiment and the relationship between the printer 102 including the printer controller 101 and the personal computer 3.

  As shown in FIG. 5, the printer 102 includes a printer controller 101 and a printer engine 5.

  Similar to the printer controller 1, the printer controller 101 performs various processes such as a printing operation process and a status notification process. As shown in FIG. 5, the printer controller 101 includes a CPU 11, a system controller 112, a main memory 13, a sub memory 114, and ROM / I / O 15 as other devices.

  The sub memory 114 is a memory having a smaller capacity than the main memory, and is, for example, a 64 MB RAM. The sub memory 114 is used as a memory dedicated to the printer engine 5 in the steady mode. Further, the sub memory 114 has a normal operation mode in which writing / reading is possible, and a memory power saving mode in which the stored contents cannot be written / read but can be stored, and consumes less power than the normal operation mode. And have.

  The system controller 112 controls each connected device and transfers data and programs between the devices.

  As shown in FIG. 5, the system controller 112 includes a CPU interface 21, a DMA controller 22, an engine interface 123, a network interface 24, an I / O interface 25, a main memory controller 26, a sub memory controller 127, an internal bus 29, and a bypass. A circuit 30 is provided.

  The engine interface 123 activates transfer of desired data from the main memory 23 and the ROM / I / O 15 via the internal bus 29. The engine interface 123 is directly connected to the sub memory controller 127, and the sub memory 114 can be used as a dedicated memory.

  The sub memory controller 127 performs a process of writing / reading a program and data to / from the sub memory 114, and is installed as a memory dedicated to the engine interface 123. The sub memory controller 127 switches between the memory power saving mode and the normal operation mode in the sub memory 114.

  The bypass circuit 30 is connected to the sub memory controller 127 and the internal bus 29 and is a circuit for relaying between the sub memory controller 127 and the internal bus 29. The bypass circuit 30 switches connection / disconnection between the sub memory controller 127 and the internal bus 29 in response to a bypass circuit on / off instruction from the CPU 11.

  As in the above-described embodiment, the DMA controller 22 responds to a copy instruction from the CPU 11 in accordance with a program and data (or sub-memory 114) stored in an area of the main memory 13 (or sub memory 114) corresponding to a predetermined address. That is, a process of copying the copy target program data) to the area of the sub memory 114 (or the main memory 13) corresponding to a predetermined address is performed. When the copy process is executed, since the internal bus 29 and the sub memory controller 127 are connected by the bypass circuit 30 as will be described later, the address of the sub memory 114 is placed on the address map of the internal bus 29. To be mapped. As a result, the DMA controller 22 can access the sub memory 114.

  Similarly to the above embodiment, the address conversion circuit 29a included in the internal bus 29 converts a copy source address when the DMA controller 22 executes a copy process into a copy destination address, and converts the copy destination address into a copy source address. Convert to

  Next, the flow of processing in the printer 102 will be described with reference to the flowchart of FIG.

  First, when the main power to the printer 102 is turned on, power is supplied to each device including the CPU 11, the main memory 13 and the sub memory 114 of the printer controller 101, and each process is performed in the steady state mode (S1). When the main power is turned on, the function of the address conversion circuit 29a is invalid, and the copy target program / data is stored in a predetermined area of the main memory 13.

  In this embodiment, since the sub memory 114 is a memory dedicated to the engine interface 123, the CPU 11 stores the print output data calculated from the printer language data in the main memory 13. The engine interface 123 reads out the print output data stored in the main memory 13 and outputs it to the print engine 23, thereby realizing a print operation. Thus, the printing process is completed. Further, the engine interface 123 may use the sub memory 114 when reading out the print output data stored in the main memory 13 and outputting it to the print engine 23.

  When each process including the printing process is completed (S2), the CPU 11 starts measuring an elapsed time from the completion time (S3).

  Next, the CPU 11 determines whether or not the network interface 24 has received any instruction via the communication network 4 (S4). When the instruction is received (Yes in S4), the CPU 11 returns to the processing step (S1) in the steady state mode according to the instruction received by the network interface 24. At this time, the CPU 11 resets the elapsed time measured in S3.

  When the instruction is not received (No in S4), the CPU 11 determines whether or not the elapsed time starting measurement in S3 has reached a preset time (for example, 30 minutes) (S4). If the designated time has not been reached (No in S5), the process returns to S4.

  When the designated time has been reached (Yes in S5), the CPU 11 determines to shift to the low power consumption mode.

  When the CPU 11 determines to shift to the low power consumption mode, the CPU 11 first outputs a bypass circuit ON instruction to the system controller 112 in order to validate the function of the bypass circuit 30. Thereby, the bypass circuit 30 connects the internal bus 29 and the sub memory controller 127 (S21). At this time, the area of the sub memory 114 is mapped to the address map of the internal bus 29.

  Next, the CPU 11 outputs a copy instruction to the system controller 112. Receiving the copy instruction, the DMA controller 22 causes the main memory 13 to execute the copy process of the copy target program data (status notification program, status data, etc.). For example, when the copy target program and data are stored in the area of the address 0000_0000h to 0400_0000h of the main memory 13, the DMA controller 22 stores the copy target program data stored in the area corresponding to the address 0000_0000h to less than 0400_0000h. The data is copied to the sub memory 114 (area corresponding to the address 1000_0000h or more and less than 1400_0000h) (S22).

  Next, the CPU 11 outputs an address conversion ON instruction for enabling the function of the address conversion circuit 29a to the system control 112 (S23). The address conversion circuit 29a that has received the address conversion ON instruction converts the leading 0 of the address 0000_0000h to less than 0400_0000h specified on the bus master side, and converts the leading 0 to 1 and less than 1400_0000h specified on the bus master side. Convert leading 1 to 0. If an address other than the address 0000_0000h to less than 0400_0000h and the address 1000_0000h to less than 1400_0000h are designated on the bus master side, the address conversion circuit 29a does not convert the designated address.

  Next, the CPU 11 outputs a main memory power saving mode shift instruction for setting the main memory 13 to the memory power saving mode to the system controller 112. The main memory controller 26 that has received the main memory power saving mode transition instruction switches the main memory 13 to the memory power saving mode (S24).

  Subsequently, the CPU 11 outputs to the system controller 112 a sub memory power saving mode transition instruction for setting the sub memory 114 to the memory power saving mode. Receiving the sub memory power saving mode transition instruction, the sub memory controller 127 switches the sub memory 114 to the memory power saving mode (S25).

  Further, the CPU 11 itself shifts to the CPU power saving mode (S26). As a result, the printer controller 101 enters a low power consumption mode.

  Next, the CPU 11 determines whether or not there is a return request signal from the network interface 24 (S27). If there is no return request signal (No in S27), the process of S27 is repeated. On the other hand, when the return request signal is received (Yes in S27), the CPU 11 increases its own clock number and returns from the CPU power saving mode (S28). Further, the CPU 11 returns and sends a return instruction to the system controller 112.

  In the system controller 112 that has received the return instruction from the CPU 11, the sub memory controller 127 returns the sub memory 114 to the normal operation mode (S29).

  Next, the CPU 11 starts processing according to the instruction received by the network interface 24 (S30). That is, the CPU 11 designates an address and sends it to the system controller 112 in order to retrieve a program and data for executing the processing from the memory.

  Next, the system controller 112 determines whether or not the process executed by the CPU 11 is completed only in the sub memory 114 (S31). Specifically, when the area accessed by the internal bus 29 is only the sub memory 114, the system controller 112 determines that the processing is completed only in the sub memory 114 (Yes in S31), and the internal bus 29 accesses. When the area is the main memory 13, the system controller 112 determines that the process is not completed only in the sub memory 114 (No in S31).

  Since the process in S31 is the same as S15 described in the above embodiment, a detailed description thereof is omitted here. If Yes in S31, the process returns to S25.

  On the other hand, in the case of No in S31, the main memory controller 26 returns the main memory 13 to the normal operation mode (S32). At this time, the main memory controller 26 sends a main memory return notification that notifies the CPU 11 that the main memory 13 has returned to the normal operation mode.

  Upon receiving the main memory return notification from the main memory controller 26, the CPU 11 outputs a copy instruction to the system controller 112 in order to return the copy target program / data copied to the sub memory 114 to the main memory 13. Receiving the copy instruction, the DMA controller 22 returns the copy target program data to the original main memory 13 address 0000_0000h to 0400_0000h area (S33).

  At this time, since the function of the address conversion circuit 29a is valid, the DMA controller 22 copies the program and data stored in the area of addresses 0000_0000h to 0400_0000h to the area of addresses 1000_0000h to 1400_0000h, as in S22 above. You can tell the internal bus to do it. As a result, the internal bus 29 converts the address, and instructs the main memory controller 26 and the sub memory controller to copy the copy target program data stored in the area of addresses 1000_0000h to 1400_0000h to the area of addresses 0000_0000h to 0400_0000h. 127. As a result, the copy target program data that has been moved to the sub memory 114 is returned again to a predetermined area of the main memory 13.

  Thereafter, the CPU 11 outputs an address translation off instruction to the system controller 112 in order to switch the function of the address translation circuit 29a from valid to invalid. As a result, the address conversion circuit 29a disables the address conversion function (S34).

  Further, the CPU 11 outputs a bypass circuit off instruction for invalidating the function of the bypass circuit 30 to the system controller 112. Thereby, the bypass circuit 30 shuts off the sub memory controller 127 and the internal bus 29 (S35). Then, the process returns to the processing step (S1) in the steady state mode.

  As described above, in this embodiment, a program that can be executed only by the capacity of the sub memory 114 and its necessary data are transferred to the sub memory 114 that is a dedicated memory for the engine interface in the steady state mode. Copy from the memory 13. At the same time, the sub memory controller 127 and the internal bus 29 are connected. Thereby, when execution of processing based on the copied program is instructed in the low power consumption mode, the processing can be performed only by returning only the sub memory 114. That is, since it is not necessary to restore the large-capacity main memory 13, power saving can be achieved.

  Further, the system controller 112 of this embodiment includes a bypass circuit 30 that switches whether the CPU 11 can access the sub memory 14. The bypass circuit 30 enables the CPU 11 to access the sub memory 14 at least when the main memory 13 is in the memory power saving mode. When the main memory 13 returns to the normal operation mode, access to the sub memory 14 from the CPU 11 is disabled, so that the sub memory 14 is a device other than the CPU 11 (for example, the printer engine 5 in this embodiment). It can be used as a dedicated storage means.

  In the present embodiment, the sub memory 114 is external to the system controller 112, but the system controller 112 may include the sub memory 114. In this case, the system controller 112 excluding the sub memory 114 can be said to be a control device that controls devices such as the main memory 13 and the sub memory 114.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

  Finally, each block of the system controllers 12 and 112 may be configured by hardware logic, or may be realized by software using an arithmetic means (CPU 11 or another CPU) as follows.

  That is, the system controllers 12 and 112 include a CPU that executes instructions of a power saving control program that realizes each function, a storage device (recording medium) such as a memory that stores the power saving control program and various data, and the like. . The object of the present invention is to record the program code (execution format program, intermediate code program, source program) of the power saving control program of the system controllers 12 and 112, which is software that realizes the above-described functions, in a computer-readable manner. This can also be achieved by supplying the recording medium to the system controllers 12 and 112 and reading and executing the program code recorded on the recording medium by the computer (or CPU or MPU).

  Examples of the recording medium include a tape system such as a magnetic tape and a cassette tape, a magnetic disk such as a floppy (registered trademark) disk / hard disk, and an optical disk such as a CD-ROM / MO / MD / DVD / CD-R. Card system such as IC card, IC card (including memory card) / optical card, or semiconductor memory system such as mask ROM / EPROM / EEPROM / flash ROM.

  Further, the system controllers 12 and 112 may be configured to be connectable to a communication network, and the program code may be supplied via the communication network. The communication network is not particularly limited. For example, the Internet, intranet, extranet, LAN, ISDN, VAN, CATV communication network, virtual private network, telephone line network, mobile communication network, satellite communication. A net or the like is available. Further, the transmission medium constituting the communication network is not particularly limited. For example, even in the case of wired such as IEEE 1394, USB, power line carrier, cable TV line, telephone line, ADSL line, etc., infrared rays such as IrDA and remote control, Bluetooth ( (Registered trademark), 802.11 wireless, HDR, mobile phone network, satellite line, terrestrial digital network, and the like can also be used. The present invention can also be realized in the form of a carrier wave or a data signal sequence in which the program code is embodied by electronic transmission.

  According to the control device or the information processing device of the present invention, a general-purpose arithmetic processing device can be used, and power saving can be achieved as compared with the related art. Therefore, the present invention can be applied to electronic devices such as printers, AV devices, and personal computers. Here, the electronic apparatus may include an arithmetic processing device such as a CPU, two storage units, and a control device that performs read / write processing of the two storage units.

1 is a block diagram illustrating a configuration of a printer controller according to an embodiment of the present invention. FIG. It is a figure which shows an address mapping when an address conversion function is invalid. It is a figure which shows an address mapping when an address translation function is effective. It is a flowchart which shows the flow of a process in the said printer controller. FIG. 10 is a block diagram illustrating a configuration of a printer controller according to another embodiment of the present invention. 6 is a flowchart showing a flow of processing in the printer controller shown in FIG. 5.

Explanation of symbols

1.101 Printer controller (information processing device)
11 CPU (arithmetic processing unit)
12.112 System controller (control device)
13 Main memory (first storage)
14.114 Sub memory (second storage)
22 DMA controller (copying means)
26 Main memory controller (first power switching means)
27/127 Sub-memory controller (second power switching means)
29 Internal bus (access control means)
29a Address conversion circuit (address conversion means)
30 Bypass circuit (access switching means)

Claims (10)

Connected to the arithmetic processing unit and a first storage unit for storing a program and data;
When the arithmetic processing device performs processing, the control device causes the arithmetic processing device to access the first storage unit,
Connected to a second storage unit having a smaller capacity than the first storage unit,
First power switching means for switching the first storage unit to a normal state in which at least stored contents can be read, or to a power saving state in which power consumption is lower than the normal state;
Before the first power switching unit switches the first storage unit from the normal state to the power saving state, a predetermined part of the program and data stored in the first storage unit is stored in the second storage unit. Copying means to copy to,
When the arithmetic processing unit performs processing when the first storage unit is in a power saving state, if the program and data used for the processing are copied by the copying unit, the arithmetic processing unit is Two access control means for accessing the storage unit,
When the arithmetic processing unit performs processing when the first storage unit is in a power saving state, the arithmetic processing unit determines whether or not the processing is completed without accessing the first storage unit. If the process is not completed without accessing the first storage unit, the first storage unit is caused to switch the first storage unit from a power saving state to a normal state. When the process is completed without accessing the first storage unit, the first power switching unit does not switch the first storage unit from the power saving state to the normal state .
After the first power switching unit returns the first storage unit from the power saving state to the normal state, the copying unit includes the program stored in the second storage unit and the first storage unit in the power saving state. Storage of the first storage unit that is a copy source when the data stored in the second storage unit edited during a certain period is copied before the first storage unit is switched from the normal state to the power saving state A control device for copying to an area . An address for designating the storage area is given to the storage areas of the first storage unit and the second storage unit,
An address receiving means for receiving an access destination designation address for designating an access destination storage area from the arithmetic processing unit;
Address conversion means for converting an address designating a copy source storage area of the program and data copied by the copy means into an address designating a copy destination storage area,
The access control means is configured to cause the address conversion means to convert the designated address received by the address receiving means when the first storage unit is in a power saving state, and to store the arithmetic processing device by the converted address. The control apparatus according to claim 1, wherein the area is accessed.   2. The control apparatus according to claim 1, wherein the copying unit copies a program and data according to a direct memory access method. An address for specifying the storage area is given to the storage area of the first storage unit and the second storage unit,
The copying means designates a copy source address and a copy destination address, and copies a program and data according to a direct memory access method.
When the copying unit copies a program and data from the second storage unit to the first storage unit, the copying unit includes an address conversion unit that replaces a copy source address and a copy destination address designated by the copy unit. The control device according to claim 1 . A second power switching unit configured to switch the second storage unit to at least a normal state in which stored contents can be read or a power saving state in which power consumption is smaller than the normal state;
The second power switching unit sets the second storage unit in a power saving state after the copying unit copies the program and data from the first storage unit to the second storage unit, and then the arithmetic processing unit performs processing. The control device according to claim 1, wherein the second storage unit is set in a normal state when performing. Comprising an access switching means for switching availability of access from the arithmetic processing unit to the second storage unit;
2. The control according to claim 1, wherein the access switching unit enables access from the arithmetic processing device to the second storage unit at least when the first storage unit is in a power saving state. apparatus. An arithmetic processing unit, a first storage unit that stores a program and data, a second storage unit having a smaller capacity than the first storage unit, and the control device according to any one of claims 1 to 6. An information processing apparatus comprising: It is connected to an arithmetic processing unit, a first storage unit for storing programs and data, and a second storage unit having a smaller capacity than the first storage unit, and at least the stored contents can be read out from the first storage unit A control method in a control device for switching to a normal state or a power saving state in which the power consumption is smaller than the normal state,
Before the first storage unit switches from the normal state to the power saving state, a predetermined part of the program and data stored in the first storage unit is copied to the second storage unit,
When the arithmetic processing unit performs processing when the first storage unit is in a power saving state, if the program and data used for the processing are copied, the arithmetic processing unit is accessed to the second storage unit. Let
When the arithmetic processing unit performs processing when the first storage unit is in a power saving state, the arithmetic processing unit determines whether or not the processing is completed without accessing the first storage unit. If the process is not completed without accessing the first storage unit, the first storage unit is switched from the power saving state to the normal state, and the process is performed without accessing the first storage unit. Is completed, the first storage unit is not switched from the power saving state to the normal state ,
A program stored in the second storage unit and the second storage unit edited while the first storage unit is in the power saving state after the first storage unit is returned from the power saving state to the normal state. A control method, wherein data to be stored is copied to a storage area of the first storage unit which is a copy source when the first storage unit is copied before the normal state is switched from a normal state to a power saving state . A power saving control program for operating the control device according to any one of claims 1 to 6, wherein the power saving control program causes a computer to function as each of the means. A computer-readable recording medium on which the power saving control program according to claim 9 is recorded.

Images