JP4358027B2

JP4358027B2 - LD driver circuit

Info

Publication number: JP4358027B2
Application number: JP2004141218A
Authority: JP
Inventors: 稔富樫
Original assignee: Nippon Telegraph and Telephone Corp
Current assignee: Nippon Telegraph and Telephone Corp
Priority date: 2004-05-11
Filing date: 2004-05-11
Publication date: 2009-11-04
Anticipated expiration: 2024-05-11
Also published as: JP2005323277A

Description

本発明は、バースト用レーザードダイオード（ＬＤ）ドライバ回路等のＬＤドライバ回路に関するものである。 The present invention relates to an LD driver circuit such as a laser diode (LD) driver circuit for burst.

図７は、従来例を示す図である。従来例（ＮＥＣ技報ＶＯＬ．５５ＮＯ１２／２００２Ｐ３６）は、トランジスタＴＲ５〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２、高電位電源端子３１、３２から構成され、ＴＲ５はドレインが、高電位電源端子３１に接続され、第１の反転入力端子１１がゲートに接続され、ソースが第１の定電流源Ｊ１の一端に接続され、ＴＲ６はドレインがドライバ出力端子２１に接続され、第１の入力端子１２はゲートに接続され、ソースが第１の定電流源Ｊ１の一端に接続され、ＴＲ８はドレインが、高電位電源端子３２に接続され、第２の反転入力端子１４がゲートに接続され、ソースが第２の定電流源Ｊ２の一端に接続され、ＴＲ７はドレインがドライバ出力端子２１に接続され、第２の入力端子１２がゲートに接続され、ソースが第２の定電流源Ｊ２の一端に接続され、第１の定電流源Ｊ１、第２の定電流源Ｊ２の他端は低電位電源端子３４に接続され構成される。 FIG. 7 is a diagram showing a conventional example. The conventional example (NEC technical report VOL.55NO12 / 2002P36) is composed of transistors TR5 to TR8, a first constant current source J1, a second constant current source J2, and high potential power supply terminals 31 and 32, and TR5 has a drain. The first inverting input terminal 11 is connected to the gate, the source is connected to one end of the first constant current source J1, the drain of TR6 is connected to the driver output terminal 21, The first input terminal 12 is connected to the gate, the source is connected to one end of the first constant current source J1, the drain of TR8 is connected to the high potential power supply terminal 32, and the second inverting input terminal 14 is the gate. , The source is connected to one end of the second constant current source J2, the TR7 has a drain connected to the driver output terminal 21, a second input terminal 12 connected to the gate, Is connected to one end of the second constant current source J2, a first constant current source J1, the other end of the second constant current source J2 is comprised are connected to the low-potential power supply terminal 34.

ＮＥＣ技報ＶＯＬ．５５ＮＯ１２／２００２Ｐ３６NEC Technical Report VOL. 55 NO12 / 2002 P36

従来のＬＤドライバ回路には高速化に間題があった。 Conventional LD driver circuits have a problem in speeding up.

本発明はより高速なＬＤドライバ回路を実現させることを目的とする。 An object of the present invention is to realize a higher-speed LD driver circuit.

請求項１に係わるＬＤドライバ回路は、第１のトランジスタのドレインと第２のトランジスタのドレインは共通に第２の抵抗の一端に接続され、前記第１のトランジスタのゲート、前記第２のトランジスタのゲート、第３のトランジスタのゲート、第４のトランジスタのゲートは共通に第１の抵抗の一端に接続され、前記第１のトランジスタのソースは第５のトランジスタのドレインに接続され、前記第２のトランジスタのドレインと前記第３のトランジスタのドレインは共通に出力部に接続され、前記第２のトランジスタのソースは第６のトランジスタのドレインに接続され、前記第３のトランジスタのソースは第７のトランジスタのドレインに接続され、前記第４のトランジスタのソースは第８のトランジスタのドレインに接続され、前記第５のトランジスタのゲートは第１の反転入力部に接続され、前記第５のトランジスタのソースと前記第６のトランジスタのソースは共通に第１の定電流源の一端に接続され、前記第６のトランジスタのゲートは第１の入力部に接続され、前記第７のトランジスタのゲートは第２の入力部に接続され、前記第７のトランジスタのソースと前記第８のトランジスタのソースは共通に第２の定電流源の一端に接続され、前記第８のトランジスタのゲートは第２の反転入力部に接続され、前記第１の抵抗と前記第２の抵抗の他端は共通に高電位電源に接続され、前記第１の定電流源の他端と前記第２の定電流源の他端が共通に低電位電源に接続する。
In the LD driver circuit according to claim 1 , the drain of the first transistor and the drain of the second transistor are commonly connected to one end of the second resistor, the gate of the first transistor, and the second transistor The gate, the gate of the third transistor, and the gate of the fourth transistor are commonly connected to one end of the first resistor, the source of the first transistor is connected to the drain of the fifth transistor, and the second transistor The drain of the transistor and the drain of the third transistor are commonly connected to the output section, the source of the second transistor is connected to the drain of the sixth transistor, and the source of the third transistor is the seventh transistor And the source of the fourth transistor is connected to the drain of the eighth transistor, The gate of the fifth transistor is connected to the first inverting input portion, the source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the sixth transistor The gate of the transistor is connected to the first input portion, the gate of the seventh transistor is connected to the second input portion, and the source of the seventh transistor and the source of the eighth transistor are commonly connected to the second input portion. 2 is connected to one end of the second constant current source, the gate of the eighth transistor is connected to the second inverting input section, and the other end of the first resistor and the second resistor is commonly used as a high potential power source. The other end of the first constant current source and the other end of the second constant current source are commonly connected to a low potential power source.

請求項２に係わるＬＤドライバ回路は、第２の高電位電源に第１のトランジスタのゲート、第２のトランジスタのゲート、第３のトランジスタのゲート、第４のトランジスタのゲートが共通に接続され、前記第１のトランジスタのドレインと前記第４のトランジスタのドレインは共通に第１の高電圧電源に接続され、前記第２のトランジスタのドレインと前記第３のトランジスタのドレインは共通に出力部に接続され、前記第１のトランジスタのソースは第５のトランジスタのドレインに接続され、前記第２のトランジスタのソースは第６のトランジスタのドレインに接続され、前記第３のトランジスタのソースは第７のトランジスタのドレインに接続され、前記第４のトランジスタのソースは第８のトランジスタのドレインに接続され、前記第５のトランジスタのゲートは第１の反転入力部に接続され、前記第５のトランジスタのソースと前記第６のトランジスタのソースは共通に第１の定電流源の一端に接続され、前記第６のトランジスタのゲートは第１の入力部に接続され、前記第７のトランジスタのゲートは第２の入力部に接続され、前記第７のトランジスタのソースと前記第８のトランジスタのソースは共通に第２の定電流源の一端に接続され、前記第８のトランジスタのゲートは第２の反転入力部に接続され、前記第１の定電流源の他端と前記第２の定電流源の他端は共通に低電位電源に接続する。
In the LD driver circuit according to claim 2 , the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are commonly connected to the second high potential power source. The drain of the first transistor and the drain of the fourth transistor are commonly connected to the first high voltage power supply, and the drain of the second transistor and the drain of the third transistor are commonly connected to the output section. The source of the first transistor is connected to the drain of the fifth transistor, the source of the second transistor is connected to the drain of the sixth transistor, and the source of the third transistor is the seventh transistor. And the source of the fourth transistor is connected to the drain of the eighth transistor, The gate of the fifth transistor is connected to the first inverting input portion, the source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the sixth transistor The gate of the transistor is connected to the first input portion, the gate of the seventh transistor is connected to the second input portion, and the source of the seventh transistor and the source of the eighth transistor are commonly connected to the second input portion. 2 is connected to one end of the second constant current source, the gate of the eighth transistor is connected to the second inverting input unit, the other end of the first constant current source and the other end of the second constant current source Are commonly connected to a low potential power source.

請求項３に係わるＬＤドライバ回路は、第１の抵抗の一端に第１のトランジスタのゲート、第２のトランジスタのゲート、第３のトランジスタのゲート、第４のトランジスタのゲートが共通に接続され、前記第１の抵抗の他端は第２の高電位電源に接続され、前記第１のトランジスタのドレインと前記第４のトランジスタのドレインは共通に第２の抵抗の一端に接続され、前記第２の抵抗の他端は第１の高電圧電源に接続され、前記第２のトランジスタのドレインと前記第３のトランジスタのドレインは共通に出力部に接続され、前記第１のトランジスタのソースは第５のトランジスタのドレインに接続され、前記第２のトランジスタのソースは第６のトランジスタのドレインに接続され、前記第３のトランジスタのソースは第７のトランジスタのドレインに接続され、前記第４のトランジスタのソースは第８のトランジスタのドレインに接続され、前記第５のトランジスタのゲートは第１の反転入力部に接続され、前記第５のトランジスタのソースと前記第６のトランジスタのソースは共通に第１の定電流源の一端に接続され、前記第６のトランジスタのゲートは第１の入力部に接続され、前記第７のトランジスタのゲートは第２の入力部に接続され、前記第７のトランジスタのソースと前記第８のトランジスタのソースは共通に第２の定電流源の一端に接続され、前記第８のトランジスタのゲートは第２の反転入力部に接続され、前記第１の定電流源の他端と前記第２の定電流源の他端は共通に低電位電源に接続する。
In the LD driver circuit according to claim 3 , the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are commonly connected to one end of the first resistor. The other end of the first resistor is connected to a second high potential power source, the drain of the first transistor and the drain of the fourth transistor are commonly connected to one end of a second resistor, and the second resistor The other end of the resistor is connected to the first high-voltage power supply, the drain of the second transistor and the drain of the third transistor are connected in common to the output section, and the source of the first transistor is the fifth And the source of the second transistor is connected to the drain of the sixth transistor, and the source of the third transistor is the seventh transistor. And the source of the fourth transistor is connected to the drain of the eighth transistor, the gate of the fifth transistor is connected to the first inverting input, and the source of the fifth transistor And the source of the sixth transistor are commonly connected to one end of the first constant current source, the gate of the sixth transistor is connected to the first input, and the gate of the seventh transistor is the second The source of the seventh transistor and the source of the eighth transistor are commonly connected to one end of the second constant current source, and the gate of the eighth transistor is the second inverting input. The other end of the first constant current source and the other end of the second constant current source are commonly connected to a low potential power source.

請求項４に係わるＬＤドライバ回路は、第１の抵抗の一端に第１のトランジスタのゲート、第２のトランジスタのゲート、第３のトランジスタのゲート、第４のトランジスタのゲートとコンデンサの一端が共通に接続され、前記第１の抵抗の他端と第２の抵抗の他端が共通に高電位電源接続され、前記第１のトランジスタのドレインと前記第４のトランジスタのドレインは共通に第２の抵抗の一端に接続され、前記第２のトランジスタのドレインと前記第３のトランジスタのドレインは共通に出力部に接続され、前記第１のトランジスタのソースは第５のトランジスタのドレインに接続され、前記第２のトランジスタのソースは第６のトランジスタのドレインに接続され、前記第３のトランジスタのソースは第７のトランジスタのドレインに接続され、前記第４のトランジスタのソースは第８のトランジスタのドレインに接続され、前記第５のトランジスタのゲートは第１の反転入力部に接続され、前記第５のトランジスタのソースと前記第６のトランジスタのソースは共通に第１の定電流源の一端に接続され、前記第６のトランジスタのゲートは第１の入力部に接続され、前記第７のトランジスタのゲートは第２の入力部に接続され、前記第７のトランジスタのソースと前記第８のトランジスタのソースは共通に第２の定電流源の一端に接続され、前記第８のトランジスタのゲートは第２の反転入力部に接続され、前記コンデンサの他端と前記第１の定電流源の他端と前記第２の定電流源の他端は共通に低電位電源に接続する。
In the LD driver circuit according to the fourth aspect , the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor, and one end of the capacitor are common to one end of the first resistor. The other end of the first resistor and the other end of the second resistor are commonly connected to a high-potential power supply, and the drain of the first transistor and the drain of the fourth transistor are commonly connected to the second Connected to one end of a resistor, the drain of the second transistor and the drain of the third transistor are connected in common to the output unit, the source of the first transistor is connected to the drain of a fifth transistor, The source of the second transistor is connected to the drain of the sixth transistor, and the source of the third transistor is connected to the drain of the seventh transistor. The source of the fourth transistor is connected to the drain of the eighth transistor, the gate of the fifth transistor is connected to the first inverting input, the source of the fifth transistor and the sixth transistor The sources of the transistors are commonly connected to one end of the first constant current source, the gate of the sixth transistor is connected to the first input section, and the gate of the seventh transistor is connected to the second input section. The source of the seventh transistor and the source of the eighth transistor are connected in common to one end of the second constant current source, and the gate of the eighth transistor is connected to the second inverting input section. The other end of the capacitor, the other end of the first constant current source, and the other end of the second constant current source are commonly connected to a low potential power source.

請求項５に係わるＬＤドライバ回路は、第１の抵抗の一端に第１のトランジスタのゲート、第２のトランジスタのゲート、第３のトランジスタのゲート、第４のトランジスタのゲートとコンデンサの一端が共通に接続され、前記第１の抵抗の他端が第２の高電位電源に接続され、第２の抵抗の一端に前記第１のトランジスタのドレインを接続し、前記第２の抵抗の他端は第１の高電位電源に接続され、前記第２のトランジスタのドレインと前記第３のトランジスタのドレインは共通に出力部に接続され、第３の抵抗の一端に前記第４のトランジスタのドレインを接続し、前記第３の抵抗の他端は第３の高電位電源に接続され、前記第１のトランジスタのソースは第５のトランジスタのドレインに接続され、前記第２のトランジスタのソースは第６のトランジスタのドレインに接続され、前記第３のトランジスタのソースは第７のトランジスタのドレインに接続され、前記第４のトランジスタのソースは第８のトランジスタのドレインに接続され、前記第５のトランジスタのゲートは第１の反転入力部に接続され、前記第５のトランジスタのソースと前記第６のトランジスタのソースは共通に第１の定電流源の一端に接続され、前記第６のトランジスタのゲートは第１の入力部に接続され、前記第７のトランジスタのゲートは第２の入力部に接続され、前記第７のトランジスタのソースと前記第８のトランジスタのソースは共通に第２の定電流源の一端に接続され、前記第８のトランジスタのゲートは第２の反転入力部に接続され、前記コンデンサの他端と前記第１の定電流源の他端と前記第２の定電流源の他端は共通に低電位電源に接続する。
In the LD driver circuit according to the fifth aspect , the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor, and one end of the capacitor are common to one end of the first resistor. The other end of the first resistor is connected to a second high potential power supply, the drain of the first transistor is connected to one end of the second resistor, and the other end of the second resistor is Connected to the first high-potential power supply, the drain of the second transistor and the drain of the third transistor are connected in common to the output section, and the drain of the fourth transistor is connected to one end of the third resistor The other end of the third resistor is connected to a third high potential power source, the source of the first transistor is connected to the drain of the fifth transistor, and the source of the second transistor is 6 is connected to the drain of the sixth transistor, the source of the third transistor is connected to the drain of the seventh transistor, the source of the fourth transistor is connected to the drain of the eighth transistor, and the fifth transistor Is connected to the first inverting input portion, the source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the gate of the sixth transistor. Is connected to the first input portion, the gate of the seventh transistor is connected to the second input portion, and the source of the seventh transistor and the source of the eighth transistor are commonly connected to the second constant current. Connected to one end of the source, the gate of the eighth transistor is connected to the second inverting input, the other end of the capacitor and the other end of the first constant current source The other end of the second constant current source connected in common to the low-potential power supply.

カスコード接続により、ドライバのスイッチングトランジスタの等価寄生容量が小さくでき、結果として、ドライバを従来例より約３０％高速動作できる。また、カスコードバイアス電源と、ＬＤドライバの主電源を共通化できるため、新たな電源または、電源回路を必要としないと言う効果がある。 By cascode connection, the equivalent parasitic capacitance of the switching transistor of the driver can be reduced, and as a result, the driver can be operated about 30% faster than the conventional example. Further, since the cascode bias power supply and the main power supply of the LD driver can be shared, there is an effect that a new power supply or a power supply circuit is not required.

以下、図面を用いて本発明の実施の形態について説明する。なお、以下で説明する図面で、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof is omitted.

本発明の第１の実施の形態について、図１を用いて説明する。図１は本発明の第１の実施の形態のＬＤドライバ回路の回路図であり、先ず、図１の構成を説明する。 A first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram of an LD driver circuit according to a first embodiment of the present invention. First, the configuration of FIG. 1 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、高電位電源端子３１、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２から構成されている。 First input terminal 11, first inverting input terminal 12, second input terminal 13, second inverting input terminal 14, high potential power terminal 31, low potential power terminal 34, output terminal 21, transistors TR1 to TR8 The first constant current source J1 and the second constant current source J2.

次に、第１の実施の形態のＬＤドライバ回路の接続を説明する。ＴＲ１（第１のトランジスタ）のドレイン、ＴＲ４（第４のトランジスタ）のドレイン、ＴＲ１のゲート、ＴＲ２（第２のトランジスタ）のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４のゲートは共通に高電位電源端子３１に接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子（出力部）２１に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、ＴＲ５のゲートは第１の反転入力端子（第１の反転入力部）１１に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは第１の入力端子（第１の入力部）に接続され、ＴＲ７のゲートは第２の入力端子（第２の入力部）１３に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子（第２の反転入力部）１４に接続され、Ｊ１の他端とＪ２の他端は共通に低電位電源端子３４に接続されている。 Next, connection of the LD driver circuit of the first embodiment will be described. The drain of TR1 (first transistor), the drain of TR4 (fourth transistor), the gate of TR1, the gate of TR2 (second transistor), the gate of TR3 (third transistor), and the gate of TR4 are common. Connected to the high potential power supply terminal 31, the drain of TR2 and the drain of TR3 are connected in common to the output terminal (output unit) 21, the source of TR1 is connected to the drain of TR5 (fifth transistor), and the source of TR2 Is connected to the drain of TR6 (sixth transistor), the source of TR3 is connected to the drain of TR7 (seventh transistor), the source of TR4 is connected to the drain of TR8 (eighth transistor), The gate is connected to the first inverting input terminal (first inverting input unit) 11, and the source of TR 5 and the source of TR 6 are Connected to one end of J1, the gate of TR6 is connected to the first input terminal (first input section), the gate of TR7 is connected to the second input terminal (second input section) 13, The source of TR7 and the source of TR8 are commonly connected to one end of J2, the gate of TR8 is connected to a second inverting input terminal (second inverting input unit) 14, and the other end of J1 and the other end of J2 are connected to each other. Commonly connected to the low potential power supply terminal 34.

以上述べた構成により、カスコード回路のＴＲ１〜ＴＲ４のゲートへの電源およびＴＲ１、ＴＲ４への電源を高電位電源ＶＤＤの１電源とすることができ、回路構成が簡略化できる。またカスコード回路を採用しているため、ＬＤドライバ回路のスイッチング回路の等価寄生容量が小さくでき、ドライバのスイッチング速度は従来構成より２０〜３０％高速動作ができる。 With the above-described configuration, the power supply to the gates of TR1 to TR4 and the power supply to TR1 and TR4 of the cascode circuit can be one power supply of the high potential power supply VDD, and the circuit configuration can be simplified. In addition, since the cascode circuit is employed, the equivalent parasitic capacitance of the switching circuit of the LD driver circuit can be reduced, and the switching speed of the driver can be 20 to 30% faster than the conventional configuration.

図２は、本発明の第２の実施の形態を示す図である。先ず、図２の構成を説明する。 FIG. 2 is a diagram showing a second embodiment of the present invention. First, the configuration of FIG. 2 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、高電位電源端子３１、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２、抵抗Ｒ１、Ｒ２から構成されている。 First input terminal 11, first inverting input terminal 12, second input terminal 13, second inverting input terminal 14, high potential power terminal 31, low potential power terminal 34, output terminal 21, transistors TR1 to TR8 The first constant current source J1, the second constant current source J2, and the resistors R1 and R2.

次に、第２の実施の形態のＬＤドライバ回路の接続を説明する。ＴＲ１（第１のトランジスタ）のドレインとＴＲ２（第２のトランジスタ）のドレインは共通にＲ２（第２の抵抗）の一端に接続され、ＴＲ１のゲート、ＴＲ２のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４（第４のトランジスタ）のゲートは共通にＲ１（第１の抵抗）の一端に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子２１（出力部）に接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、ＴＲ５のゲートは第１の反転入力端子１１（第１の反転入力部）に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは入力端子１２（第１の入力部）に接続され、ＴＲ７のゲートは入力端子１３（第２の入力部）に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子（第２の反転に入力）１４に接続され、Ｒ１（第１の抵抗）とＲ２（第２の抵抗）の他端は共通に高電位電源端子３１に接続され、Ｊ１の他端とＪ２の他端が共通に低電位電源端子３４に接続する。 Next, the connection of the LD driver circuit of the second embodiment will be described. The drain of TR1 (first transistor) and the drain of TR2 (second transistor) are commonly connected to one end of R2 (second resistor). The gate of TR1, the gate of TR2, and TR3 (third transistor) And the gate of TR4 (fourth transistor) are commonly connected to one end of R1 (first resistor), the source of TR1 is connected to the drain of TR5 (fifth transistor), the drain of TR2 and TR3 Are commonly connected to the output terminal 21 (output unit), the source of TR2 is connected to the drain of TR6 (sixth transistor), the source of TR3 is connected to the drain of TR7 (seventh transistor), The source of TR4 is connected to the drain of TR8 (eighth transistor), and the gate of TR5 is the first inverting input terminal 11 (first inverting input). ), The source of TR5 and the source of TR6 are commonly connected to one end of J1, the gate of TR6 is connected to the input terminal 12 (first input section), and the gate of TR7 is connected to the input terminal 13 (second input). The source of TR7 and the source of TR8 are commonly connected to one end of J2, the gate of TR8 is connected to the second inverting input terminal (input to the second inverting) 14, and R1 ( The other ends of the first resistor) and R2 (second resistor) are commonly connected to the high potential power supply terminal 31, and the other end of J1 and the other end of J2 are commonly connected to the low potential power supply terminal.

以上述べた構成により、ＬＤドライバ回路のスイッチング回路の等価寄生容量を小さくし、ドライバのスイッチング速度を従来構成より２０〜３０％高速動作ができるというカスコード回路の特徴を損なうことなく、かつ、Ｒ１、Ｒ２を設けたことによって寄生インダクタンスによる波形の乱れを吸収する効果がある。
Thus mentioned configuration, reducing the equivalent parasitic capacitance of the switching circuit of the LD driver circuit, without impairing the characteristics of the cascode circuit that can 20-30% faster operation than the conventional structure the switching speed of the driver, and, R1, The provision of R2 has the effect of absorbing waveform disturbance due to parasitic inductance.

図３は、本発明の第３の実施の形態を示す図である。先ず、図３の構成を説明する。 FIG. 3 is a diagram showing a third embodiment of the present invention. First, the configuration of FIG. 3 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、第１の高電位電源端子３１、第２の高電位電源端子３２、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２から構成されている。 First input terminal 11, first inverting input terminal 12, second input terminal 13, second inverting input terminal 14, first high potential power terminal 31, second high potential power terminal 32, low potential The power source terminal 34, the output terminal 21, transistors TR1 to TR8, a first constant current source J1, and a second constant current source J2 are included.

次に、第３の実施の形態のＬＤドライバ回路の接続を説明する。第２の高電位電源端子３２にＴＲ１（第１のトランジスタ）のゲート、ＴＲ２（第２のトランジスタ）のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４のゲートは共通に接続され、ＴＲ１（第１のトランジスタ）のドレイン、ＴＲ４（第４のトランジスタ）のドレインは共通に第１の高電位電源端子３１に接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子（出力部）２１に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、ＴＲ５のゲートは第１の反転入力端子（第１の反転入力部）１１に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは第１の入力端子（第１の入力部）に接続され、ＴＲ７のゲートは第２の入力端子（第２の入力部）１３に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子（第２の反転入力部）１４に接続され、Ｊ１の他端とＪ２の他端は共通に低電位電源端子３４に接続されている。 Next, connection of the LD driver circuit of the third embodiment will be described. The gate of TR1 (first transistor), the gate of TR2 (second transistor), the gate of TR3 (third transistor), and the gate of TR4 are connected in common to the second high-potential power supply terminal 32, and TR1 ( The drain of the first transistor) and the drain of TR4 (fourth transistor) are commonly connected to the first high-potential power supply terminal 31, and the drain of TR2 and the drain of TR3 are commonly connected to the output terminal (output unit) 21. Connected, the source of TR1 is connected to the drain of TR5 (fifth transistor), the source of TR2 is connected to the drain of TR6 (sixth transistor), and the source of TR3 is the drain of TR7 (seventh transistor) , The source of TR4 is connected to the drain of TR8 (eighth transistor), and the gate of TR5 is the first inverting input terminal. (First inverting input unit) 11 is connected, the source of TR5 and the source of TR6 are commonly connected to one end of J1, the gate of TR6 is connected to a first input terminal (first input unit), The gate of TR7 is connected to the second input terminal (second input unit) 13, the source of TR7 and the source of TR8 are connected in common to one end of J2, and the gate of TR8 is connected to the second inverting input terminal (second input). 2 inverting input portion 14, and the other end of J 1 and the other end of J 2 are connected in common to a low potential power supply terminal 34.

この構成により、ＬＤドライバ回路のスイッチング回路の等価寄生容量を小さくし、ドライバのスイッチング速度を従来構成より２０〜３０％高速動作ができるというカスコード回路の特徴を損なうことなく、かつ、ＶＤＤ１とＶＤＤ２を分離することで、出力波形をより良いものにすることができる。また、ＶＤＤ１とＶＤＤ２を同一とすることで、第１の実施の形態と同様の効果が得られる。
With this configuration, the equivalent parasitic capacitance of the switching circuit of the LD driver circuit can be reduced, and the switching speed of the driver can be operated by 20 to 30% faster than the conventional configuration, and the characteristics of the cascode circuit can be reduced. By separating, the output waveform can be improved. Further, by making VDD1 and VDD2 the same, the same effect as in the first embodiment can be obtained.

図４は、本発明の第４の実施の形態を示す図である。先ず、図４の構成を説明する。 FIG. 4 is a diagram showing a fourth embodiment of the present invention. First, the configuration of FIG. 4 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、第１の高電位電源端子３１、第２の高電位電源端子３２、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２、抵抗Ｒ１、Ｒ２から構成されている。 First input terminal 11, first inverting input terminal 12, second input terminal 13, second inverting input terminal 14, first high potential power terminal 31, second high potential power terminal 32, low potential The power source terminal 34, the output terminal 21, transistors TR1 to TR8, a first constant current source J1, a second constant current source J2, and resistors R1 and R2 are included.

次に、第４の実施の形態のＬＤドライバ回路の接続を説明する。Ｒ１（第１の抵抗）の一端にＴＲ１（第１のトランジスタ）のゲート、ＴＲ２（第２のトランジスタ）のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４（第４のトランジスタ）のゲートが共通に接続され、Ｒ１の他端は第２の高電位電源端子３２に接続され、ＴＲ１のドレインとＴＲ４のドレインは共通にＲ２（第２の抵抗）の一端に接続され、Ｒ２の他端は第１の高電圧電源端子３１に接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子２１に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、ＴＲ５のゲートは第１の反転入力端子１１に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは第１の入力端子１２に接続され、ＴＲ７のゲートは第２の入力端子１３に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子１４に接続され、Ｊ１の他端とＪ２の他端は共通に低電位電源端子３４に接続されている。 Next, connection of the LD driver circuit of the fourth embodiment will be described. One end of R1 (first resistor) has a gate of TR1 (first transistor), a gate of TR2 (second transistor), a gate of TR3 (third transistor), and a gate of TR4 (fourth transistor). The other end of R1 is connected to the second high potential power supply terminal 32, the drain of TR1 and the drain of TR4 are connected to one end of R2 (second resistor), and the other end of R2 is Connected to the first high voltage power supply terminal 31, the drain of TR2 and the drain of TR3 are connected in common to the output terminal 21, the source of TR1 is connected to the drain of TR5 (fifth transistor), and the source of TR2 is The drain of TR6 (sixth transistor) is connected, the source of TR3 is connected to the drain of TR7 (seventh transistor), and the source of TR4 is TR8 (eighth transistor). The gate of TR5 is connected to the first inverting input terminal 11, the source of TR5 and the source of TR6 are commonly connected to one end of J1, and the gate of TR6 is connected to the first input terminal 12. , The gate of TR7 is connected to the second input terminal 13, the source of TR7 and the source of TR8 are connected in common to one end of J2, the gate of TR8 is connected to the second inverting input terminal 14, The other end of J1 and the other end of J2 are connected to the low potential power supply terminal 34 in common.

この構成により、ＬＤドライバ回路のスイッチング回路の等価寄生容量を小さくし、ドライバのスイッチング速度を従来構成より２０〜３０％高速動作ができるというカスコード回路の特徴を損なうことなく、Ｒ１、Ｒ２を設けたことによって寄生インダクタンスによる波形の乱れを吸収する効果があり、かつ、第３の実施の形態の効果も兼ね備えることができる。
With this configuration, the equivalent parasitic capacitance of the switching circuit of the LD driver circuit is reduced, and R1 and R2 are provided without impairing the characteristics of the cascode circuit that the driver switching speed can be operated 20 to 30% faster than the conventional configuration . effects have to absorb the disturbance of waveform due to the parasitic inductance by is, and can combine the effect of the third embodiment.

図５は、本発明の第５の実施の形態を示す図である。先ず、図５の構成を説明する。 FIG. 5 is a diagram showing a fifth embodiment of the present invention. First, the configuration of FIG. 5 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、高電位電源端子３１、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２、抵抗Ｒ１、Ｒ２とコンデンサＣから構成されている。 First input terminal 11, first inverting input terminal 12, second input terminal 13, second inverting input terminal 14, high potential power terminal 31, low potential power terminal 34, output terminal 21, transistors TR1 to TR8 The first constant current source J1, the second constant current source J2, resistors R1 and R2, and a capacitor C.

次に、第５の実施の形態のＬＤドライバ回路の接続を説明する。Ｒ１（第１の抵抗）の一端にＴＲ１（第１のトランジスタ）のゲート、ＴＲ２（第２のトランジスタ）のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４（第４のトランジスタ）のゲートとコンデンサＣの一端が共通に接続され、Ｒ１の他端とＲ２（第２の抵抗）の他端が共通に高電位電源端子３１接続され、ＴＲ１のドレインとＴＲ４のドレインは共通にＲ２の一端に接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子２１に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、ＴＲ５のゲートは第１の反転入力端子１１に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは第１の入力端子１２に接続され、ＴＲ７のゲートは第２の入力端子１３に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子１４に接続され、コンデンサＣの他端とＪ１の他端とＪ２の他端は共通に低電位電源端子３４に接続されている。 Next, connection of the LD driver circuit of the fifth embodiment will be described. One end of R1 (first resistor) is connected to the gate of TR1 (first transistor), the gate of TR2 (second transistor), the gate of TR3 (third transistor), the gate of TR4 (fourth transistor), One end of the capacitor C is commonly connected, the other end of R1 and the other end of R2 (second resistor) are commonly connected to the high potential power supply terminal 31, and the drain of TR1 and the drain of TR4 are commonly connected to one end of R2. The drains of TR2 and TR3 are connected in common to the output terminal 21, the source of TR1 is connected to the drain of TR5 (fifth transistor), and the source of TR2 is the drain of TR6 (sixth transistor). , The source of TR3 is connected to the drain of TR7 (seventh transistor), and the source of TR4 is the drain of TR8 (eighth transistor). , The gate of TR5 is connected to the first inverting input terminal 11, the source of TR5 and the source of TR6 are connected in common to one end of J1, the gate of TR6 is connected to the first input terminal 12, The gate of TR7 is connected to the second input terminal 13, the source of TR7 and the source of TR8 are connected in common to one end of J2, the gate of TR8 is connected to the second inverting input terminal 14, and the other capacitor C The other end of J1, the other end of J1, and the other end of J2 are commonly connected to the low potential power supply terminal 34.

この構成により、ＬＤドライバ回路のスイッチング回路の等価寄生容量を小さくし、ドライバのスイッチング速度を従来構成より２０〜３０％高速動作ができるというカスコード回路の特徴を損なうことなく、Ｒ１、Ｒ２を設けたことによって寄生インダクタンスによる波形の乱れを吸収する効果があり、かつ、コンデンサＣはＴＲ１〜ＴＲ４のゲート電圧をより安定化させる効果がある。また第４の実施の形態と同様の効果がある。
With this configuration, the equivalent parasitic capacitance of the switching circuit of the LD driver circuit is reduced, and R1 and R2 are provided without impairing the characteristics of the cascode circuit that the driver switching speed can be operated 20 to 30% faster than the conventional configuration . Ri effect there to absorb disturbance of waveform due to the parasitic inductance by, and the capacitor C is effective to stabilize the gate voltage of TR1 to TR4. Also, there are the same effects as in the fourth embodiment.

図６は、本発明の第６の実施の形態を示す図である。先ず、図６の構成を説明する。 FIG. 6 is a diagram showing a sixth embodiment of the present invention. First, the configuration of FIG. 6 will be described.

第１の入力端子１１、第１の反転入力端子１２、第２の入力端子１３、第２の反転入力端子１４、第１の高電位電源端子３１、第２の高電位電源端子３２、第３の高電位電源端子３３、低電位電源端子３４、出力端子２１、トランジスタＴＲ１〜ＴＲ８、第１の定電流源Ｊ１、第２の定電流源Ｊ２、抵抗Ｒ１、Ｒ２、Ｒ３とコンデンサＣから構成されている。 1st input terminal 11, 1st inverting input terminal 12, 2nd input terminal 13, 2nd inverting input terminal 14, 1st high potential power supply terminal 31, 2nd high potential power supply terminal 32, 3rd High-potential power supply terminal 33, low-potential power supply terminal 34, output terminal 21, transistors TR1 to TR8, first constant current source J1, second constant current source J2, resistors R1, R2, R3 and capacitor C. ing.

次に、第６の実施の形態のＬＤドライバ回路の接続を説明する。Ｒ１（第１の抵抗）の一端にＴＲ１（第１のトランジスタ）のゲート、ＴＲ２（第２のトランジスタ）のゲート、ＴＲ３（第３のトランジスタ）のゲート、ＴＲ４（第４のトランジスタ）のゲートとコンデンサＣの一端が共通に接続され、前記Ｒ１の他端が第２の高電位電源端子３２に接続され、Ｒ２（第２の抵抗）の一端にＴＲ１のドレインを接続し、Ｒ２の他端は第１の高電位電源端子３１に接続され、ＴＲ２のドレインとＴＲ３のドレインは共通に出力端子２１に接続され、Ｒ３（第３の抵抗）の一端にＴＲ４のドレインを接続し、Ｒ３の他端は第３の高電位電源端子３３に接続され、ＴＲ１のソースはＴＲ５（第５のトランジスタ）のドレインに接続され、ＴＲ２のソースはＴＲ６（第６のトランジスタ）のドレインに接続され、ＴＲ３のソースはＴＲ７（第７のトランジスタ）のドレインに接続され、ＴＲ４のソースはＴＲ８（第８のトランジスタ）のドレインに接続され、第５のトランジスタのゲートは第１の反転入力端子１１に接続され、ＴＲ５のソースとＴＲ６のソースは共通にＪ１の一端に接続され、ＴＲ６のゲートは第１の入力端子１２に接続され、ＴＲ７のゲートは第２の入力端子１３に接続され、ＴＲ７のソースとＴＲ８のソースは共通にＪ２の一端に接続され、ＴＲ８のゲートは第２の反転入力端子１４に接続され、コンデンサＣの他端とＪ１の他端とＪ２の他端は共通に低電位電源端子３４に接続されている。
この構成により、ＬＤドライバ回路のスイッチング回路の等価寄生容量を小さくし、ドライバのスイッチング速度を従来構成より２０〜３０％高速動作ができるというカスコード回路の特徴を損なうことなく、Ｒ１、Ｒ２、Ｒ３を設けたことにより、寄生インダクタンスによる波形の乱れを吸収する効果がある。かつ、コンデンサＣはＴＲ１〜ＴＲ４のゲート電圧をより安定化させる効果がある。同様に第２の実施の形態において、Ｒ１と低電位電源ＶＳＳ間に容量を挿入すると同様の効果がある。もちろんＲ１、Ｒ２、Ｒ３、コンデンサＣのいずれかがない場合でも、高速化の効果がある。さらにＶＤＤ１〜ＶＤＤ３は同一の電源であってもよい。 Next, the connection of the LD driver circuit of the sixth embodiment will be described. One end of R1 (first resistor) is connected to the gate of TR1 (first transistor), the gate of TR2 (second transistor), the gate of TR3 (third transistor), the gate of TR4 (fourth transistor), One end of the capacitor C is connected in common, the other end of R1 is connected to the second high potential power supply terminal 32, the drain of TR1 is connected to one end of R2 (second resistor), and the other end of R2 is Connected to the first high potential power supply terminal 31, the drain of TR2 and the drain of TR3 are connected to the output terminal 21 in common, the drain of TR4 is connected to one end of R3 (third resistor), and the other end of R3 Is connected to the third high potential power supply terminal 33, the source of TR1 is connected to the drain of TR5 (fifth transistor), the source of TR2 is connected to the drain of TR6 (sixth transistor), and T 3 is connected to the drain of TR7 (seventh transistor), the source of TR4 is connected to the drain of TR8 (eighth transistor), and the gate of the fifth transistor is connected to the first inverting input terminal 11. The source of TR5 and the source of TR6 are commonly connected to one end of J1, the gate of TR6 is connected to the first input terminal 12, the gate of TR7 is connected to the second input terminal 13, and the source of TR7 And the source of TR8 are commonly connected to one end of J2, the gate of TR8 is connected to the second inverting input terminal 14, and the other end of the capacitor C, the other end of J1, and the other end of J2 are commonly connected to a low potential power source. It is connected to the terminal 34.
This configuration reduces the equivalent parasitic capacitance of the switching circuit of the LD driver circuit, without impairing the characteristics of the cascode circuit that the switching speed of the driver can 20-30% faster operation than the conventional configuration, the R1, R2, R3 By providing, there is an effect of absorbing the disturbance of the waveform due to the parasitic inductance. In addition, the capacitor C has an effect of further stabilizing the gate voltages of TR1 to TR4. Similarly, in the second embodiment, the same effect can be obtained by inserting a capacitor between R1 and the low potential power supply VSS. Of course, even if any of R1, R2, R3 and capacitor C is not provided, there is an effect of speeding up. Furthermore, VDD1 to VDD3 may be the same power source.

第１の実施の形態のＬＤドライバ回路の回路図。1 is a circuit diagram of an LD driver circuit according to a first embodiment. FIG. 第２の実施の形態のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of 2nd Embodiment. 第３の実施の形態のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of 3rd Embodiment. 第４の実施の形態のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of 4th Embodiment. 第５の実施の形態のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of 5th Embodiment. 第６の実施の形態のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of 6th Embodiment. 従来例のＬＤドライバ回路の回路図。The circuit diagram of the LD driver circuit of a prior art example.

Explanation of symbols

１１第１の反転入力端子
１２第１の入力端子
１３第２の入力端子
１４第２の反転入力端子
２１出力端子
３１高電位電源端子、第１の高電位電源端子
３２第３の高電位電源端子
３３第２の高電位電源端子
３４低電位電源端子
Ｃコンデンサ
Ｊ１第１の定電流源
Ｊ２第２の定電流源
Ｒ１第１の抵抗
Ｒ２第２の抵抗
Ｒ３第３の抵抗
ＴＲ１第１のトランジスタ
ＴＲ２第２のトランジスタ
ＴＲ３第３のトランジスタ
ＴＲ４第４のトランジスタ
ＴＲ５第５のトランジスタ
ＴＲ６第６のトランジスタ
ＴＲ７第７のトランジスタ
ＴＲ８第８のトランジスタ DESCRIPTION OF SYMBOLS 11 1st inversion input terminal 12 1st input terminal 13 2nd input terminal 14 2nd inversion input terminal 21 Output terminal 31 High potential power supply terminal, 1st high potential power supply terminal 32 3rd high potential power supply terminal 33 Second high potential power supply terminal 34 Low potential power supply terminal C Capacitor J1 First constant current source J2 Second constant current source R1 First resistor R2 Second resistor R3 Third resistor TR1 First transistor TR2 2nd transistor TR3 3rd transistor TR4 4th transistor TR5 5th transistor TR6 6th transistor TR7 7th transistor TR8 8th transistor

Claims

The drain of the first transistor and the drain of the second transistor are commonly connected to one end of the second resistor, and the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, 4 transistors are commonly connected to one end of the first resistor, the source of the first transistor is connected to the drain of the fifth transistor, the drain of the second transistor and the third transistor The drain is commonly connected to the output section, the source of the second transistor is connected to the drain of the sixth transistor, the source of the third transistor is connected to the drain of the seventh transistor, and the fourth transistor The source of the transistor is connected to the drain of the eighth transistor, and the gate of the fifth transistor is the first transistor The source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the gate of the sixth transistor is the first input unit. The gate of the seventh transistor is connected to the second input section, and the source of the seventh transistor and the source of the eighth transistor are commonly connected to one end of the second constant current source. The gate of the eighth transistor is connected to a second inverting input, the other end of the first resistor and the second resistor is connected to a high potential power source in common, and the first constant current source The other end of the second constant current source and the other end of the second constant current source are commonly connected to a low potential power source.

The gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are connected in common to the second high potential power source, and the drain of the first transistor and the second transistor 4 drains are commonly connected to a first high-voltage power supply, the drains of the second transistor and the third transistor are commonly connected to an output section, and the source of the first transistor is Connected to the drain of the fifth transistor, the source of the second transistor is connected to the drain of the sixth transistor, the source of the third transistor is connected to the drain of the seventh transistor, and the fourth transistor The source of the transistor is connected to the drain of the eighth transistor, and the gate of the fifth transistor is the first transistor The source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the gate of the sixth transistor is the first input unit. The gate of the seventh transistor is connected to the second input section, and the source of the seventh transistor and the source of the eighth transistor are commonly connected to one end of the second constant current source. The gate of the eighth transistor is connected to the second inverting input unit, and the other end of the first constant current source and the other end of the second constant current source are commonly connected to a low potential power source. An LD driver circuit characterized by the above.

The gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are connected in common to one end of the first resistor, and the other end of the first resistor is connected to the first resistor. 2, the drain of the first transistor and the drain of the fourth transistor are commonly connected to one end of the second resistor, and the other end of the second resistor is connected to the first high potential power source. Connected to a voltage power source, the drain of the second transistor and the drain of the third transistor are connected in common to the output section, the source of the first transistor is connected to the drain of the fifth transistor, and The source of the second transistor is connected to the drain of the sixth transistor, the source of the third transistor is connected to the drain of the seventh transistor, and the fourth transistor The source of the transistor is connected to the drain of the eighth transistor, the gate of the fifth transistor is connected to the first inverting input, and the source of the fifth transistor and the source of the sixth transistor are shared. Connected to one end of a first constant current source, the gate of the sixth transistor is connected to a first input section, the gate of the seventh transistor is connected to a second input section, and The source of the transistor and the source of the eighth transistor are commonly connected to one end of a second constant current source, the gate of the eighth transistor is connected to a second inverting input portion, and the first constant current is supplied. An LD driver circuit, wherein the other end of the source and the other end of the second constant current source are commonly connected to a low potential power source.

One end of the first resistor is connected in common to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor, and one end of the capacitor. The other end and the other end of the second resistor are commonly connected to a high potential power source, the drain of the first transistor and the drain of the fourth transistor are commonly connected to one end of a second resistor, and the second resistor The drain of the first transistor and the drain of the third transistor are commonly connected to the output section, the source of the first transistor is connected to the drain of the fifth transistor, and the source of the second transistor is the sixth Connected to the drain of the transistor, the source of the third transistor is connected to the drain of the seventh transistor, and the source of the fourth transistor. Is connected to the drain of the eighth transistor, the gate of the fifth transistor is connected to the first inverting input, and the source of the fifth transistor and the source of the sixth transistor are commonly connected to the first transistor. The gate of the sixth transistor is connected to the first input portion, the gate of the seventh transistor is connected to the second input portion, and the seventh transistor has a gate connected to the first input portion. The source of the eighth transistor is commonly connected to one end of a second constant current source, the gate of the eighth transistor is connected to a second inverting input, the other end of the capacitor and the second transistor An LD driver circuit, wherein the other end of one constant current source and the other end of the second constant current source are commonly connected to a low potential power source.

One end of the first resistor is connected in common to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, the gate of the fourth transistor, and one end of the capacitor. The other end is connected to a second high potential power source, the drain of the first transistor is connected to one end of a second resistor, the other end of the second resistor is connected to the first high potential power source, The drain of the second transistor and the drain of the third transistor are commonly connected to the output section, the drain of the fourth transistor is connected to one end of the third resistor, and the other end of the third resistor Is connected to a third high potential power source, the source of the first transistor is connected to the drain of the fifth transistor, and the source of the second transistor is connected to the drain of the sixth transistor. The source of the third transistor is connected to the drain of the seventh transistor, the source of the fourth transistor is connected to the drain of the eighth transistor, and the gate of the fifth transistor is the first inverting input. The source of the fifth transistor and the source of the sixth transistor are commonly connected to one end of the first constant current source, and the gate of the sixth transistor is connected to the first input unit. The gate of the seventh transistor is connected to a second input portion, the source of the seventh transistor and the source of the eighth transistor are commonly connected to one end of a second constant current source, The gate of the eighth transistor is connected to the second inverting input, and the other end of the capacitor, the other end of the first constant current source, and the other end of the second constant current source are commonly low. It was connected to the position power, LD driver circuit according to claim.