JP4357594B2 - Pack data processor in transport data packet assembly system - Google Patents

Description

動作状態の種々の例（表１のケース１〜６）に関するＷ ＥＮ１、Ｗ ＥＮ２およびＷ ＺＥＲＯを生成するための真理表が、図３に示されている。これについては図５乃至図１６との関連で後述する。表１用のアルゴリズムが付録Ａに記載されている。制御器２６の出力信号は、出力ワード制御信号として図４に示されるデータ組み立て回路に供給される前に、出力バッファレジスタ２８に供給される。
図４のデータ組立て回路は、図１のデータパック器１２の出力回路を構成している。即ち、データ組立て回路は、図示のような回路構成で、論理積ゲート４２および４４、論理和ゲート４６およびＤ型フリップフロップ（Ｄ Ｆ／Ｆ）４３および４５を具えている。３２ビット幅のパック・データワードPacked Data Wordが論理積ゲート４２を介してデータＦＩＦＯに送られ、前段のパック器回路から供給されるワードレディ信号Word Readyが、論理積ゲート４４を介して送られ、図１のデータＦＩＦＯ１６用のデータ書き込みイネーブル信号Data Write Enableになる。パック・ワード状態制御器２６から供給されるデータ書き込み制御信号Ｗ ＥＮ１、Ｗ ＥＮ２およびＷ ＺＥＲＯ（図２Ａ）が図示のようにフリップフロップ４３と４５および論理和ゲート４６に供給される。Ｗ ＥＮ２は現在のワードに関連する最終ワード・フラグLast Word Flagを示し、Ｗ ＥＮ１は次のクロックサイクルにおけるワードに関連する最終ワード・フラグLast Word Flagを示す。Ｗ ＺＥＲＯ制御は、Ｗ ＥＮ１によって最終ワードのフラグが立てられる擬似最終ワードPseudo Last Wordの生成を示す（表１のケース４）。このケース４においては、擬似最終ワードと呼ばれる全ＺＥＲＯのワードがパック・データワードストリームPacked Dataに挿入され、データＦＩＦＯ１６に書き込まれる。組立て回路の論理積ゲート４４へのワードレディ入力信号Word Readyが保持レジスタ３６（図２Ｃ）によって供給されて、処理可能なパックされた３２ビットが存在することを示す。
次に、図５乃至図１６に例示された最終ワードの発生の例について説明する。これらの例のあるものは、ＰＡＦの前後の位置に存在する長さがゼロのＮＯ−ＯＰワードの作用を示している。
図５および図６は表１のケース５に該当する相異なる例を示している。図５においては、パケットは次のパケットへのセグメント化を行って（即ち、アキュムレータのビット値が９６０より大きい）完全パケットを形成している。図６においては、パケットは正確にパケットの境界の位置で完全パケットを形成し（即ち、アキュムレータのビット値が９６０に等しい）、次のパケットへのセグメント化を行うことなくまたは残余データを生じることなく完全パケットを形成している。このいずれのケースにおいても最終ワード・フラグLast Word Flagはパケット完全Packet Completeの発生と同時に発生する。この最終ワード・フラグLast Word Flagは、ＰＡＦが存在しないときは真ゼロTrue Zeroおよび残余Remnantの各表示を考慮せずに独立に発生される。一方、ＰＡＦが存在する場合は、最終ワード・フラグLAST Word Flagは真ゼロTrue Zeroおよび残余Remnantの各表示を考慮して発生される。
図７および図８は、表１のケース２を例示している。図７において、パケットが完全になった直後にセグメント化を行わずにＰＡＦが発生し、その後に３２ビットのＰＳコードワードが続く。図８は、挿入された３個の長さゼロのノー・オペレーション（ＮＯ−ＯＰ）コードワードがＰＳコードワードに先行して存在することを除けば、図７と同様である。図７および図８において、ＰＡＦはパケット完全信号Packet Completeと時間的位置が一致して発生し、パケットは次のパケットに残余データのセグメント化を生じることなく終了する。図７は、３２ビット長のＰＳコードワードが直後に続いている、より一般なケースを示す。図８は、ＮＯ−ＯＰワードが挿入されることが許容されることを示している。
図９は表１のケース６ａに関係する図であり、この図においてＰＡＦはパケット完全信号Packet Completeと位置が一致せずにずれて発生している。ＰＡＦは、セグメント化を伴わずにパケットが完全になった後のＮＯ−ＯＰワードの後に生じ、その後にＰＳコードワードが続く。このケースにおいては、最終ワード表示（フラグ）Last Word Indicatationがパケット完全信号Packet Completeと関連して発生するが、アキュムレータ状態が０（ゼロ）の値でアイドル状態になっていて真ゼロ表示True Zeroが存在することになるので、最終ワード表示（フラグ）Last Word IndicationはＰＡＦと関連して発生することはない。
図１０および図１１は表１のケース１を例示す。図１０において、ＰＡＦは、パケットが完全になった直後にセグメント化が生じた状態で発生し、その後にＰＳコードワードが続く。図１１は、挿入ＮＯ−ＯＰワードがＰＳコードワードに先行して存在することを除けば、図１０と同様である。この場合、セグメント化される残余データが存在するので、２つの最終ワード・インジケータ（フラグ）Last Word Indivatorが必要になる。その中の一方の最終ワード・インジケータ（フラグ）Last Word Indivatorがパケット完全Packet Completeの期間に生じ、そのうちの他方の最終ワード・インジケータ（フラグ）Last Word Indicationは、セグメント化が生じたためにＰＡＦの１クロック期間後に生じる。
図１２、図１３および図１４は表１のケース３を例示す。これらの例においては、ＰＡＦは、パケット形成期間中のある位置で発生するが、ワード境界上では発生せず（即ち、次のワードへのセグメント化が生じる）、パケット完全表示Packet Completeとは位置が一致しない。次いで、ワードが部分的に開始された結果（セグメント化による）、最終ワード信号Last Wordは、通常、ＰＡＦの後にくる次のクロック期間に発生する。図１２において、ＰＡＦは、パケットがセグメント化を行った状態で完全になった後の数個のＮＯ−ＯＰワード後に発生し、その後にＰＳコードワードが続く。図１３において、ＰＡＦは、ワードが完全になると同時にセグメント化が生じた状態で発生し、その後にＰＳコードワードが続く。図１４において、ＰＡＦは、ワードが完全になった後で、かつ数個のコードワードによってセグメント化が生じた後に発生する。
図１５および図１６は、表１のケース４を例示し、特別な種類の最終ワードである擬似最終ワードPseudo Last Wordを生成することの必要性を説明するための図である。このケースにおいて、ＰＡＦは、１つのワードがセグメント化を生じることなく、即ち３２の倍数のワード境界上でワードが完全になった直後（図１５）またはその少し後の時間（図１６）に発生する。このケースにおいて、完全ワードは、それが最終ワードであったという情報が得られる前に（ＰＡＦの後に供給される）既に供給されていることを前提にしている。その場合は、全ゼロ擬似最終ワードPseudo Last Wordが形成され、供給される。これが許容される理由は、ＭＰＥＧでは、開始コードワードの前に任意の数のゼロ（０）が先行して続くことを許容し、ＰＡＦの発生によりＰＳコードワードが次ぎに来ることが保証されているためである。さらに、これらのケースでは、パケットの不足分を、データ／ヘッダ合成器によってゼロ値ビット（null）・ワードで補填している。１つのゼロワードが発行されて、それを最終ワードとして擬似的にマークするので、このケースにおいて、合成器は１つの少ないワードを供給することになる。図１５において、ＰＡＦは、ワードが完全になると直ぐに発生し（セグメント化が生じない状態で）、その後にＰＳコードワードが続く。図１６においては、ワードが完全となった（セグメント化を生じない状態で）後に、挿入ＮＯ−ＯＰワードが続く。その後に、ＰＡＦが発生し、さらにその後にＰＳコードワードが続く。
図１７は、データ／ヘッダ合成器１５（図１）の詳細な構成を示す。ヘッダ成分は、ヘッダがヘッダ発生器１８によって生成されたときは常に、ヘッダ書き込みイネーブル信号Header Write Enableに応答して、ヘッダＦＩＦＯ７０に書き込まれる。同様に、パック・データワードは、そのワードがデータパック器１２によって生成されたときに、データ書き込みイネーブル信号Data Write Enableに応答して、データＦＩＦＯ７２に書き込まれる。データパック処理によって生成された最終ワード・インジケータLast Word Indicatorは、その最終ワードが３０番目のワードであるか否かとは関係なく、パケット中に最終ワードを伴って生じる。ヘッダＦＩＦＯ７０およびデータＦＩＦＯ７２の各ユニットのヘッダ出力およびデータ出力が多重化器（マルチプレクサ）７６によって共通バス上に多重化されて供給され、さらに出力レジスタ７８に供給される。図１９に示されているように、出力レジスタ７８は、データレディ信号Data Ready、パケットデータPacket Data、ヘッダHeader、およびヘッダ・インジケータHeader Indicatorをレートバッファ７１３および７１４に供給する。多重化器７６は、ＦＩＦＯ状態制御器７４から供給されたゼロ発行信号Issue Zeroに応答して、命令（コマンド）に従ってゼロワードを発行することができる。
２つのＦＩＦＯ７０および７２の両方のユニット、多重化器７６および出力レジスタ７８は、ステート・マシン（状態マシン）である制御器７４の指示を受ける。パワーオン（電源オン）または同様に作用する動作の再開の後で、制御器７４は処理可能なヘッダが現れるのを待つ。処理可能なヘッダは、データレディ・インジケータData Ready Indicatorおよびヘッダ・インジケータHeader Indicatorと共に多重化器７６の出力バスに送られる。次いで、制御器７４は、最終ワード・インジケータLast Word Indicatorが出現するまで、処理可能なデータが存在する限りそのデータを抽出してデータＦＩＦＯ７２の状態を制御する。伝送された各データはデータレディ・インジケータData Ready Indicatorを伴い、そのデータレディ・インジケータData Ready Indicatorは出力レジスタ７８に送られる。最終ワード・インジケータLast Word Indicatorが出現した時に、既に３０個のデータワードが供給されていたことが判明すれば、制御器７４はさらに処理可能な情報が存在するか否かについてヘッダＦＩＦＯ７０を再検査する。３０個未満のデータワードが供給されたときは、制御器７４は、ゼロ発行命令Issue Zeroを用いて多重化器７６に指令して、パケットの不足分を補うためにゼロワードを発行させる。そのようなゼロワードは、全てデータレディ・インジケータData Ready Indicatorを伴って供給される。伝送すべきヘッダとデータがない場合は、制御器７４は、多重化器７６に指令して、処理可能なデータが存在しない期間、データレディ・インジケータData Ready Indicatorなしでゼロワードを発行させる。上述のようなステートマシンで駆動される合成器１５の動作を表すフローチャート（状態遷移図）が図１８に示されている。データレディ・インジケータData Ready Indicatorおよびヘッダ・インジケータHeader Indicatorは、出力レジスタ７８を通して図１９のレートバッファ７１３および７１４に送られる。これらのインジケータは、バス上にデータおよびヘッダ情報が存在することをレートバッファに伝え、ヘッダ/データ記録（registration）を維持してレートバッファの後段で前進型誤り訂正（ＦＥＣ）符号化およびデータ・インターリーブ（間挿）を行わせる。このシステム（図１９）において、ＦＥＣ処理およびインターリーブ処理を行うには、ヘッダによって表されるデータパケットが送られる前に、最初にヘッダを送る、即ち１つのヘッダを送ってレートバッファへの伝送を開始する必要がある。ヘッダＦＩＦＯ７０およびデータＦＩＦＯ７２から送られた空きフラグ信号Empty Flagは、ヘッダおよびデータワードがそれぞれ存在しない（nullである）ことを示し、これによってステートマシンである状態制御器７４がアイドル状態になる。この状態が図１８に、状態０および状態１における”ヘッダなし”および“ワードなし”の状態として示されている。関連する読みとりイネーブル信号Read EnableがヘッダＦＩＦＯ７０またはデータＦＩＦＯ７２にそれぞれ送られると、制御器７４から供給されるヘッダ／データ選択信号Header/Data Selectが多重化器７６に指令して、ヘッダＦＩＦＯ７０のユニットのヘッダ出力Header OutputまたはデータＦＩＦＯ７２のユニットのデータ出力Data Outputのいずれかを出力レジスタ７８の入力側の信号バスに切り換え接続される。不完全な短縮パケットにはゼロワードを付加して所定の３０個のワードのデータパケットが生成され、そのデータパケットが出力バッファ７８に供給される。この出力バッファ７８の容量は、前段のヘッダバッファ７０およびデータバッファ７２の容量よりもかなり大きい。これらのバッファは、割り込みを受けずに効率的にデータを受け取り、処理する。このような割り込みを受けない動作構成とすることによって、タイミングおよび同期化の機能が大幅に簡単になる。その機能は、例えば、クロック停止／開始における難しい同期化処理を不要にすることにより簡単にできる。
所定長の完全パケットは、上述のように必要数の空ワードを付加することによって適正に利用できるようになる。このような完全パケットを使用することによって、例えば可変長コードワード・システム等における任意のデータ状態においてもデータのサーチおよび同期化が可能になる。開始コードワード、特にＩフレーム開始コードワードは、ＭＰＥＧと互換性（相互運用性）のあるデータストリームにおける固有の再同期化点となる。開始コードワードはパケット境界に出現する。本明細書に記載したシステムにおけるゼロ値ビットの空ワードを用いて、切り捨てられたデータパケットをパケット完全化し、パケット境界を決定することによって、そのようなパケット境界の処理を行うことができる。ＭＰＥＧ標準では、開始コードワードの前に任意の数のゼロワードが来ることを許容しており、受信機／デコーダはゼロ値ビットのnullワードを無視するようになっている。この例において、出力バッファ７８は、その容量が大きく、時間的耐性（連続同一値に対する耐性）が高く、従ってnullワードパック動作を実行するのに適した手段を構成している。ここで、パケット境界におけるＰＡＦの出現とＰＳコードワードの出現との間においてnullワードをパックするために利用できる時間は僅かしかない（例えば１クロックサイクル）ことに留意すべきである。
図１９は、トランスポート・プロセッサ部において本発明に従う装置を用いた高解像度テレビジョン（ＨＤＴＶ）符号化システムを例示している。図１９は、単一のビデオ入力信号を処理するシステムを示す。但し、輝度（ルミナンス）成分およびクロミナンス成分は別々に処理され、輝度の動きベクトルを用いて圧縮クロミナンス成分が生成されることが分かる。圧縮された輝度成分およびクロミナンス成分は、コードワード優先度をパース（構文解析）する前に、インターリーブされてマクロブロックが形成される。図１９のシステムに関する別の情報が、アカンポーラ氏外の米国特許第5,168,356号に記載されている。図２０Ａに示された画像フィールド／フレームのシーケンス（列）は、図２０Ｂに従うフィールド／フレームを再配列する回路７０５に供給される。その再配列されたシーケンスは圧縮器７１０に供給される。この圧縮器７１０は、ＭＰＥＧ形式のフォーマットに従って符号化された圧縮されたフレームのシーケンスを生成する。そのフォーマットは階層構造になっており、それが図２２に簡略形式で例示されている。ＭＰＥＧ形式の階層構造フォーマットは、各別のヘッダ情報をそれぞれ有する複数の階層からなる。各ヘッダは、開始コードワード、各階層に関連するデータおよびヘッダ拡張を行うための項目（プロビジョン）を正規のヘッダ形式として含んでいる。
このシステムによって生成されるＭＰＥＧ形式の信号について説明すると、（ａ）ビデオ信号の連続的画像フィールド／フレームがＩ，Ｐ，Ｂ符号化シーケンスに従って符号化され、（ｂ）画面レベルで符号化されたデータはＭＰＥＧ形式のスライスまたはブロック群の形式で符号化される。その場合、各フィールド／フレーム当たりのスライス数は種々の値をとり、各スライス当たりのマクロブロック数も種々の値をとる。Ｉ符号化フレームは、画像再生を行うときにＩフレーム圧縮データだけを用いて処理できるようにイントラフレーム圧縮されている。Ｐ符号化フレームは前方動き補償予測法に従って符号化されており、Ｐフレーム符号化データは、現在のフレーム、および現在のフレームの前に発生するＩまたはＰフレームから生成される。Ｂ符号化フレームは、双方向動き補償予測法に従って符号化される。Ｂ符号化フレームデータは、現在のフレーム、および現在のフレームの前および後に発生するＩおよびＰフレームから生成される。
現在のシステムの符号化出力信号は、フィールド／フレーム群、またはボックスＬ２行（図２２）に例示されている画像群（ＧＯＰ）にセグメント化される。各ＧＯＰ（Ｌ２）はヘッダを含んでおり、ヘッダの後には画像データのセグメントが続く。ＧＯＰヘッダは、水平方向および垂直方向の画面サイズ、アスペクト比、フィールド／フレーム・レート、ビット・レート、などに関連するデータを含んでいる。
各画像フィールド／フレームに対応する画像データ（Ｌ３）は、ピクチャヘッドを含んでいて、ピクチャヘッダの後にはスライスデータ（Ｌ４）が続く。ピクチャヘッドはフィールド／フレーム数およびピクチャ・コード・タイプを含んでいる。各スライス（Ｌ４）は、スライスヘッダを含んでいて、スライスヘッダの後には複数のデータ・ブロックＭＢｉが続く。スライスヘッダは、群番号および量子化パラメータを含んでいる。
各ブロックＭＢｉ（Ｌ５）は、マクロブロックを表し、ヘッダを含んでおり、ヘッダの後に動きベクトル（ＭＶ）および符号化係数が続く。ＭＢｉヘッダは、マクロブロック・アドレス、マクロブロック・タイプおよび量子化パラメータを含んでいる。符号化係数は階層Ｌ６に例示されている。各マクロブロックは、４つの輝度ブロック、１つのＵクロミナンスブロックおよび１つのＶクロミナンスブロックからなる合計６個のブロックを含んでいる（図２１参照）。１つのブロックは、ピクセルのマトリックス、例えば８×８のマトリックスを表していて、このマトリックスに対して離散コサイン変換（ＤＣＴ）が実行される。その４つの輝度ブロックは、例えば１６×１６のピクセル・マトリックスを表す２×２の隣接輝度ブロックのマトリックスである。クロミナンス（ＵおよびＶ）ブロックは、４つの輝度ブロックの領域全体と同じ領域を表している。すなわち、圧縮の前に、クロミナンス信号は、輝度に対して水平方向および垂直方向に２つの係数（１／２）でサブサンプル（subsample）される。１つのスライスのデータは、隣接したマクロブロック群として表される領域に対応する画像中の長方形部分を表すデータに対応する。１つのフレームは、３６０個のスライス、すなわち垂直方向の６０スライス×水平方向の６スライスからなる。
ブロック係数は、ＤＣＴによって１回につき１ブロック分供給される。まずＤＣ係数が発生し、ＤＣ係数の後にその相対的重要度順に各ＤＣＴ ＡＣ係数が続く。ブロック終了コードＥＯＢ（end-of-block）が、連続的に発生するデータの各ブロックの最後に付加される。
図１９において、圧縮器７１０から供給されるデータは、データを高優先度（ＨＰ）成分と標準優先度（ＳＰ）成分とにセグメント化するトランスポート・プロセッサ７１２に供給される前に、優先度プロセッサ７１１により処理される。これらの成分は、レートバッファ７１３および７１４を介して各前進型誤り訂正符号化ユニット７１５および７１６に結合される。レートバッファは一時的にパニック・データおよびヘッダを記憶し、その後ＦＥＣ誤り訂正符号化回路はそのパック・データおよびヘッダを抽出する。レート（rate）制御器７１８は、バッファ７１３、７１４と協働して、圧縮器７１０から供給されるデータの平均データ・レートを調整する。その後、信号が伝送モデム７１７に結合され、そのＨＰおよびＳＰデータは、標準６ＭＨｚのＮＴＳＣ方式のテレビジョン・チャンネル内の各搬送波を直交振幅変調する。

The present invention relates to the field of digital signal processing, and more particularly to transport data packets used, for example, for transmitting MPEG-type data encoded in high-definition television systems. The present invention relates to an assembling method and apparatus.
Background of the invention U.S. Pat. No. 5,168,356 issued to Acampora et al. Describes a system for processing high-definition television (HDTV) signals according to MPEG-type variable length coding. . MPEG is a standard encoding format determined by the International Organization for Standardization (ISO). The standard is “International Organization for Standardization” ISO / IEC DIS 11172, Coding for Moving Pictures and Associated Audio for Digital Storage Media, Rev. Nov. .23, 1991, and is referred to herein to describe a general encoding format, and in a system outside of Acampola, codewords (codewords) contain data. Priorities are given to represent high and low priority information in the stream, and the codeword data stream is sent to the transport processor, which transmits the codeword data. , Each with a header section and packed data payload section Pack in the form of transport cells containing a down, supplies a high data stream priority and low priority output data stream.
The main function of the transport processor is to pack the variable-length code word data supplied (issued) by the priority processor in the previous stage into a packed data word format. The accumulated packed word is called a data packet, and a transport header is added in front of it.
The transport packet format facilitates resynchronization and signal recovery at the receiver. For example, if the header data is added even after the signal has been destroyed or broken due to interference in the transmission channel, the receiver can re-entry the data stream if the transmitted data is lost or corrupted. Points can be determined based on the header data. Data synchronization in an MPEG-compliant decoder is also performed by a GOP (Group of Pictures) having a starting point at the packet boundary. As will be seen later, a GOP is a series of one or more pictures or frames that allow a random access to a sequence of encoded video bitstreams (columns). . Resynchronization can also be facilitated by responding to the PS codeword of an intra-coded I frame and placing the PS codeword at the packet boundary in an MPEG standard compliant system, for example. If an apparatus according to the principle of the present invention is used, transport packets can be easily formed and processed.
SUMMARY OF THE INVENTION In accordance with the principles of the present invention, an imperfection having fewer words than a predetermined number in a system for transferring variable length codewords (e.g., MPEG codewords) in a data packet for transfer. A no-op “zero word” is packed into a new data packet to create a fixed-length packet, and a boundary between packets in which a predetermined code word appears is defined.
In the preferred embodiment disclosed, a special codeword, packet alignment flag (PAF), is inserted into the MPEG data stream to indicate the beginning of a GOP. . The PAF is placed immediately before the 'image start' codeword for the intra-frame encoded “I” frame that starts the GOP. The PAF informs that the appearance of the 'PS' codeword is imminent and has been over one clock cycle, during which one “housekeeping” function is activated at the beginning of the next packet. Performed before the start 'codeword appears. These housekeeping functions include, for example, resetting the accumulator, checking the status of the header, and setting the 'last word indicator' for the data packet being built when the PAF appears. Is to occur. Since the GOP is supposed to start at the packet boundary, when a PAF appears, the data packet being built is terminated. Such a termination may result in a shortened packet containing stuffed words, less than the specified number. This shortened data packet is filled with null (zeroed bits) words to form a complete data packet with a specified number of words, and the interpacket boundary where the image start codeword appears Determine. Thirty 32-bit fixed-length words form one data packet, and this data packet is preceded by one 32-bit header.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a partial block diagram of a video signal encoder comprising a data word controller, a data packer, and a data / header synthesizer according to the present invention.
2A, 2B and 2C show details of the word controller and data packer of FIG.
FIG. 3 is a truth table for the operation of the word state controller shown in FIG. 2A.
FIG. 4 shows details of the pack data assembly circuit.
5 to 16 show examples of the last word occurrence.
FIG. 17 shows details of the data and header synthesizer shown in FIG.
FIG. 18 is a state transition diagram regarding the operation of the state controller shown in FIG.
FIG. 19 is a block diagram of a high resolution television encoding system including an apparatus according to the present invention.
20A and 20B are image representations of a sequence of image fields / frames of an encoded video signal.
FIG. 21 is an image representation of data block generation formed by the encoding / compression apparatus in the system of FIG.
FIG. 22 is a generalized image representation of the data format formed by the encoding / compression device in the system of FIG.
Detailed Description of the Drawings FIG. 1 is a block diagram of a data packer 12 and a pack dataword controller 10 of a transport processor. As mentioned above, the main function of the transport processor is to pack variable length code word data into fixed length (eg, 32 bit) data words. The accumulated 30 data words constitute a data packet, and finally a transport header is added before the data packet. As will be described later with respect to FIG. 19, such a transport processor is used in a system for processing compressed video signals in MPEG format. Other features of MPEG format and processing will be described later in connection with FIGS.
The controller 10 monitors the cumulative value of the length data word in relation to the PAF (Packet Alignment Flag), and completes (completes) the integrity of the 32-bit data word assembled from the stream of variable length code words. ) Confirm the integrity (completion) of the 960-bit data packet. The length data Length is a parallel 6-bit word that matches the length of the variable-length code word, and defines the length of the variable-length code word. The binary value of the length word Length indicates the number of bits matching the length of the variable length codeword that actually represents the MPEG codeword to be transported (transmitted). Each variable-length codeword appears on a 32-bit wide bus and has a variable number of valid bits (1-32) representing an MPEG format code.
The PAF is generated by the input processor 14 and appears one codeword before the PS (Picture Start) codeword of the MPEG type “I” (intra-coded) frame at the start of the GOP (Group of Pictures). It is supposed to be. The PAF is generated by detecting the presence of an I frame / PS codeword by a digital comparator. The unit of the input processor 14 includes a signal delay circuit for processing the PS code word and the PAF so that the PAF is generated in the clock period of the code word immediately before the I frame / PS code word. It has become. The delay circuit ensures that the output signals supplied to the units of the packed word controller 10 and the data packer 12 have an appropriate time synchronization relationship.
The word address Word Address is sent to the data packer 12, and the data packer 12 receives the variable length codeword VLC to be packed and ensures that the input variable length codeword is properly connected. Also, a word control signal Word Control is sent to the packer 12 to indicate the presence of a short word, mark (display) the last word in the packet, and the proper alignment position with the associated transport header added So that a sequence of 30 packed data words is obtained. The controller 10 tracks and monitors the completeness (completion) of the packet by accumulating the binary value of the length word Length. Each length value represents the number of significant bits in the associated codeword. One packet is complete (completed) when 960 bits are accumulated. The starting point setting or initialization of the count value (count) is performed by the appearance of the PAF, and the PAF resets the internal accumulator in the controller 10.
Data packer 12 receives variable length codewords (VLC) via a 32-bit parallel data bus. The valid bits are packed into 32-bit words according to the supervisory control signal supplied from the controller 10. Further, concatenation is performed so as to accept the final MPEG format (bit serial transmission order. The pack data supplied from the unit of the data packer 12 is the variable word rate (speed) of the data and header combiner 15. The data is transferred to the input FIFO data buffer (data FIFO) 16. The synthesizer 15 receives the data write enable signal Data Write Enable from the data packer 12, and the data packer 12 stores the FIFO data buffer 16 in the synthesizer 15. Enable to enable valid data to be written to the FIFO data buffer 16. The data packet is fully packetized when such 30 word transfers are completed, unless the PAF forces a short packet. The state supplied by the data pack unit 12 is Word Indicator Last Word Indicator marks the last word in a packet to be shortened by the appearance of 30-th word mark, or PAF in normal packet in this example.
As long as there are pack data words that can be processed, the pack data words are transferred to the data / header combiner 15. Similarly, a transport header is sent from the header generator 18 to the input FIFO header buffer (header FIFO) 17 of the synthesizer 15 as long as there is a processable transport header. Information used by the header generator 18 to form the header is obtained from the input processor 14 and the word controller 10. The header write enable signal Header Write Enable indicates that there is a processable header, and enables the FIFO 17 so that the header is written into the FIFO 17. The combiner 15 adds a header before each packed data payload and sends the resulting transport packet or block to the output rate buffer as shown in FIG. Further, the synthesizer 15 supplies an output data ready data ready signal indicating that the packed data word or the transport header is in a send ready (send ready) state. The header indicator signal Header Indicator indicates a clock cycle when the header is transmitted. This signal functions as a transport packet boundary marker so that subsequent operations such as Forward Error Correction (FEC) are properly supplied to the transport cell.
Each header contains information about the data in the data packet associated with that header. The header information provides data assembly and synchronization at the receiver. The header information includes information such as a service type (eg, audio, video, data), a frame type, a frame number, and a slice number, for example. This type of header and its processing is described in relation to an HDTV digital signal processing system using MPEG type signal coding in US Pat. No. 5,168,356 to Acampola et al.
A data packet may contain less than 30 packed data words, ie 1 to 29 words, in this example. The PAF supplied by the input processor 14 appears immediately before the PS codeword for the intra-coded I frame when the GOP starts, as will be described later in connection with FIGS. A new packet is always started by a PS codeword for an intra-coded frame, and a PAF preceding the previous one indicates the end of the data packet and the start of the new packet. This PS codeword packet alignment or alignment is useful for fast acquisition of data streams at the receiver. If PAF occurs during the formation of a fixed length word, a shortened data packet will be formed. The remaining bits in the packed word being assembled are filled with a plurality of "zero value bits" (1-31) in the data packer 12. Further, the remaining words in the data packet are similarly filled with a plurality of “zero value words” (1 to 29) in the synthesizer 15, and the size of the transport packet is maintained at a predetermined length. Such a “zero word fill” (full word) request is indicated by the occurrence of the last word indicator Last Word Indicator before 30 word data has been transferred to the combiner 15.
It is important to properly identify the last word Last Word in the data packet. The final word Last Word confirms that the packet assembled with the associated transport header is properly recorded (accommodated). The last word “Last Word” indicates the presence of a packet filled in an MPEG GOP boundary (ie, an intra-coded frame). GOP boundaries are important for resynchronization, for example in a television receiver / decombiner after a channel change. Determining the last word Last Word is not trivial. For example, when the packet is complete (completed), and when complete, whether the packet is being segmented or data segmented into the next packet The final word Last Word is determined according to the specific information. The last word has a state when the last word Last Word is a word formed during the current clock period and a state when the last word Last Word is a word to be formed during the next clock period. Exists.
The following are some specific examples of forming the final word Last Word. If there is no PAF when the packet is complete, the last word (the 30th word in this example) is the last word and is marked as the last word by the last word indicator Last Word Indicator. . This is an example of the “true” final word Last Word. PAF occurs when a packet does not have bits to segment into the next packet, ie when a word ends exactly at a packet boundary. Since the final word of the complete packet is actually the final word, it is marked as the final word Last Word. This is another example of a “true” final word Last Word. PAF also occurs when a packet is complete with the remaining few bits segmented into the first word of the next packet. In this case, two consecutive last words Last Word are formed and marked as such. First, the final word of the complete packet is marked as Last Last (the “true” final word Last Word). The first word of the next packet is then marked as the last word Last Word because the packet is forcibly shortened by PAF. In the case of a shortened packet like the latter, the last word Last Word appears before 30 words have been transmitted, and then “zero words” are filled to make the packet a complete packet. Next, other examples of the last word Last Word will be given. PAF also occurs when a packet is in the state of an incomplete packet being assembled. If the internal word is word complete with the remaining bits being segmented into the next word, that partial word becomes the last word Last Word. A difficult situation arises, especially when the packet is complete with an incomplete packet being assembled and the internal word is complete without any bits being segmented into the next word. That is, if an internal word is sent to the data / header synthesizer before later data (ie, the appearance of a PAF) indicates that this word is the last word, this word is the last word. It is already too late to properly mark In this case, a zero word called a “pseudo” final word is generated and displayed as the final word. Such a pseudo-final word consists entirely of zero bits. This is different from, for example, part of the segmented (incomplete) final word being filled with 0 bits. The above example or another example will be described with reference to FIGS.
Among the important features of the system disclosed in the following description is the generation of a zero length PAF. A PAF with this length of 0 indicates that the beginning of the GOP will appear soon after, generates and marks the last word Last Word in the data packet and, if necessary, the pseudo last word Pseudo Last Word And specific signals can be easily generated in relation to various states of occurrence of the last word Last Word.
FIG. 2A shows details of the controller 10 of FIG. The controller 10 includes an accumulator 20 in a feedback circuit having a modulo 960 circuit 22. The feedback path includes a buffer register 23 that holds the newly accumulated value at the end of each length Length input cycle. The input PAF word and the length word Length are sent to the modulo unit 22 and the accumulator 20 via the input register 24, respectively. The value of the length word Length is sequentially and continuously accumulated by the units of the accumulator 20, and the packet length is set to 960 bits by feedback synthesis of the accumulator 20 and the modulo 960 unit 22. The accumulator output supplied from the buffer register 23 represents the bit position in the packet and is sent to the packet state controller 25.
The packet state controller 25 receives the PAF from the input buffer register 24 and supplies (generates) an output signal necessary for generating a write command in the word state controller 26. When the accumulator bit count (bit count value) reaches 960 or more, the packet complete output signal Packet Complete is supplied to the word state controller 26. When the accumulator bit count does not indicate a word boundary (ie, when the bit count is not equal to an integral multiple of 32), the controller 25 generates an output residual signal Remnant. When the accumulator bit count is zero, a true zero output signal True Zero is provided. This true zero output signal is an important signal for making an accurate final word decision only when a PAF is present. The logic circuit that generates these signals is shown in FIG. 2B as described below.
When a zero-length empty codeword is received, ie, a zero-length word Length indicating the presence of a no-op (NO-OP) codeword, the accumulator 20 is idle and holds the final bit count. To do. There are exceptions to this rule, and the PAF may always force the accumulator value to zero regardless of the bit count. Another exception is when the packet forms a complete packet exactly at the packet boundary (ie, the accumulator count is 960). Then, in the next clock cycle, the accumulator count is corrected via the modulo 960 unit 22 to the binary value of the next length word Length. When the accumulator count reaches 960 or higher, the packet is complete.
In FIG. 2B, a 10-bit accumulator output representing the accumulated length is assigned to I0-I9. A packet is complete when the accumulated length of the packet codeword is greater than 960. When the four upper (MSB) bits I 6 -I 9 of the accumulator are in a logic one state, that state is indicated and the four bits are provided to the AND gate 30. When 10 bits of all accumulators are in the logic 0 state, true zero is displayed and the 10 bits are supplied to the OR gate 31. When the five lower (LSB) bits I 0 -I 4 of the accumulator are in the logic 0 (zero) state, a “no residue” state is indicated and the five bits are provided to the OR gate 32. The word address Word Address of the data packer is generated according to the six lower bits I0 to I5 of the accumulator. The AND gate array 34 forcibly sets the word address Word Address to the logic 0 state when the packet alignment flag (PAF) appears.
FIG. 2C shows details of the data packer 12 of FIG. A variable length code word is sent to the data shifter 35. As the data shifter 35, a barrel shifter such as model 74AS8838 manufactured by Texas Instruments can be used. To determine the proper position of the valid bits of the variable length codeword to be concatenated, a low order bit (LSB) portion of the length accumulator output is generated from the packet state controller 25 (see FIGS. 2A and 2B). The word address is sent to the data shifter 35 as a word address. When a 32-bit word is formed by concatenating variable length code words, the packed word is transferred to the holding register 36. A flag indicating whether or not there is pack data that can be processed is given by the word ready signal Word Ready supplied from the register 36, and the word is transferred to the data assembly circuit 37. The data assembly circuit 37 uses the control signals WEN1, WEN2 and WZERO supplied from the packed word controller 10 (FIG. 1) to enable data write enable and final word flag (indicator) Last Word. The pack data is supplied to the FIFO data buffer 16 in the data and header synthesizer 15 together with the flag.
After transmitting the last word in the packet so that the header of the next packet is inserted after the last word of the current packet, the next transport header is subsequently inserted in the combined data stream Is done. The header controller uses the Accumulator Output Accumulator Output (FIG. 2A) to indicate the position of certain codewords in the packet so that each position is described in the entry point field in the header. A logic array associated with the word state controller 26 and the data assembly circuit 37 generates a final word indicator Last Word Indicator and a flag that enables the data word to be written to the FIFO buffer. Table 1 below generates a final word according to PAF (Packet Alignment Flag), PC (Packet Complete), TZ (True Zero) and REM (Remnant Word Segmentation Indicator) which are inputs to the logical array. Indicates the action state. When the output signal of the controller 26 is supplied via the buffer register 28, an output signal is generated from the data assembly circuit 37. These signals are written to generate a write enable signal W EN1 indicating the last word appearing in the next clock cycle, a write enable signal W EN2 indicating the last word appearing in the current clock cycle, and a pseudo last word Psuedo Last Word. Contains the zero signal W ZERO. This pseudo last word Psuedo Last Word is generated when the occurrence of PAF coincides with the packet formation time point located at the internal code word data boundary of the incomplete packet.

A truth table for generating WEN1, WEN2 and WZERO for various examples of operating conditions (cases 1-6 of Table 1) is shown in FIG. This will be described later in connection with FIGS. The algorithm for Table 1 is described in Appendix A. The output signal of the controller 26 is supplied to the output buffer register 28 before being supplied as an output word control signal to the data assembly circuit shown in FIG.
The data assembly circuit shown in FIG. 4 constitutes the output circuit of the data packer 12 shown in FIG. That is, the data assembly circuit has AND gates 42 and 44, an OR gate 46, and D-type flip-flops (DF / F) 43 and 45 in a circuit configuration as shown. A packed data word having a 32-bit width is sent to the data FIFO via the AND gate 42, and the word ready signal Word Ready supplied from the packer circuit in the previous stage is sent via the AND gate 44. The data write enable signal Data Write Enable for the data FIFO 16 in FIG. Data write control signals WEN1, WEN2 and WZERO (FIG. 2A) supplied from the packed word state controller 26 are supplied to flip-flops 43 and 45 and an OR gate 46 as shown. W EN2 indicates the Last Word Flag associated with the current word, and W EN1 indicates the Last Word Flag associated with the word in the next clock cycle. W ZERO control indicates the generation of a pseudo last word Pseudo Last Word that is flagged by W EN1 as the last word (case 4 in Table 1). In this case 4, all ZERO words called pseudo final words are inserted into the packed data word stream Packed Data and written into the data FIFO 16. A word ready input signal Word Ready to the AND gate 44 of the assembly circuit is provided by the holding register 36 (FIG. 2C) to indicate that there are 32 bits of packed packable data.
Next, an example of generation of the last word illustrated in FIGS. 5 to 16 will be described. Some of these examples show the action of zero-length NO-OP words that exist before and after the PAF.
5 and 6 show different examples corresponding to Case 5 in Table 1. FIG. In FIG. 5, the packet is segmented into the next packet (ie, the accumulator bit value is greater than 960) to form a complete packet. In FIG. 6, the packet forms a complete packet exactly at the packet boundary (ie, the accumulator bit value is equal to 960) and produces residual data without segmentation into the next packet. Without forming a complete packet. In either case, the last word flag Last Word Flag is generated simultaneously with the occurrence of packet complete Packet Complete. The last word flag is generated independently without considering each indication of true zero and residual Remnant when there is no PAF. On the other hand, if a PAF exists, the last word flag LAST Word Flag is generated in consideration of each indication of true zero and residual Remnant.
7 and 8 illustrate case 2 in Table 1. In FIG. 7, PAF occurs without segmentation immediately after the packet is complete, followed by a 32-bit PS codeword. FIG. 8 is similar to FIG. 7 except that three inserted zero-length no-operation (NO-OP) codewords precede the PS codeword. 7 and 8, the PAF is generated in time coincident with the packet complete signal Packet Complete, and the packet ends without causing the remaining data to be segmented in the next packet. FIG. 7 shows the more general case where a 32-bit long PS codeword follows immediately. FIG. 8 shows that NO-OP words are allowed to be inserted.
FIG. 9 is a diagram related to case 6a in Table 1. In this figure, the PAF is generated in a position that does not coincide with the packet complete signal Packet Complete. PAF occurs after the NO-OP word after the packet is complete without segmentation, followed by the PS code word. In this case, the last word indication (flag) Last Word Indicatation occurs in association with the packet complete signal Packet Complete, but the accumulator status is idle with a value of 0 (zero) and the true zero indication True Zero Since there will be a final word indication (flag) Last Word Indication will not occur in association with PAF.
10 and 11 show an example of case 1 in Table 1. In FIG. 10, PAF occurs with segmentation occurring immediately after a packet is complete, followed by a PS codeword. FIG. 11 is the same as FIG. 10 except that the inserted NO-OP word is present prior to the PS code word. In this case, since there is residual data to be segmented, two final word indicators (flags) Last Word Indivator are required. One of the final word indicators (flags) Last Word Indivator occurs during the packet complete Packet Complete, and the other of the final word indicators (flags) Last Word Indication is one of the PAFs because of segmentation. Occurs after the clock period.
12, 13 and 14 show an example of case 3 in Table 1. FIG. In these examples, PAF occurs at some position during packet formation, but does not occur on a word boundary (ie, segmentation into the next word occurs), and packet complete indication Packet Complete Does not match. Then, as a result of the partial start of the word (due to segmentation), the final word signal Last Word usually occurs in the next clock period after the PAF. In FIG. 12, PAF occurs after several NO-OP words after the packet is complete with segmentation, followed by PS code words. In FIG. 13, PAF occurs with segmentation occurring at the same time as the word is complete, followed by a PS code word. In FIG. 14, PAF occurs after a word is complete and after segmentation has occurred with several codewords.
FIG. 15 and FIG. 16 are diagrams for illustrating the necessity of generating the pseudo last word Pseudo Last Word, which is a special type of final word, illustrating case 4 in Table 1. In this case, PAF occurs without a word being segmented, that is, immediately after a word completes on a word boundary that is a multiple of 32 (Figure 15) or just after that (Figure 16). To do. In this case, it is assumed that the complete word has already been supplied (supplied after the PAF) before the information that it was the last word is obtained. In that case, an all-zero pseudo last word Pseudo Last Word is formed and supplied. The reason for this is that MPEG allows any number of zeros (0) to precede the start codeword, and guarantees that the PS codeword will be followed by the occurrence of PAF. Because it is. Furthermore, in these cases, the packet shortage is compensated by a zero value bit (null) word by a data / header synthesizer. In this case, the synthesizer will provide one fewer word, since one zero word is issued and it is pseudo-marked as the last word. In FIG. 15, PAF occurs as soon as a word is complete (with no segmentation) followed by a PS code word. In FIG. 16, the inserted NO-OP word follows after the word is complete (with no segmentation). Thereafter, a PAF occurs, followed by a PS code word.
FIG. 17 shows a detailed configuration of the data / header synthesizer 15 (FIG. 1). The header component is written to the header FIFO 70 in response to the header write enable signal Header Write Enable whenever the header is generated by the header generator 18. Similarly, the packed data word is written to the data FIFO 72 in response to the data write enable signal Data Write Enable when the word is generated by the data packer 12. The last word indicator Last Word Indicator generated by the data pack process occurs with the last word in the packet regardless of whether the last word is the 30th word. The header output and data output of each unit of the header FIFO 70 and the data FIFO 72 are multiplexed and supplied on a common bus by a multiplexer (multiplexer) 76, and further supplied to an output register 78. As shown in FIG. 19, the output register 78 supplies the data ready signal Data Ready, packet data Packet Data, header header, and header indicator Header Indicator to the rate buffers 713 and 714. In response to the zero issue signal Issue Zero supplied from the FIFO state controller 74, the multiplexer 76 can issue a zero word in accordance with an instruction (command).
Both units of the two FIFOs 70 and 72, the multiplexer 76 and the output register 78 are directed by a controller 74 which is a state machine. After power-on (or power-on) or resumption of a similarly acting operation, controller 74 waits for a processable header to appear. The processable header is sent to the output bus of the multiplexer 76 along with a data ready indicator Data Ready Indicator and a header indicator Header Indicator. Next, the controller 74 extracts the data as long as it can be processed and controls the state of the data FIFO 72 until the last word indicator Last Word Indicator appears. Each transmitted data is accompanied by a data ready indicator, which is sent to an output register 78. If it is determined that 30 data words have already been supplied when the last word indicator Last Word Indicator appears, the controller 74 rechecks the header FIFO 70 for further processable information. To do. When less than 30 data words are supplied, the controller 74 instructs the multiplexer 76 using a zero issue command Issue Zero to issue zero words to make up for packet shortages. All such zero words are supplied with a data ready indicator. If there is no header and data to be transmitted, the controller 74 commands the multiplexer 76 to issue a zero word without a data ready indicator Data Ready Indicator for a period when there is no data that can be processed. A flowchart (state transition diagram) showing the operation of the combiner 15 driven by the state machine as described above is shown in FIG. The data ready indicator and the header indicator Header Indicator are sent through the output register 78 to the rate buffers 713 and 714 of FIG. These indicators inform the rate buffer that data and header information is present on the bus, maintain forward header / data registration, and forward error correction (FEC) encoding and data Interleaving is performed. In this system (FIG. 19), FEC processing and interleaving are performed by sending a header first, ie sending one header for transmission to a rate buffer, before the data packet represented by the header is sent. Need to start. The empty flag signal Empty Flag sent from the header FIFO 70 and the data FIFO 72 indicates that the header and the data word do not exist (null), and the state controller 74, which is a state machine, enters an idle state. This state is shown in FIG. 18 as “no header” and “no word” states in states 0 and 1. When the related read enable signal Read Enable is sent to the header FIFO 70 or the data FIFO 72, respectively, the header / data selection signal Header / Data Select supplied from the controller 74 commands the multiplexer 76, and the header FIFO 70 unit Either the header output Header Output or the data output Data Output of the data FIFO 72 unit is switched and connected to the signal bus on the input side of the output register 78. A zero word is added to the incomplete shortened packet to generate a predetermined 30-word data packet, and the data packet is supplied to the output buffer 78. The capacity of the output buffer 78 is considerably larger than the capacity of the header buffer 70 and the data buffer 72 in the previous stage. These buffers receive and process data efficiently without being interrupted. By adopting such an operation configuration that does not receive interrupts, the timing and synchronization functions are greatly simplified. Its function can be simplified, for example, by eliminating the difficult synchronization process in clock stop / start.
A complete packet of a predetermined length can be properly used by adding the required number of empty words as described above. By using such complete packets, data can be searched and synchronized in any data state, such as in a variable length codeword system. The start codeword, in particular the I frame start codeword, is an inherent resynchronization point in a data stream compatible with MPEG (interoperability). The start codeword appears at the packet boundary. Such packet boundary processing can be performed by packet perfecting the truncated data packet and determining the packet boundary using an empty word of zero-value bits in the system described herein. The MPEG standard allows any number of zero words to precede the start code word, and the receiver / decoder ignores null words with zero value bits. In this example, the output buffer 78 has a large capacity and high temporal tolerance (resistance against consecutive identical values), and therefore constitutes a means suitable for executing a null word pack operation. It should be noted here that there is only a small amount of time (eg, one clock cycle) available to pack a null word between the appearance of a PAF and a PS codeword at the packet boundary.
FIG. 19 illustrates a high-definition television (HDTV) encoding system using an apparatus according to the present invention in the transport processor section. FIG. 19 shows a system for processing a single video input signal. However, it can be seen that the luminance (luminance) component and the chrominance component are processed separately, and the compressed chrominance component is generated using the luminance motion vector. The compressed luminance and chrominance components are interleaved to form macroblocks before parsing the codeword priority. Additional information regarding the system of FIG. 19 can be found in US Pat. No. 5,168,356 to Acampola et al. The sequence (column) of image fields / frames shown in FIG. 20A is supplied to a circuit 705 for rearranging the fields / frames according to FIG. 20B. The rearranged sequence is supplied to the compressor 710. The compressor 710 generates a compressed sequence of frames encoded according to an MPEG format. The format has a hierarchical structure, which is illustrated in simplified form in FIG. The MPEG hierarchical structure format is composed of a plurality of hierarchies each having different header information. Each header includes a start codeword, data related to each layer, and an item (provision) for header extension as a normal header format.
An MPEG format signal generated by this system will be described. (A) A continuous image field / frame of a video signal is encoded according to an I, P, B encoding sequence, and (b) is encoded at a screen level. Data is encoded in the form of MPEG format slices or blocks. In that case, the number of slices per field / frame takes various values, and the number of macroblocks per slice also takes various values. The I-coded frame is intra-frame compressed so that it can be processed using only the I-frame compressed data when performing image reproduction. P-coded frames are coded according to the forward motion compensated prediction method, and P-frame coded data is generated from the current frame and the I or P frame that occurs before the current frame. The B encoded frame is encoded according to a bidirectional motion compensated prediction method. B-coded frame data is generated from the current frame and the I and P frames that occur before and after the current frame.
The encoded output signal of the current system is segmented into fields / frames or groups of images (GOP) illustrated in box L2 row (FIG. 22). Each GOP (L2) includes a header, followed by a segment of image data. The GOP header includes data related to horizontal and vertical screen sizes, aspect ratios, field / frame rates, bit rates, and the like.
Image data (L3) corresponding to each image field / frame includes a picture head, and slice data (L4) follows the picture header. The picture head contains the field / frame number and the picture code type. Each slice (L4) includes a slice header, and the slice header is followed by a plurality of data blocks MBi. The slice header includes a group number and a quantization parameter.
Each block MBi (L5) represents a macroblock and includes a header, followed by a motion vector (MV) and a coding coefficient. The MBi header includes a macroblock address, a macroblock type, and a quantization parameter. The coding coefficient is exemplified in the layer L6. Each macroblock includes a total of six blocks including four luminance blocks, one U chrominance block, and one V chrominance block (see FIG. 21). A block represents a matrix of pixels, for example an 8 × 8 matrix, on which a discrete cosine transform (DCT) is performed. The four luminance blocks are, for example, a matrix of 2 × 2 adjacent luminance blocks representing a 16 × 16 pixel matrix. The chrominance (U and V) blocks represent the same area as the entire area of the four luminance blocks. That is, before compression, the chrominance signal is subsampled by two coefficients (1/2) in the horizontal and vertical directions with respect to luminance. One slice of data corresponds to data representing a rectangular portion in an image corresponding to an area represented as an adjacent macroblock group. One frame includes 360 slices, that is, 60 slices in the vertical direction × 6 slices in the horizontal direction.
The block coefficient is supplied by the DCT for one block at a time. DC coefficients are generated first, followed by each DCT AC coefficient in order of its relative importance. A block end code EOB (end-of-block) is added to the end of each block of continuously generated data.
In FIG. 19, the data supplied from the compressor 710 is prioritized before being supplied to a transport processor 712 that segments the data into a high priority (HP) component and a standard priority (SP) component. Processed by the processor 711. These components are coupled to each forward error correction coding unit 715 and 716 via rate buffers 713 and 714. The rate buffer temporarily stores the panic data and header, after which the FEC error correction coding circuit extracts the packed data and header. A rate controller 718 cooperates with the buffers 713 and 714 to adjust the average data rate of the data supplied from the compressor 710. The signal is then coupled to a transmission modem 717 whose HP and SP data quadrature amplitude modulates each carrier in a standard 6 MHz NTSC television channel.

Claims (2)

An apparatus for processing a data stream of variable length codewords representing an image, comprising:
In response to a data stream of the variable-length code words, and means to form a packet having a predetermined number of bits less than the number,
Comprising a <br/> the data processing means to transfer the formed packets to an output,
When transferring the formed packet to the output, a packet alignment flag is inserted to indicate the start of a group of images (GOP) associated with the packet, and the data processing means is configured to transmit the predetermined number of bits. as the fixed-length packets having, the optionally packets, meets a zero value word with no function
The data processing means includes
Including pre Kipa packets, means for receiving a header information about the contents of the associated data packets of the stream of data packets is on,
And means for receiving the Kipa packet before,
Hints, pre SL receives the header and the data packet, processes it and wherein the creating an output data stream. A method of processing a data stream of variable length codewords representing an image, comprising:
In response to the variable length codeword data stream, forming a packet having fewer than a predetermined number of bits;
Forwarding the formed packet to the output;
With
The transferring step includes:
Receiving a header containing information about the contents of the associated packet of the stream of data packets, including the packet;
Receiving the packet;
Inserting a packet alignment flag to signal the start of a group of images (GOP) associated with the packet;
Filling the packet with a non-functional zero-value word as necessary to be a fixed-length packet having the predetermined number of bits;
Processing the header and packets to create an output data stream.

Images