JP2004357340A - Apparatus for processing data stream - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily form and process a transport packet in digital signal processing. <P>SOLUTION: An apparatus for processing a data stream of variable length code words representing an image is provided with: a means (12) for creating a data packet which includes a short data packet including words less than a predetermined number in response to the data stream of variable length code words; and a data processing means (15) for transferring the created data packet to an output. When the stream of data packets is transferred to the output, the data processing means fills the short data packet with no-op null words as needed to obtain a data packet of a fixed length including the predetermined number of words. That is, an incomplete data packet is filled with blank (zero bit) words and a perfect data packet equipped with the specified number of words is constituted. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to the field of digital signal processing, and more particularly, to a method and apparatus for assembling transport data packets used to transmit encoded MPEG-type data, for example, in high definition television systems.

  U.S. Pat. No. 5,168,356 issued to Acampora et al. Describes a system for processing high definition television (HDTV) signals according to an MPEG type variable length coding. MPEG is a standard encoding format determined by the International Standards Organization (ISO). Its standard is "International Organization for Standardization" ISO / IEC DIS11172, coding method for moving pictures and associated audio for digital storage media (Coding for Moving Pictures and Associated Audio for Digital Storage Media), Rev. Nov. 23, 1991, which is hereby incorporated by reference to describe the general encoding format.In the system of Acampola et al., Codewords (codewords) Priorities are given to represent high and low priority information in the stream, and the codeword data stream is sent to a transport processor, which transports the codeword data. Each with a header section and a packed data payload section. Pack in the form of transport cells containing a down, it supplies a high data stream priority and low priority output data stream.

  The main function of the transport processor is to pack the variable-length codeword data supplied (issued) by the preceding priority processor in the form of packed data words. The accumulated packed words are called data packets, and are preceded by a transport header.

  The format of the transport packet facilitates resynchronization and signal recovery at the receiver. For example, even if a signal is destroyed or broken due to interference in a transmission channel, adding header data enables the receiver to re-enter the data stream if transmitted data is lost or corrupted. Points can be determined based on the header data. Synchronization of data in an MPEG-compliant decoder is also performed by an image group GOP (Group of Pictures) having a start point at a packet boundary. As will be seen in the following description, a GOP is a series of one or more images or frames, the GOP format allowing random access to a sequence of encoded video bitstreams. ing. Also, resynchronization is achieved by responding to the picture start codeword of an intra (intra or intra-frame) coded I-frame and by placing the picture start codeword at the boundary of a packet, for example in an MPEG standard compliant system. Easy to do. The use of an apparatus according to the principles of the present invention facilitates the formation and processing of transport packets.

  In accordance with the present invention, in systems that transmit variable length codewords (eg, MPEG codewords) within data packets, incomplete data packets having fewer than a specified number of words have no function. The "zero words" are stuffed to create fixed length packets and demarcate the packets where the defined code word appears.

  In the disclosed preferred embodiment, a special codeword, a packet alignment flag (PAF), is inserted into the MPEG data stream to signal the beginning of a group of pictures (GOP). The PAF is placed immediately before the 'picture start' code word for the intra-coded "I" frame that starts the GOP. The PAF signals the upcoming appearance of the 'picture start' code word and spans one clock cycle, during which one "housekeeping" function may be implemented at the beginning of the next packet. Performed before the 'image start' code word appears. These housekeeping functions include, for example, resetting the accumulator, checking the status of the header, and providing a 'last word indicator' for the data packet under construction when the PAF appears. Is to happen. Since the GOP is to begin on a packet boundary, the appearance of the PAF terminates the data packet under construction. Such termination may result in truncated packets containing less than a prescribed number of packed words. This shortened data packet is filled with blank (zeroed out) words to make up a complete data packet with a defined number of words, and between the packets in which the picture start code word appears. Set boundaries. One 32-bit fixed-length word forms one data packet, and the data packet is preceded by a 32-bit header.

  According to the present invention, formation and processing of a transport packet are easily performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram of a data packer 12 and a packed data word controller 10 of a transport processor. As noted above, the primary function of the transport processor is to pack variable length codeword data into fixed length (eg, 32 bits) data words. The accumulated 30 data words make up a data packet, and a transport header is finally added before the data packet. As described below with respect to FIG. 19, such a transport processor is used in a system for processing a compressed video signal in MPEG format. Additional features of the formatting and processing of the MPEG format will be described below with reference to FIGS. 20, 21 and 22.

  The controller 10 monitors the accumulated value of the data word of the length (Length) in relation to the packet alignment flag (Packet Alignment Flag) PAF, and completes the 32-bit data word assembled from the stream of the variable length codeword. Check the integrity (completed) of the 960-bit data packet. The length data Length is a parallel 6-bit word that matches the length of the variable-length codeword, and defines the length of the variable-length codeword. The binary value of the length word Length indicates the number of bits that match the length of the variable length codeword that actually represents the MPEG codeword to be transported (transmitted). Each variable length codeword appears on a 32 bit wide bus and has a variable number of significant bits (1-32) representing a code in MPEG format.

  The PAF is generated by the input processor 14 and is one codeword before the picture start codeword PS (Picture Start codeword) of the MPEG type "I" (intra-coded) frame at the start of the group of pictures. Is to appear. The PAF is generated by detecting the presence of an I-frame picture start codeword PS by a digital comparator. The unit of the input processor 14 also includes a signal delay circuit for processing the picture start codeword PS and the PAF, so that the PAF is synchronized with the clock cycle of the codeword immediately before the I-frame picture start codeword PS. Is to occur. The delay circuit also ensures that the output signals supplied to each unit of packed word controller 10 and data packer 12 have the proper time synchronization relationship.

  The word address Word Address is sent to the data packer 12, which receives the packed variable length codewords VLC and ensures proper concatenation of the input variable length codewords. Also, a word control signal Word Control is sent to packer 12 to indicate the presence of a short word, to mark (indicate) the last word in the packet, and to indicate the proper alignment position with the associated transport header added. To obtain a sequence (column) of 30 packed data words. The controller 10 tracks and monitors the completion (completion) of the packet by accumulating the binary value of the length word Length. Each length value represents the number of significant bits in the associated codeword. One packet is completed (completed state) when 960 bits are accumulated. The starting point or initialization of this count is made by the appearance of the PAF, which resets the internal accumulator in the controller 10.

  The data packer 12 receives a variable length codeword (VLC) via a 32-bit parallel data bus. The valid bits are packed into a 32-bit word according to the supervisory control signal supplied from the controller 10. Also, concatenation is performed to accept the final MPEG bit serial transmission order. The packed data supplied from the unit of the data packer 12 is transferred to the input FIFO data buffer (data FIFO) 16 of the data and header combiner 15 at a variable word rate (speed). Further, the synthesizer 15 receives the data write enable signal Data Write Enable from the data packer 12, and the data packer 12 enables the FIFO data buffer 16 in the synthesizer 15 so that valid data is written to the FIFO data buffer 16. To The data packet will be packet-complete when the transfer of such 30 words is complete, unless the PAF mandates a short packet. The Last Word Indicator provided by packer 12 marks the 30th word in the normal packet in this example, or marks the last word in the packet which is shortened by the appearance of PAF.

  As long as there are pack data words that can be processed, the pack data words are transferred to the data / header combiner 15. Similarly, as long as there is a transport header that can be processed, the transport header is sent from the header generator 18 to the input FIFO header buffer (header FIFO) 17 of the synthesizer 15. The information used by header generator 18 to form the header is obtained from input processor 14 and word controller 10. The header write enable signal Header Write Enable indicates that there is a header that can be processed, and enables the FIFO 17 so that the header is written to the FIFO 17. The combiner 15 adds a header before each packed data payload and sends the resulting transport packet or block to the output rate bach as shown in FIG. In addition, the synthesizer 15 supplies an output data ready signal indicating that the packed data word or the transport header is in a transmission ready (transmittable) state. The header indicator signal Header Indicator indicates a clock cycle when the header is transmitted. This signal acts as a marker at the transport packet boundary to ensure that subsequent operations, such as Forward Error Correction (FEC), are properly provided to the transport cell.

  Each header contains information about the data in the data packet associated with that header. The header information provides data assembly and synchronization at the receiver. The header information includes, for example, information such as a service type (eg, audio, video, data), a frame type, a frame number, and a slice number. This type of header and its processing is described in U.S. Pat. No. 5,168,356 to Acampola et al. In connection with an HDTV digital signal processing system using MPEG type signal encoding.

  The data packet may include less than 30 packed data words, ie, 1-29 words, in this example. The PAF provided by the input processor 14 appears immediately before the picture start codeword PS of the intra-coded I frame when the GOP starts, as described below in connection with FIGS. A new packet is always started by the picture start codeword PS for an intra-coded frame, and immediately preceding PAF indicates the end of the data packet and the start of the new packet. This packet alignment or alignment with the picture start codeword PS helps to perform fast acquisition of the data stream at the receiver. If a PAF occurs during the formation of a fixed length word, a shortened data packet will be formed. The remaining bits in the pack word being assembled are filled in the data packer 12 with a plurality of "zero value bits" (1-31). Further, the remaining words in the data packet are similarly filled with a plurality of "zero value words" (1 to 29) in the combiner 15 so that the size of the transport packet is maintained at a predetermined length. Such a "zero word fill" request is indicated by the generation of the last word indicator Last Word Indicator before 30 data words have been transferred to combiner 15.

  It is important to properly identify the last word in a data packet. The Last Word ensures that packets assembled with the associated transport header are properly recorded (accommodated). Further, the last word Last Word indicates the presence of a packet filled at the boundary (that is, an intra-coded frame) of the screen group GOP in the MPEG format. GOP boundaries are important, for example, to provide resynchronization in a television receiver / decoder after a channel change. Determining the last word is not trivial. The state of the packet, such as when the packet is complete (completed) and when it is complete, whether data segmentation or data segmentation to the next packet is taking place. The final word Last Word is determined according to the specific information. The last word has a state where the last word is a word formed during the current clock period and a state where the last word is a word to be formed during the next clock period. Exists.

  Some specific examples of the formation of the final word Last Word are given below. If there is no PAF when the packet is complete, the last word (the 30th word in this example) is the last word and is marked as the last word by the last word indicator Last Word Indicator. . This is an example of the “true” last word Last Word. PAF occurs when a packet has no bits to segment into the next packet, ie, when a word ends exactly at a packet boundary. The last word of the completed packet is marked as the last word Last Word, since it is in fact the last word. This is another example of the "true" last word, Last Word. PAF also occurs when a packet is complete with the remaining few bits segmented into the first word of the next packet. In this case, two consecutive final words Last Word are formed and marked as such. First, the last word of the completed packet is marked as Last Last (the "true" last word). The first word of the next packet is then marked as the last word, Last Word, because the packet is forcibly shortened by the PAF. In the case of a shortened packet such as the latter, the last word Last Word appears before 30 words have been transmitted, and then "zero words" are filled to make the packet a complete packet. Next, another example of the last word Last Word will be described. PAF also occurs when a packet is in an incomplete packet state during assembly. If the internal word is word-complete with the remaining few bits segmented into the next word, that partial word will be the last word Last Word. A difficult situation arises, especially when the packet is incomplete in the process of being assembled and the internal word is complete without bits being segmented into the next word. That is, if the internal word is sent to the data / header combiner before the subsequent data (ie, the appearance of the PAF) indicates this word is the last word, then this word is the last word. It is already too late to mark properly. In this case, one zero word called a "pseudo" last word is generated and displayed as the last word. Such a pseudo final word is composed entirely of zero bits. This is different from, for example, that part of the segmented (incomplete) final word is padded with 0 bits. The above example or another example will be described with reference to FIGS.

  An important feature of the system disclosed in the following description is the generation of a zero length PAF. This zero-length PAF indicates that the beginning of the GOP will appear shortly after, and generates and marks the last word Last Word in the data packet and, if necessary, the pseudo last word Pseudo Last Word , And specific signals can easily be generated in relation to the various states of occurrence of the last word Last Word.

  FIG. 2A shows details of the controller 10 of FIG. Controller 10 includes accumulator 20 in a feedback circuit having modulo 960 circuit 22. The return path includes a buffer register 23 which holds the newly accumulated value at the end of each length input cycle. The input PAF word and length word Length are sent to modulo unit 22 and accumulator 20 via input register 24, respectively. The value of the length word Length is sequentially and continuously accumulated by the units of the accumulator 20, and the packet length is set to 960 bits by feedback synthesis of the accumulator 20 and the modulo 960 unit 22. The accumulator output supplied from the buffer register 23 indicates a bit position in the packet, and is sent to the packet state controller 25.

  The packet state controller 25 receives the PAF from the input buffer register 24 and supplies (generates) an output signal necessary for generating a write command in the word state controller 26. When the accumulator bit count (bit count value) becomes 960 or more, a packet complete output signal Packet Complete is supplied to the word state controller 26. When the accumulator bit count does not indicate a word boundary (i.e., when the bit count is not equal to an integer multiple of 32), controller 25 generates an output residual signal Remnant. When the accumulator bit count is zero, a true zero output signal True Zero is provided. This true zero output signal is an important signal for making an accurate generation decision for the final word only when a PAF is present. The logic that generates these signals is shown in FIG. 2B, as described below.

  When an empty codeword of zero length, a zero length word Length indicating the presence of a no-operation (NO-OP) codeword, is received, accumulator 20 is idle and holds the final bit count. I do. There are exceptions to this rule, where the PAF may always force the accumulator value to 0 regardless of the bit count. Another exception is when a packet forms a complete packet exactly at the packet boundary (ie, the accumulator count is 960). Then, in the next clock cycle, the accumulator count is corrected via the modulo 960 unit 22 to the binary value of the next length word Length. When the accumulator count goes above 960, the packet is complete.

  In FIG. 2B, a 10-bit accumulator output representing the accumulated length is assigned to I0-I9. A packet is complete when the accumulated length of the packet codeword is 960 or more. When the four most significant (MSB) bits I6-I9 of the accumulator are in a logic one state, that state is indicated and the four bits are provided to AND gate AND30. When the ten bits of all accumulators are in a logic zero state, a true zero is indicated, and the ten bits are provided to an OR gate OR31. The "no residue" state is indicated when the five lower (LSB) bits I0-I4 of the accumulator are in a logic zero (zero) state, and the five bits are provided to an OR gate OR32. The word address Word Address of the data packer is generated in response to the six lower bits I0-I5 of the accumulator. The logical product (AND) gate array 34 forces the word address Word Address to a logical 0 state when the packet alignment flag (PAF) appears.

  FIG. 2C shows details of the data packer 12 of FIG. The variable length codeword is sent to the data shifter 35. As the data shifter 35, a barrel shifter such as Model 74AS8838 manufactured by Texas Instruments can be used. To determine the proper position of the valid bit of the variable length codeword to be concatenated, the LSB of the length accumulator output is generated from the packet state controller 25 (see FIGS. 2A and 2B). Is sent to the data shifter 35 as a word address. When the 32-bit word is formed by concatenation of the variable length codewords, the packed word is transferred to holding register 36. A flag indicating whether there is any pack data that can be processed is provided by a word ready signal Word Ready supplied from the register 36, and the word is transferred to the data assembling circuit 37. The data assembling circuit 37 uses the control signals W EN1, W EN2 and W ZERO supplied from the packed word controller 10 (FIG. 1) to enable data writing and a last word flag (indicator) Last Word The pack data together with the flag is supplied to the data and FIFO data buffer 16 in the header synthesizer 15 of FIG.

  After transmitting the last word in the packet, the next transport header is then inserted into the combined data stream so that the header of the next packet is inserted after the last word of the current packet Is done. The header controller uses the accumulator output (FIG. 2A) to indicate the location of certain codewords in the packet, such that each location is described in the entry point field in the header. The logic array associated with the word state controller 26 and the data assembling circuit 37 generates a Last Word Indicator and a flag that enables the data word to be written to the FIFO buffer. Table 1 below illustrates the generation of the final word in response to the inputs to the logical array: PAF (Packet Alignment Flag), PC (Packet Complete), TZ (True Zero) and REM (Remnant Word Segmentation Indicator). Shows the action state of When the output signal of the controller 26 is supplied via the buffer register 28, an output signal is generated from the data assembling circuit 37. These signals include a write enable signal W EN1 indicating the last word appearing in the next clock cycle, a write enable signal W EN2 indicating the last word appearing in the current clock cycle, and a write that generates a pseudo last word Psuedo Last Word. Zero signal W ZERO is included. The pseudo last word Psuedo Last Word is generated when the occurrence of the PAF coincides with the packet formation time located at the internal codeword data boundary of the incomplete packet.

Table 1
Word state controller states
PAF PC TZ REM Action performed
YES YES N / A YES Flag current word as Last Word,
then flag word on next clock also
(CASE 1)
[Last word flag for current word
And then wait for the next clock
Flag the code
(Case 1)]
YES YES N / A NO Flag current word as Last (CASE 2)
[Last word flag for current word
(Case 2)]
YES NO N / A YES Flag word on next clock as Last
(CASE 3)
[Last word at next clock
Flag (Case 3)]
YES NO NO NO Form a pseudo Zero Word on next
clock, and flag it as Last Word
(Case 4)
[Word pseudo zero word at next clock
Generate the final word
Rag (Case 4)]
NO YES N / AN / A Flag current word as Last (CASE 5)
[Last word flag for current word
(Case 5)]
YES NO YES No None (CASE 6a)
[None (Case 6a)]
NO NO N / Z NA None (CASE 6b)
[None (Case 6b)]

  Note 1: The Last Word Flag on the current word is indicated by Write Enable 2.

  Note 2: The last word flag on the word at the next clock Last Word Flag is indicated by Write Enable 1.

  Note 3: The generation of a pseudo-word is indicated by Write Zero and is flagged by Write Enable 1.

  A truth table for generating W EN1, W EN2 and W ZERO for various examples of operating states (cases 1-6 in Table 1) is shown in FIG. This will be described later in connection with FIGS. The algorithm for Table 1 is described in Appendix A. The output signal of controller 26 is provided to output buffer register 28 before being provided to the data assembly circuit shown in FIG. 4 as an output word control signal.

  4 constitutes the output circuit of the data packer 12 of FIG. That is, the data assembling circuit has a circuit configuration as shown, and includes AND gates AND42 and 44, an OR gate OR46, and D-type flip-flops (DF / F) 43 and 45. The 32-bit packed data word Packed Data Word is sent to the data FIFO via the AND gate AND42, and the word ready signal Word Ready supplied from the preceding packer circuit is sent via the AND gate AND44. , The data write enable signal Data Write Enable for the data FIFO 16 in FIG. Data write control signals W EN1, W EN2 and W ZERO (FIG. 2A) provided by packed word state controller 26 are provided to flip-flops 43 and 45 and logic gate 46 as shown. W EN2 indicates the last word flag Last Word Flag associated with the current word, and W EN1 indicates the last word flag Last Word Flag associated with the word in the next clock cycle. The W ZERO control indicates the generation of a pseudo last word Pseudo Last Word whose last word is flagged by W EN1 (case 4 in Table 1). In this case 4, words of all ZEROs called pseudo final words are inserted into the packed data word stream Packed Data and written to the data FIFO 16. The word ready input signal Word Ready to gate AND44 of the assembly circuit is provided by holding register 36 (FIG. 2C) to indicate that there are 32 packed bits that can be processed.

  Next, an example of generation of the last word illustrated in FIGS. 5 to 16 will be described. Some of these examples illustrate the effect of zero-length NO-OP words at positions before and after the PAF.

  5 and 6 show different examples corresponding to case 5 in Table 1. In FIG. 5, a packet has been segmented into the next packet (ie, the bit value of the accumulator is greater than 960) to form a complete packet. In FIG. 6, the packet forms a complete packet exactly at the boundary of the packet (i.e., the bit value of the accumulator is equal to 960), without segmentation into the next packet or producing residual data. Not complete packets. In either case, the last word flag, Last Word Flag, is generated at the same time that the packet complete packet complete occurs. The last word flag Last Word Flag is generated independently without considering the indication of True Zero and the remaining Remnant when no PAF exists. On the other hand, if PAF is present, the last word flag LAST Word Flag is generated taking into account the representation of True Zero and the remaining Remnant.

  7 and 8 illustrate Case 2 of Table 1. In FIG. 7, a PAF occurs without segmentation immediately after the packet is complete, followed by a 32-bit picture start codeword PS. FIG. 8 is similar to FIG. 7 except that the three inserted zero-length no-operation (NO-OP) codewords precede the picture start codeword PS. In FIGS. 7 and 8, the PAF occurs at the same time position as the packet complete signal Packet Complete, and the packet ends without segmentation of the residual data in the next packet. FIG. 7 shows a more general case in which a 32-bit picture start codeword PS immediately follows. FIG. 8 shows that NO-OP words are allowed to be inserted.

  FIG. 9 is a diagram related to the case 6a in Table 1. In this diagram, the PAF is generated without being aligned with the position of the packet complete signal Packet Complete. PAF occurs after the NO-OP word after the packet is complete without segmentation, followed by the picture start codeword PS. In this case, the last word indication (flag) Last Word Indicatation occurs in association with the packet complete signal Packet Complete, but the accumulator state is idle with a value of 0 (zero) and the true zero indication True Zero indicates Last Word Indication will not occur in connection with PAF because it will be present.

  FIGS. 10 and 11 show Case 1 of Table 1. FIG. In FIG. 10, the PAF occurs with segmentation occurring immediately after the packet is complete, followed by a picture start codeword PS. FIG. 11 is similar to FIG. 10 except that the insertion NO-OP word precedes the picture start codeword PS. In this case, since there is residual data to be segmented, two final word indicators (flags) Last Word Indivator are required. One of them, the last word indicator (flag) Last Word Indivator, occurs during the packet complete period, and the other of them, the last word indicator (flag) Last Word Indication, has one of the PAFs due to segmentation. Occurs after a clock period.

  FIGS. 12, 13 and 14 show case 3 of Table 1. In these examples, the PAF occurs at some location during the packet formation, but not on word boundaries (ie, segmentation to the next word occurs), and the packet complete indication Packet Complete Do not match. Then, as a result of the partial start of the word (due to segmentation), the final word signal Last Word typically occurs in the next clock period after the PAF. In FIG. 12, the PAF occurs after several NO-OP words after the packet has been completed with segmentation, followed by a picture start codeword PS. In FIG. 13, the PAF occurs with word completion and with segmentation occurring at the same time, followed by a picture start codeword PS. In FIG. 14, PAF occurs after a word has been completed and after segmentation has occurred with a few codewords.

  FIGS. 15 and 16 are diagrams illustrating Case 4 of Table 1 and explaining the necessity of generating a pseudo final word Pseudo Last Word which is a special type of final word. In this case, the PAF occurs without one word causing segmentation, ie, immediately after the word is complete (FIG. 15) or shortly thereafter (FIG. 16) on multiples of 32 word boundaries. I do. In this case, it is assumed that the complete word has already been provided (provided after the PAF) before the information that it was the last word was obtained. In that case, an all-zero pseudo last word Pseudo Last Word is formed and supplied. The reason for this being allowed is that MPEG allows any number of zeros (0) to precede the start codeword and guarantees that the picture start codeword PS will come next due to the occurrence of the PAF. Because it is. Further, in these cases, the packet shortage is made up of zero value bits (empty) words by the data / header combiner. In this case, the synthesizer will supply one fewer word because one zero word is issued and it is pseudo-marked as the last word. In FIG. 15, a PAF occurs as soon as the word is complete (without segmentation), followed by a picture start codeword PS. In FIG. 16, after the word is complete (without segmentation), an insertion NO-OP word follows. Thereafter, a PAF occurs, followed by a picture start codeword PS.

  FIG. 17 shows a detailed configuration of the data / header combiner 15 (FIG. 1). The header component is written to the header FIFO 70 in response to the header write enable signal Header Write Enable whenever the header is generated by the header generator 18. Similarly, a packed data word is written to data FIFO 72 in response to a data write enable signal Data Write Enable when the word is generated by data packer 12. The Last Word Indicator generated by the data packing process occurs with the last word in the packet regardless of whether or not the last word is the 30th word. The header output and data output of each unit of the header FIFO 70 and the data FIFO 72 are multiplexed on a common bus by a multiplexer (multiplexer) 76 and supplied to an output register 78. As shown in FIG. 19, the output register 78 supplies a data ready signal Data Ready, packet data Packet Data, a header Header, and a header indicator Header Indicator to the rate buffers 713 and 714. The multiplexer 76 can issue a zero word according to an instruction (command) in response to the zero issue signal Issue Zero supplied from the FIFO state controller 74.

  Both units of the two FIFOs 70 and 72, the multiplexer 76 and the output register 78, are directed by a controller 74 which is a state machine. After power-on (or power-on) or resumption of a similarly acting operation, the controller 74 waits for a processable header to appear. The header that can be processed is sent to the output bus of the multiplexer 76 together with the Data Ready Indicator and the Header Indicator. Next, the controller 74 controls the state of the data FIFO 72 by extracting data that can be processed, as long as there is data that can be processed, until the last word indicator Last Word Indicator appears. Each transmitted data is accompanied by a data ready indicator, Data Ready Indicator, which is sent to output register 78. If it is found that 30 data words have already been supplied when the Last Word Indicator appears, the controller 74 re-examines the header FIFO 70 for more processable information. I do. When less than 30 data words have been provided, controller 74 commands multiplexer 76 using a zero issue command Issue Zero to issue zero words to compensate for the packet shortage. All such zero words are provided with a Data Ready Indicator. If there is no header and data to transmit, controller 74 commands multiplexer 76 to issue a zero word without a data ready indicator during periods when there is no data to process. FIG. 18 is a flowchart (state transition diagram) showing the operation of the synthesizer 15 driven by the above-described state machine. The data ready indicator and the header indicator are sent to the rate buffers 713 and 714 of FIG. These indicators signal the presence of data and header information on the bus to the rate buffer, maintain header / data registration, and provide forward error correction (FEC) coding and data Causes interleaving. In this system (FIG. 19), FEC processing and interleaving are performed by first sending a header before sending the data packet represented by the header, ie, sending one header and transmitting it to the rate buffer. Need to start. The empty flag signal Empty Flag sent from the header FIFO 70 and the data FIFO 72 indicates that the header and the data word are not present (empty), respectively, whereby the state controller 74 as a state machine enters an idle state. This state is shown in FIG. 18 as "no header" and "no word" in states 0 and 1. When the associated read enable signal Read Enable is sent to the header FIFO 70 or the data FIFO 72, respectively, a header / data select signal Header / Data Select supplied from the controller 74 instructs the multiplexer 76 to operate the unit of the header FIFO 70. Either the header output Header Output or the data output Data Output of the data FIFO 72 unit is switched to the signal bus on the input side of the output register 78 and connected. Zero words are added to the incomplete shortened packet to generate a data packet of predetermined 30 words, and the data packet is supplied to the output buffer 78. The capacity of the output buffer 78 is considerably larger than the capacities of the header buffer 70 and the data buffer 72 in the preceding stage. These buffers receive and process data efficiently without interruption. With such an operation configuration that does not receive interrupts, the timing and synchronization functions are greatly simplified. Its function can be simplified, for example, by eliminating the need for difficult synchronization processing in clock stop / start.

  A complete packet of a predetermined length can be properly used by adding the required number of empty words as described above. The use of such complete packets allows for data search and synchronization in any data state, such as in variable length codeword systems. The start codeword, particularly the I-frame start codeword, is a unique resynchronization point in an MPEG compatible (interoperable) data stream. The start codeword appears on a packet boundary. Such packet boundary processing can be accomplished by packet-completed truncated data packets and determining packet boundaries using empty words of zero value bits in the systems described herein. The MPEG standard allows any number of zero words to precede the start codeword, and the receiver / decoder ignores empty words of zero value bits. In this example, the output buffer 78 has a large capacity and a high temporal tolerance (resistance to successive identical values), and thus constitutes means suitable for executing an empty word pack operation. It should be noted here that there is only a small amount of time available (eg one clock cycle) to pack an empty word between the appearance of the packet alignment flag PAF at the packet boundary and the appearance of the picture start codeword PS. is there.

  FIG. 19 illustrates a high definition television (HDTV) coding system using a device according to the present invention in a transport processor section. FIG. 19 shows a system for processing a single video input signal. However, it can be seen that the luminance (luminance) component and the chrominance component are processed separately, and a compressed chrominance component is generated using the luminance motion vector. The compressed luminance and chrominance components are interleaved to form macroblocks before parsing the codeword priorities. Additional information regarding the system of FIG. 19 is provided in U.S. Pat. No. 5,168,356 to Acampola. The sequence (column) of image fields / frames shown in FIG. 20A is supplied to a field / frame rearrangement circuit 705 according to FIG. 20B. The rearranged sequence is supplied to a compressor 710. The compressor 710 generates a sequence of compressed frames encoded according to an MPEG format. The format has a hierarchical structure, which is illustrated in a simplified form in FIG. The hierarchical format of the MPEG format includes a plurality of layers each having different header information. Each header includes a start codeword, data related to each layer, and an item (provision) for header extension as a regular header format.

  The MPEG format signal generated by this system will now be described. (A) A continuous picture field / frame of a video signal is coded according to an I, P, B coding sequence, and (b) a picture level is coded. The data is encoded in the form of slices or blocks in the MPEG format. In this case, the number of slices per field / frame takes various values, and the number of macroblocks per slice also takes various values. The I-coded frame is intra-frame compressed so that it can be processed using only I-frame compressed data when performing image reproduction. P coded frames are coded according to the forward motion compensated prediction method, and P frame coded data is generated from the current frame and I or P frames occurring before the current frame. The B coded frame is coded according to the bidirectional motion compensation prediction method. B-encoded frame data is generated from the current frame and the I and P frames that occur before and after the current frame.

  The coded output signal of the current system is segmented into groups of fields / frames, or groups of pictures (GOPs), as illustrated in box L2 row (FIG. 22). Each GOP (L2) includes a header, which is followed by a segment of image data. The GOP header contains data related to horizontal and vertical screen sizes, aspect ratios, field / frame rates, bit rates, and the like.

  The image data (L3) corresponding to each image field / frame includes a picture head, and the picture header is followed by slice data (L4). The picture head contains the number of fields / frames and the picture code type. Each slice (L4) includes a slice header, which is followed by a plurality of data blocks MBi. The slice header includes a group number and a quantization parameter.

  Each block MBi (L5) represents a macroblock and includes a header, followed by a motion vector (MV) and coding coefficients. The MBi header includes a macroblock address, a macroblock type, and a quantization parameter. Coding coefficients are illustrated in layer L6. Each macro block includes a total of six blocks including four luminance blocks, one U chrominance block, and one V chrominance block (see FIG. 21). One block represents a matrix of pixels, for example, an 8 × 8 matrix, on which a discrete cosine transform (DCT) is performed. The four luminance blocks are, for example, a matrix of 2 × 2 adjacent luminance blocks representing a 16 × 16 pixel matrix. The chrominance (U and V) blocks represent the same area as the entire area of the four luminance blocks. That is, before compression, the chrominance signal is subsampled by two coefficients (1/2) in the horizontal and vertical directions with respect to luminance. Data of one slice corresponds to data representing a rectangular portion in an image corresponding to an area represented as an adjacent macroblock group. One frame is composed of 360 slices, that is, 60 vertical slices × 6 horizontal slices.

  The block coefficient is supplied by the DCT for one block at a time. First, a DC coefficient occurs, followed by each DCT AC coefficient in order of their relative importance. A block end code EOB (end-of-block) is added to the end of each block of continuously generated data.

In FIG. 19, the data provided by compressor 710 is prioritized prior to being provided to a transport processor 712 which segments the data into a high priority (HP) component and a standard priority (SP) component. The processing is performed by the processor 711. These components are coupled to each forward error correction coding unit 715 and 716 via rate buffers 713 and 714. The rate buffer temporarily stores the packed data and header, and then the FEC error correction coding circuit extracts the packed data and header. Rate controller 718 cooperates with buffers 713 and 714 to adjust the average data rate of data provided from compressor 710. The signal is then coupled to a transmission modem 717, the HP and SP data of which quadrature amplitude modulates each carrier in a standard 6 MHz NTSC television channel.

Appendix A Final Word Generation Algorithm

do positive_clock_edge = 1, ∞
if Packet_Alignment_Flag
if packet_complete
if remnant
flag word ready coincident with
packet_complete as last then flag short word ready on
next clock as last
else
flag word ready coincident with packet_
complete as last
else
if remnant
flag word ready on next clock as last
else
if not true_zero
create a zero word on the next clock,
and flag this pseudo word as last
else continue (ie, do nothing)
else
if packet_complete
flag word ready coincident with
packet_complete as last
enddo

Appendix A Final Word Generation Algorithm

do positive_clock_edge = 1, ∞
if Packet_Alignment_Flag [if packet alignment flag]
if packet_complete [if the packet is complete]
if remnant
flag word ready coincident with
packet_complete as last then flag short word ready on
next clock as last
[Set the final flag to word ready at the same time as the packet is complete,
The next clock will flag short word ready as final.)
else (other)
flag word ready coincident with packet_
complete as last
[Set the final flag to word ready at the same time as the packet is complete.]
else (other)
if remnant
flag word ready on next clock as last
[Set final flag to word ready at next clock]
else
if not true_zero [if not true zero]
create a zero word on the next clock,
and flag this pseudo word as last
[Generate a zero word at the next clock,
Flag the pseudoword as final.]
else continue (ie, do nothing)
[Others continue (do nothing)]
else (other)
if packet_complete [if the packet is complete]
flag word ready coincident with
packet_complete as last
[Flag the word ready at the same time as the packet is complete.]
enddo

FIG. 3 is a partial block diagram of a video signal encoder including a data word controller, a data packer, and a data / header combining device according to the present invention. FIG. 2 is a block diagram illustrating details of a word controller and a data packer of FIG. 1. FIG. 2 is a circuit diagram illustrating details of a word controller and a data packer of FIG. 1. FIG. 2 is a block diagram illustrating details of a word controller and a data packer of FIG. 1. 2B is a truth table for the operation of the word state controller shown in FIG. 2A. 5 shows details of the packed data assembling circuit. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 11 is an explanatory diagram illustrating an example of generation of a last word. FIG. 2 is a diagram illustrating details of a data and header combiner illustrated in FIG. 1. FIG. 18 is a state transition diagram relating to the operation of the state controller shown in FIG. 17. 1 is a block diagram of a high definition television encoding system including a device according to the present invention. FIG. 3 shows an image representation of a sequence of image fields / frames of an encoded video signal. FIG. 3 shows an image representation of a sequence of image fields / frames of an encoded video signal. FIG. 20 shows an image representation of the data block generation formed by the encoding / compression device in the system of FIG. 19; FIG. 20 illustrates a generalized image representation of a data format formed by an encoding / compression device in the system of FIG. 19.

Explanation of reference numerals

Reference Signs List 10 Controller 12 Data packer 14 Input processor 15 Header synthesizer 16 Input FIFO data buffer (data FIFO)
18 Header generator 17 Input FIFO header buffer (Header FIFO)

Claims (7)

An apparatus for processing a data stream of variable length codewords representing an image, comprising:
Means (12) for responding to said variable length codeword data stream to create a data packet comprising a short data packet comprising less than a predetermined number of words;
Data processing means (15) for transferring the created data packet to an output;
When transferring the stream of data packets to the output, the data processing means may convert the short data packet, if necessary, to a fixed-length data packet having the predetermined number of words. Apparatus characterized in that it comprises means for filling in null words of ops.   2. The apparatus of claim 1 wherein said data processing means includes data selection means for transferring a stream of data packets to said output and filling said short data packets with said null words. In claim 1, the data processing means comprises:
An input header buffer (70) for receiving a header containing information about the content of the associated data packet;
An input data buffer (72) for receiving the data packet;
An output buffer (78) for receiving a controlled sequence of headers and data packets from said header buffer and said data buffer, respectively.
Apparatus, wherein the data processing means, including the input data buffer, the input header buffer, and the output buffer, operates without interruption to receive and process the header and data packets.   4. The apparatus of claim 3, further comprising a multiplexer (76) for supplying the controlled sequence of headers and data packets to the output buffer, wherein the null word is supplied to the short data packet. An apparatus characterized in that:   The apparatus of claim 1, wherein the codeword is associated with GOP (Group of Picture) data and includes a PS (Picture Start) codeword appearing at an inter-packet boundary.   The apparatus of claim 5, wherein the data stream comprises an MPEG codeword including the PS codeword. 6. The apparatus according to claim 5, wherein the PS code word is associated with intra-frame encoded I-frame image data.

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