JP4349257B2 - Integrated circuit - Google Patents

Description

  The present invention relates to an integrated circuit comprising a clock signal output circuit for generating and outputting a multiplied clock signal obtained by multiplying the frequency of a reference clock signal by digital arithmetic processing based on a clock signal generated by a ring oscillator About.

  In recent years, since an operation clock frequency has increased in an integrated circuit such as a microcomputer, a clock signal output circuit configured using a PLL circuit is built in the integrated circuit, and a clock signal supplied from the outside can be used. Many employ a configuration in which the frequency is internally multiplied and supplied to a CPU or the like. Also, in such a clock signal output circuit, the period of the low-speed reference clock signal is measured by the high-speed clock signal generated by the ring oscillator, and the multiplied clock signal is generated and output by digital data processing. (Generally referred to as a digital PLL or DPLL).

  FIG. 8 shows a configuration example of the clock signal output circuit. The detailed configuration is disclosed in Patent Document 1. The ring oscillator 1 is configured by connecting a plurality of delay gates, for example, INV (inverter) gates 2 in a ring shape, and generates a high-speed clock signal by a digital oscillation operation. For example, if 32 INV gates 2 having a propagation delay time of 153 ps in two stages are connected, the high and low levels are inverted in a cycle of 153 ps × 16 = 2.45 ns. Therefore, the cycle of the generated high-speed clock signal fr is 2.45 ns × 2 = 4.9 ns.

  On the other hand, as the reference clock signal fs, for example, 31.25 kHz (period 32 μs) obtained by dividing the clock having a frequency of 4 MHz output from the oscillation circuit 18 by, for example, 128 by the frequency dividing circuit 3 is used. The frequency dividing ratio in the frequency dividing circuit 3 can be changed. The period of the reference clock signal fs is counted by the high-speed clock signal fr of the ring oscillator 1 by, for example, a 16-bit period counter 4. The count data of the period counter 4 is divided (right bit shifted) via the divider 6 according to the multiplied value set in the multiplied data register 5.

  Here, in the ring oscillator 1, 16 pulse edges having a phase difference of 1/16 with respect to the cycle of the high-speed clock signal fr can be extracted from every other output terminal of the INV gate 2. As described later, by selecting those pulse edges and setting the output timing of the multiplied clock signal, a resolution of 4 bits can be realized for the high-speed clock signal fr. Therefore, when multiplying by 512, the divider 6 shifts the count data to the right by 5 (= 9−4) bits. Then, the upper 7 bits after the shift are set in the 8-bit down counter 8 via the upper data register 7, and the lower 4 bits are set in the lower data register 9 for phase difference pulse selection.

  When the count enable signal is output, the down counter 8 starts down counting. From the time when the count value becomes “2”, 16 phase differences (high speed) selected according to the value of the lower 4 bits. A multiplied clock signal is output in accordance with the timing of one rising edge of a pulse (having 16 times the resolution of the clock signal fr).

  The data set in the register 9 is added so as to be doubled in the pulse selector 10 every time the multiplied clock signal fm is output. When the data value exceeds “15” and a carry occurs, the down counter 8 From the time when the count value becomes “1”, the multiplied clock signal is output in accordance with the timing of the rising edge of the phase difference pulse.

The above control is performed based on a state counter in which eight cycles (256 μs) of the reference clock signal fs are one control cycle. The period measurement of the reference clock signal fs is performed in the fourth state of the control period, is determined in the fifth state, and is latched as an arithmetic processing target in the sixth state. The latched data is cleared in the eighth state.
The clock signal having a frequency of 16 MHz multiplied by 512 is divided by two for waveform shaping at the final stage and output as a multiplied clock signal fm of 8 MHz.

FIG. 9 schematically shows a circuit arrangement of the microcomputer 12 that includes the clock signal output circuit 11 as described above and is configured on the same semiconductor substrate. The internal power supply circuit 13 generates a power supply voltage of 3.3 V from a power supply of 5 V supplied from the outside of the microcomputer 12 via the power supply input terminal 5V_IN. The 3.3V internal power supply is configured to supply the power supply wiring 14 to each circuit unit inside the microcomputer 12 after passing through the power supply terminals 3V_OUT and 3V_IN once through the outside of the microcomputer 12. This is to improve the effect of the low-pass filter configured to include the resistance component of the external wiring by externally attaching the power supply noise removing capacitor 15 to the microcomputer 12.
The power supply wiring 14 supplies power to the clock signal output circuit 11 after supplying power to the digital circuit group 17 including the CPU (not shown) and the communication block 16 in the microcomputer 12. Has been routed. This is because the clock signal output circuit 11 is preferably arranged at a location distant from the external terminal in order to minimize the influence of external high frequency noise.

The digital circuit group 17 includes a circuit portion that operates in synchronization with the multiplied clock signal fm generated and output from the clock signal output circuit 11. The internal power supply circuit 13 is connected to an analog ground, and the clock signal output circuit 11 and the digital circuit group 17 are connected to a digital ground (represented by different symbols). Note that the digital ground and the analog ground are arranged separately on the substrate of the microcomputer 12, but are connected via an external terminal of the microcomputer 12.
JP-A-8-265111

By the way, in the digital circuit group 17, the current consumption changes in accordance with the operation state of the circuit portion that operates in synchronization with the clock (ΔI). Therefore, when the circuit arrangement as shown in FIG. 9 is adopted, if the power supply wiring 14 has a resistance component R, a voltage variation of (ΔI · R) occurs.
In the clock signal output circuit 11 configured as described above, the propagation delay time of the INV gate 2 configuring the ring oscillator 1 varies according to the variation of the power supply voltage, so that the measurement data of the reference clock cycle varies. The frequency accuracy of the multiplied clock signal fm may be reduced. Then, since the decrease in frequency accuracy also affects the operation of the digital circuit group 17, for example, there is a problem that the accuracy of the communication function in the communication block 16 also decreases.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an integrated circuit capable of avoiding as much as possible the influence of power fluctuation caused by the operation of the internal circuit based on the multiplied clock signal from reaching the clock signal output circuit. Is to provide.

  According to the integrated circuit of the first aspect, the wiring of the internal power supply is routed from the internal circuit to the clock signal output circuit through the internal circuit, and in the wiring path from the internal circuit to the clock signal output circuit. A power supply noise reduction means is arranged. Therefore, even if the internal power supply voltage fluctuates as the current consumption of the internal circuit fluctuates, and the fluctuation is going to propagate through the power supply wiring as high frequency noise, the noise propagation is prevented by the power noise reduction means. be able to. Therefore, it is possible to suppress the fluctuation of the power supply voltage supplied to the clock signal output circuit and improve the frequency accuracy of the multiplied clock signal.

  According to the integrated circuit of the second aspect, since the ground noise reducing means is arranged on the ground side of the clock signal output circuit, the noise component to be propagated to the clock signal output circuit side via the ground wiring is reduced to reduce the ground. Potential fluctuation can be suppressed. Therefore, an effect substantially equivalent to suppressing the fluctuation of the power supply voltage can be obtained.

  According to the integrated circuit of the third aspect, the noise reduction means is arranged on the first power supply terminal side for supplying power to the ring oscillator in the clock signal output circuit. That is, since it is the ring oscillator that is largely affected by the power supply voltage fluctuation inside the clock signal output circuit, the frequency of the multiplied clock signal can be reduced by reducing the power supply noise and / or ground noise on the first power supply terminal side. Accuracy can be improved.

  According to the integrated circuit of the fourth aspect, since the noise reduction means is composed of a low-pass filter, noise components that are to propagate through the power supply wiring and / or the ground wiring can be released to the ground side or the power supply side and removed. it can.

  According to the integrated circuit of the fifth aspect, the ground of the clock signal output circuit and the internal circuit is connected to the first circuit ground, and the ground of the low-pass filter as the power supply noise reducing means is connected to the second circuit ground side. Then, a relatively large current flows through the first circuit ground due to the digital operation of the circuit, but the current flowing through the second circuit ground is relatively small, so that the ground potential is stabilized. Therefore, if the high-frequency noise superimposed on the power supply wiring is released to the second circuit ground side through the low-pass filter, the noise removal effect can be improved.

According to the integrated circuit of the sixth aspect, since the cutoff frequency changing means for changing the cutoff frequency of the low-pass filter is provided, the constant of the filter is set so that the noise removal effect is optimized according to the actual wiring state. It can be changed later.
According to the integrated circuit of the seventh aspect, when conduction control data is set in the control register, the conduction state of the switching element can be controlled according to the data, and a plurality of resistance elements constituting the low-pass filter are selected. Can be activated to change the filter constants.

According to the integrated circuit of the eighth aspect, even when the power supply noise reduction means has insufficient driving capability to supply power to the circuit portion after the clock signal output circuit, the voltage follower circuit can be used. The shortage can be compensated for, and a voltage drop due to insufficient drive capability can be prevented.
According to the integrated circuit of the ninth aspect, since the transistor for increasing the current supply capability is arranged on the output side of the voltage follower circuit, even if the current supply capability is insufficient only by the voltage follower circuit, the shortage of the current supply capability is reduced. Can be supplemented.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIG. The same parts as those in FIG. 8 or FIG. 9 are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below. The microcomputer (integrated circuit) 21 of the present embodiment includes a low-pass filter (power supply noise reduction means) in a path in which the power supply wiring 14 supplies power to the clock signal output circuit 11 via the digital circuit group (internal circuit) 17. ) 22 is arranged. That is, the resistance element 22R is inserted in series in the power supply wiring 14, and the common connection point between the resistance element 22R and the power supply terminal of the clock signal output circuit 11 is connected to the analog ground via the capacitor 22C. Other configurations are the same as those shown in FIG.

  Next, the operation of this embodiment will be described. When the current consumption of the digital circuit group 17 changes due to a change in the ratio of the circuit portions that operate in synchronization with the clock in the digital circuit group 17, the internal power supply voltage varies according to the wiring resistance or impedance of the power supply wiring 14. . When the voltage fluctuation attempts to propagate as high frequency noise to the clock signal output circuit 11 side via the power supply wiring 14, the noise component is released to the analog ground side by the low-pass filter 22 and removed. Therefore, the influence of the power supply voltage fluctuation is prevented from affecting the clock signal output circuit 11 side, and the oscillation accuracy of the multiplied clock signal fm by the clock signal output circuit 11 is improved.

  As described above, according to the present embodiment, since the low-pass filter 22 is disposed in the path in which the power supply wiring 14 supplies power to the clock signal output circuit 11 via the digital circuit group 17, the power supply wiring 14 will propagate. Can be eliminated by escaping to the analog ground side. The oscillation accuracy of the multiplied clock signal fm by the clock signal output circuit 11 can be improved, and the communication accuracy of the communication block 16 in the digital circuit group 17 operating in synchronization with the multiplied clock signal fm can be improved. Become.

  Further, according to the present embodiment, the grounds of the clock signal output circuit 11 and the digital circuit group 17 are connected to the digital ground (first circuit ground), and the low-pass filter 22 is connected to the analog ground (second circuit ground) side. . That is, a relatively large current flows through the digital ground as the circuit operates digitally, but the current flowing through the analog ground is relatively small, so that the ground potential is stabilized. Therefore, the high frequency noise superimposed on the power supply wiring 14 can be released to the analog ground side via the low-pass filter 22 to improve the noise removal effect.

(Second embodiment)
FIG. 2 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. In the clock signal output circuit 11A constituting the microcomputer 21A of the second embodiment, a terminal VDD1 (first power supply terminal) that supplies power to the ring oscillator 1 and a terminal VDD2 that supplies power to the other circuit section 11Aa. (Second power supply terminal). The other circuit unit 11Aa includes a cycle counter 4, a down counter 8, a pulse selector 10 and the like shown in FIG. The power supply terminal VDD2 is directly connected to the power supply wiring 14, and the power supply terminal VDD1 is connected to the output terminal of the low-pass filter 22.

  According to the second embodiment configured as described above, since the low-pass filter 22 is arranged on the power supply terminal VDD1 side for supplying power to the ring oscillator 1 in the clock signal output circuit 11A, the clock signal output circuit 11A The frequency accuracy of the multiplied clock signal fm can be improved by reducing the power supply noise on the ring oscillator 1 side that is largely affected by the fluctuation of the power supply voltage inside.

(Third embodiment)
FIG. 3 shows a third embodiment of the present invention, and only different portions from the second embodiment will be described. In the microcomputer 21B of the third embodiment, in addition to the configuration of the second embodiment, a low-pass filter (ground noise reduction means) 23 is also arranged on the ground terminal side of the ring oscillator 1 in the clock signal output circuit 11A. is there. In other words, the ground terminal of the clock signal output circuit 11A is connected to the digital ground via the resistance element 23R and is connected to its own power supply terminal via the capacitor 23C.

  According to the third embodiment configured as described above, the noise superimposed on the power supply wiring 14 is removed to the analog ground side via the low-pass filter 22, and the noise superimposed on the digital ground is removed from the low-pass filter 23. This is removed to the power source side of the ring oscillator 1 via the. That is, the power supply wiring 24 between the output terminal of the low-pass filter 22 and the power supply terminal of the ring oscillator 1 shows a stable potential from which noise is removed by the action of the low-pass filter 22. In contrast, noise superimposed on the digital ground is released. Therefore, by suppressing the fluctuation of the ground potential of the clock signal output circuit 11A, an effect substantially equivalent to suppressing the fluctuation of the power supply voltage can be obtained.

(Fourth embodiment)
FIG. 4 shows a fourth embodiment of the present invention, and only different portions from the first embodiment will be described. In the microcomputer 21C of the fourth embodiment, a voltage follower circuit 25 is arranged on the output terminal side of the low-pass filter 22 in the first embodiment, and power is supplied to the clock signal output circuit 11 via the voltage follower circuit 25. I have to. The voltage follower circuit 25 is operated by a 5V power supply supplied from the outside. According to the fourth embodiment configured as described above, the voltage follower circuit 25 can be provided to sufficiently supply the power supply current to the clock signal output circuit 11.

(5th Example)
FIG. 5 shows a fifth embodiment of the present invention, and only parts different from the fourth embodiment will be described. In the microcomputer 21D of the fifth embodiment, a P-channel MOSFET 26 for increasing the current supply capability is arranged on the output terminal side of the voltage follower circuit 25. That is, the source of the FET 26 is connected to the 5V power supply terminal, the gate is connected to the output terminal of the voltage follower circuit 25, and the drain is a non-inverting input terminal (clock signal output circuit 11) of the operational amplifier constituting the voltage follower circuit 25. Power supply terminal).
According to the fifth embodiment configured as described above, the FET 26 changes its conduction state in accordance with the output voltage level of the voltage follower circuit 25 and acts to supply the power supply current from the 5V power supply. Therefore, even if the supply of power supply current is insufficient with the voltage follower circuit 25 alone, the shortage can be compensated by the current supplied via the FET 26.

(Sixth embodiment)
FIGS. 6 and 7 are partial equivalent views of FIG. 1 showing the sixth embodiment of the present invention, and different parts from the fifth embodiment will be described. The microcomputer 21E of the sixth embodiment is configured so that the cut-off frequency of the low-pass filter can be changed. That is, the low-pass filter (power supply noise reduction means) 27 is connected to, for example, a common connection point between three resistance elements 27Ra to 27Rc connected in series, and the resistance element 27Rc and the inverting input terminal of the operational amplifier constituting the voltage follower circuit 25. And a capacitor 27C.

  Further, P-channel MOSFETs (switching elements) 28a to 28c are connected in parallel to both ends of each of the resistance elements 27Ra to 27Rc, and each gate of the FETs 28a to 28c is a resistance value setting register (control register). 29 corresponding data output terminals are respectively connected. An application program 31 of a CPU included in the digital circuit group 17 is written and stored in a non-volatile memory 30 composed of an EEPROM, a flash ROM, or the like. Then, when the application program 31 is executed by the CPU after the reset is released, the resistance setting value 32 stored together with the program 31 as an initial setting is written in the resistance value setting register 29.

  Then, the FETs 28 a to 28 c are turned on / off according to the resistance setting value 32 (conduction control data: 0, 1) written in the resistance value setting register 29. When the FET 28 is turned on, the corresponding resistance element 27R is bypassed, so that the resistance value of the resistance element 27R does not contribute to the determination of the cutoff frequency of the low-pass filter 27. The FETs 28a to 28c and the resistance value setting register 29 constitute a cutoff frequency changing unit 33.

Next, how to determine the cutoff frequency of the low-pass filter 27 will be described with reference to FIG. As shown in FIG. 7A, for example, in the low-pass filter 22 of the first embodiment, when the input voltage of the low-pass filter 22 fluctuates as ΔVin (2πf · j) (f is a fluctuating frequency), the output of the low-pass filter 22 If the voltage fluctuation is ΔVout (2πf · j), the gain H (2πf · j) of the low-pass filter 22 is
H (2πf · j) = ΔVout (2πf · j) / ΔVin (2πf · j)
Represented as:
Further, when the load current fluctuation is ΔId (2πf · j) as shown in FIG. 7B, the output voltage fluctuation in the internal power supply circuit (internal power generation circuit) 13 is ΔVd (2πf · j). Then, the responsive impedance Zd (2πf · j) of the internal power supply circuit 13 is
Zd (2πf · j) = ΔVd (2πf · j) / ΔId (2πf · j)
It becomes. This responsive impedance Zd can be calculated by circuit simulation.

FIG. 7C shows the gain H of the low-pass filter 22 to be set with respect to the responsive impedance Zd. That is, if the limit frequency of the responsiveness due to the responsive impedance | Zd (2πf · j) | is, for example, f2, the cutoff frequency fc = 1 / (2πRf ··) determined by the filter gain | H (2πf · j) | Cf) is set to be equal to or lower than the limit frequency f2. Further, if the consumption current fluctuation frequency when the digital circuit group 17 operates is f1 (<f2), the cut-off frequency fc needs to be set so that the fluctuation frequency is sufficiently lower than f1. That is,
fc = 1 / (2πRf · Cf) << f1, and fc = 1 / (2πRf · Cf) << f2.
The cut-off frequency fc may be selected so that

As described above, according to the sixth embodiment, since the cutoff frequency changing means 33 for changing the cutoff frequency of the low-pass filter 27 is provided, the noise removal effect of the low-pass filter 27 is optimal according to the actual wiring state. In this way, the filter constant can be changed later.
Specifically, the low-pass filter 27 is composed of resistance elements 27Ra to 27Rc and a capacitor 27C, and the cut-off frequency changing means 33 is connected to the resistance elements corresponding to 27Ra to 27Rc in parallel with the FETs 28a to 28c, respectively. Since the resistance value setting register 29 for outputting the conduction control data to the gates of the FETs 28a to 27c is constituted, if the conduction control data is written and set in the resistance value setting register 29, the FET 28 is turned on / off according to the data. And the constants of the filter 27 can be changed by selectively enabling the resistance elements 27Ra to 27Rc constituting the low-pass filter 27.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
For example, a data register for storing a value obtained by adding “1” to the data value data value X of the upper data register 7 is prepared as the clock signal output circuit, and the data value “16” is set in the lower data register 9. The quotient Y obtained by dividing the 4-bit data value by “1” is obtained, and one out of Y times causes the down counter 8 to down-count the data value (X + 1), and (Y−1) times the data value. You may comprise so that X may be counted down. In the case of such a configuration, the multiplied clock signal fm can be equivalently expressed with a resolution less than the period of the high-speed clock signal fr without using the phase difference pulse generated by the ring oscillator 1.

The frequency of the reference clock signal fs and the high-speed clock signal fr may be changed as appropriate. The same applies to the division ratio of the reference clock signal fs and the multiplication factor in the clock signal output circuit.
The digital circuit group 17 does not necessarily include the communication block 16.
The configuration of the third embodiment may be applied to the configuration of the first embodiment. Further, the cutoff frequency changing means in the sixth embodiment may be similarly applied to the low-pass filter 23 on the ground side in the third embodiment.
Further, the configuration of the fourth to sixth embodiments may be applied to the configuration of the second or third embodiment.
The switching element constituting the transistor for increasing the current supply capability and the cutoff frequency changing means is not limited to the P-channel MOSFET, but may be an N-channel MOSFET or a bipolar transistor.

1 is a diagram showing a circuit arrangement inside a microcomputer according to a first embodiment of the present invention. FIG. 1 equivalent view showing a second embodiment of the present invention. FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. 1 is a partial equivalent diagram of FIG. 1 showing a sixth embodiment of the present invention. (A) is the gain H of the low-pass filter, (b) is the response impedance Zd of the internal power supply circuit, and (c) is a diagram for explaining the gain H of the low-pass filter to be set with respect to the response impedance Zd. Functional block diagram showing the configuration of the clock signal output circuit 1 equivalent diagram showing the prior art

Explanation of symbols

  In the drawings, 1 is a ring oscillator, 11 is a clock signal output circuit, 13 is an internal power supply circuit (internal power generation circuit), 14 is power supply wiring, 17 is a digital circuit group (internal circuit), and 21 is a microcomputer (integrated circuit). , 22 is a low-pass filter (power supply noise reduction means), 23 is a low-pass filter (ground noise reduction means), 25 is a voltage follower circuit, 26 is a P-channel MOSFET, 27 is a low-pass filter (power supply noise reduction means), and 27Ra to 27Rc are A resistor element, 27C is a capacitor, 28a to 28c are P-channel MOSFETs (switching elements), 29 is a resistance value setting register (control register), and 33 is a cutoff frequency changing means.

Claims (9)

By including a ring oscillator configured by connecting a plurality of delay gates in a ring shape, and performing arithmetic processing based on data obtained by counting the period of the reference clock signal by a high-speed clock signal generated by the ring oscillator, A clock signal output circuit for generating and outputting a multiplied clock signal obtained by multiplying the frequency of the reference clock signal;
An internal circuit that operates when supplied with the multiplied clock signal;
An internal power supply that generates a stabilized internal power supply by stepping down the power supply voltage based on an externally supplied power supply, and supplies the clock signal output circuit and the internal power supply circuit to the internal circuit on the same semiconductor substrate. In the integrated circuit formed in
The wiring of the internal power supply is routed so as to reach the clock signal output circuit after passing through the internal circuit first, and power supply noise reduction means is provided in the wiring path from the internal circuit to the clock signal output circuit. An integrated circuit characterized by being arranged.   2. The integrated circuit according to claim 1, wherein a ground noise reducing means is disposed on the ground side of the clock signal output circuit. The clock signal output circuit includes a first power supply terminal for supplying power to the ring oscillator, and a second power supply terminal for supplying power to other circuit units,
The integrated circuit according to claim 1, wherein the noise reduction unit is disposed at least on the first power supply terminal side.   4. The integrated circuit according to claim 1, wherein the noise reduction means is constituted by a low-pass filter. Comprising first and second circuit grounds arranged to be separated on the substrate;
Connecting the ground of the clock signal output circuit and the internal circuit to the first circuit ground;
5. The integrated circuit according to claim 4, wherein a ground of a low-pass filter as the power supply noise reducing means is connected to the second circuit ground side.   6. The integrated circuit according to claim 4, further comprising cutoff frequency changing means for changing the cutoff frequency of the low-pass filter. The low-pass filter is composed of a plurality of resistance elements and capacitors,
The cutoff frequency changing means is
A plurality of switching elements respectively connected in parallel corresponding to the plurality of resistance elements;
7. The integrated circuit according to claim 6, further comprising a control register for outputting conduction control data to the conduction control terminals of the plurality of switching elements.   8. The integrated circuit according to claim 1, wherein a voltage follower circuit is disposed on the output side of the power supply noise reduction means. 9. The integrated circuit according to claim 8, wherein a transistor for increasing a current supply capability is disposed on an output side of the voltage follower circuit.

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