JP4343327B2 - Method for forming circuit pattern - Google Patents
Method for forming circuit pattern Download PDFInfo
- Publication number
- JP4343327B2 JP4343327B2 JP13537499A JP13537499A JP4343327B2 JP 4343327 B2 JP4343327 B2 JP 4343327B2 JP 13537499 A JP13537499 A JP 13537499A JP 13537499 A JP13537499 A JP 13537499A JP 4343327 B2 JP4343327 B2 JP 4343327B2
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- JP
- Japan
- Prior art keywords
- circuit pattern
- pattern
- base
- cut
- unnecessary
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Description
【０００１】
【発明の属する技術分野】
本発明は回路パタ−ンの形成方法、特に抵抗式透明タッチパネル、メンブレインスイッチ、フレキシブルなプリント回路基板、プリント回路基板等に幅広く応用できる電気回路パタ−ンの形成方法に関する。
【０００２】
【発明の背景】
従来、上記した回路パタ−ンを成形作製するためには、エッチング作業が不可欠のものとなり、また、試作品等の小量生産品については回路パタ−ン作成用の版代がかかってしまうものとなっていた。
【０００３】
【発明の目的】
そこで、本発明は上記した従来の回路パタ−ン成形における問題点、実情に着目してなされたもので、かかる問題点を解消して、エッチング作業、それに伴う設備や版等を不要として、能率よく短時間で、コストがかからず、しかも信頼性の高い製品を得ることができることとした回路パタ−ンの形成方法を提供することを目的としている。
【０００４】
【課題を解決するための手段】
この目的を達成するために、本発明に係る回路パターンの形成方法はベース上に積層具備された導電層を、前記ベースに至るまで切り込みを入れることでカットして必要パターン部と不必要パターン部とを分離し、前記したカットによって生ずる切り込み溝に絶縁部を埋め込む回路パターンの形成方法において、前記した不必要パターン部の上表面に絶縁物を塗布し、その絶縁物上に必要なパターンを成形することを特徴としている。
【０００５】
また、本発明に係る回路パターンの形成方法はベース上に積層具備された導電層を、前記ベースに至るまで回路パターンよりも幅広く切り込みを入れることでカットする回路パターンの形成方法において、そのカットによって露呈されるベース上面に必要な回路パターンを形成することを特徴としている。
【０００６】
【作用】
上記した成形方法とすることにより、エッチング作業や版の作成等は一切不要となって能率が向上し、コストも大きく節減することができ、絶縁物の存在によって回路としての信頼性も向上することとなり、また、カットした部分に回路パタ−ンを成形することでパタ−ンの組み合せも幅広く望めることとなるのである。
【０００７】
【発明の実施の形態】
次に、本発明の実施の形態を図面を参照して説明する。図１は本発明を実施した回路パタ−ンの形成方法の第一の工程を示す断面図、図２は同じく第二の工程を示す断面図、図３は同じく第三の工程を示す断面図、図４は他の実施例を示す断面図である。
【０００８】
これらの図にあって１は基材を示しており、この基材１はベ−ス２の一方面に導電層３を積層具備したもので、例えば酸化インジュウムフィルム等の透明導電フィルム、ＰＥＴフィルム等に導電性インキ層を形成したもの、フレキシブルなプリント基板やプリント回路基板等々が対象となる。
【０００９】
まず、前記した基材１の導電層３の上方から、例えばレ−ザ−加工機４によって切り込み５・５…を入れ、必要なパタ−ン６・６…と不必要なパタ−ン７・７…とを分離させる。なお、前記したレ−ザ−加工機４に代えてカッティングプロッタ−、ＮＣ加工機その他導体を切断する機能をもった機械や器具を使用することができる。
【００１０】
また、前記した切り込み５・５…は導電層３のみならず、その導電層３を貫通してベ−ス２の上面にまで至るものとする。
【００１１】
次いで、上記のように形成された切り込み５・５…に例えばレジスト８・８…等の絶縁物を埋め込み必要なパタ−ン６・６…と不必要なパタ−ン７・７…とを電気的に断線させる。なお、このレジスト８・８…に代え絶縁インキ等を使用してもよく、切り込み５・５…の幅も目的に応じ自在に変更ができるもので、レジスト８・８…をはじめとする絶縁物の膜厚は目的とする断線効果が得られればよく、格別に特定されるものではない。
【００１２】
さらに、前記したレジスト８・８…の切り込み５・５…への埋め込みの後、そのレジスト８・８…の上面間に不必要なパタ−ン７・７…の上面を跨いでカバ−レジスト９・９…を塗布し、不必要なパタ−ン７・７…をレジスト８とカバ−レジスト９とによって全体的に被包する。なお、この際、不必要なパタ−ン７がベ−ス２上で最端部に位置する場合、その不必要なパタ−ン７の外側面は露呈されたままの状態とすればよい。さらに、このカバ−レジスト９上に必要なパタ−ン６ａを形成することとしてもよい。また、この工程におけるカバ−レジスト９も他の絶縁インキ等の絶縁物で代替することは可能である。
【００１３】
また、図４として示すのは他の実施例であり、この場合はレ−ザ−加工機４、その他の機械や器具を用いて切り込み５・５…を幅広く形成し、その切り込み５・５…の底面に露出されたベ−ス２の上面に別途に回路パタ−ン１０・１０…を例えばプリントすることで成形する。この方法は既述した成形方法と併せて実施することも可能となり、回路としての組み合わせも広がるものとなる。
【００１４】
前記した切り込み５・５…内にプリントすることで成形された回路パタ−ン１０・１０…は切り込み５・５…内に埋め込まれたレジスト１１等絶縁物で覆うことで信頼性が高められる。
【００１５】
【発明の効果】
本発明に係る回路パタ−ンの形成方法は上述のように構成されている。そのため、従来のようなエッチング作業が不要となり、そのエッチングのための時間や設備が一切いらなくなり、能率が大きく向上し、また、版代も不要となってコストの低廉化が図れることとなり、加えて回路としての信頼性も向上するものとなっている。
【図面の簡単な説明】
【図１】本発明を実施した回路パタ−ンの成形方法を示す第一の工程の断面図である。
【図２】第二の工程を示す断面図である。
【図３】第三の工程を示す断面図である。
【図４】他の実施例を示す断面図である。
【符号の説明】
１ 基材
２ ベ−ス
３ 導電層
４ レ−ザ−加工機
５ 切り込み
６ 必要なパタ−ン
６ａ 必要なパタ−ン
７ 不必要なパタ−ン
８ レジスト
９ カバ−レジスト
１０ 回路パタ−ン
１１ レジスト[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for forming a circuit pattern, and more particularly to a method for forming an electric circuit pattern that can be widely applied to a resistive transparent touch panel, a membrane switch, a flexible printed circuit board, a printed circuit board, and the like.
[0002]
BACKGROUND OF THE INVENTION
Conventionally, in order to mold and produce the above circuit pattern, etching work is indispensable, and for small-volume products such as prototypes, a plate cost for creating a circuit pattern is required. It was.
[0003]
OBJECT OF THE INVENTION
Therefore, the present invention has been made by paying attention to the problems and actual situations in the conventional circuit pattern molding described above, and eliminates such problems and eliminates the need for etching work, accompanying equipment and plates, etc. It is an object of the present invention to provide a method for forming a circuit pattern, which is capable of obtaining a highly reliable product in a short time, at a low cost.
[0004]
[Means for Solving the Problems]
In order to achieve this object, a circuit pattern forming method according to the present invention cuts a conductive layer laminated on a base by cutting it up to the base, thereby forming a necessary pattern portion and an unnecessary pattern portion. In the method of forming a circuit pattern in which an insulating portion is embedded in a cut groove generated by the above-described cutting , an insulating material is applied to the upper surface of the unnecessary pattern portion, and a necessary pattern is formed on the insulating material. It is characterized by doing.
[0005]
The circuit pattern forming method according to the present invention is a circuit pattern forming method in which a conductive layer stacked on a base is cut by cutting wider than the circuit pattern up to the base. It is characterized by forming a necessary circuit pattern on the exposed upper surface of the base.
[0006]
[Action]
By using the above-mentioned forming method, it is unnecessary to perform any etching work or creating a plate, so that the efficiency is improved, the cost can be greatly reduced, and the reliability as a circuit is improved by the presence of an insulator. In addition, a wide variety of pattern combinations can be expected by forming a circuit pattern in the cut portion.
[0007]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings. 1 is a cross-sectional view showing a first step of a circuit pattern forming method embodying the present invention, FIG. 2 is a cross-sectional view showing a second step, and FIG. 3 is a cross-sectional view showing a third step. FIG. 4 is a sectional view showing another embodiment.
[0008]
In these drawings, reference numeral 1 denotes a base material. The base material 1 is provided with a conductive layer 3 laminated on one surface of a base 2, for example, a transparent conductive film such as an indium oxide film, PET, and the like. This includes a film in which a conductive ink layer is formed, a flexible printed circuit board, a printed circuit board, and the like.
[0009]
First, from the upper side of the conductive layer 3 of the substrate 1, for example, a laser processing machine 4 is used to make cuts 5 · 5 ···, and necessary patterns 6 · 6 ··· and unnecessary patterns 7 ···. 7 are separated. Instead of the laser processing machine 4 described above, a cutting plotter, an NC processing machine, or other machines or instruments having a function of cutting conductors can be used.
[0010]
In addition, the above-described cuts 5, 5, and the like penetrate not only the conductive layer 3 but also the conductive layer 3 to reach the upper surface of the base 2.
[0011]
Next, the notches 5 and 5 formed as described above are electrically connected with patterns 6 and 6 that need to be filled with an insulator such as resists 8 and 8 and patterns 7 and 7 that are unnecessary. Disconnect. Insulating ink or the like may be used in place of the resists 8, 8 ..., and the widths of the cuts 5, 5 ... can be freely changed according to the purpose. Insulators including the resists 8, 8 ... The film thickness is not particularly specified as long as the desired disconnection effect can be obtained.
[0012]
Further, after embedding the resists 8... Into the cuts 5..., The cover resists 9 are formed across the upper surfaces of the unnecessary patterns 7. ... Are applied, and unnecessary patterns 7, 7... Are entirely encapsulated by the resist 8 and the cover resist 9. At this time, if the unnecessary pattern 7 is located at the end on the base 2, the outer surface of the unnecessary pattern 7 may be left exposed. Further, a necessary pattern 6a may be formed on the cover resist 9. In addition, the cover resist 9 in this process can be replaced with another insulating material such as insulating ink.
[0013]
FIG. 4 shows another embodiment. In this case, the laser cutting machine 4 and other machines and instruments are used to form a wide range of cuts 5. Are separately formed on the upper surface of the base 2 exposed on the bottom surface of the substrate by, for example, printing. This method can be carried out in combination with the above-described forming method, and the combination as a circuit can be expanded.
[0014]
The circuit pattern 10 · 10 ··· that is formed by printing in the cuts 5 · 5 ··· is covered with an insulating material such as a resist 11 embedded in the cuts 5 · 5 ··· so that the reliability is improved.
[0015]
【The invention's effect】
The circuit pattern forming method according to the present invention is configured as described above. This eliminates the need for conventional etching operations, eliminates the time and facilities for the etching, greatly improves efficiency, and eliminates the need for plate cost, thereby reducing costs. Therefore, the reliability as a circuit is also improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a first process showing a circuit pattern forming method embodying the present invention.
FIG. 2 is a cross-sectional view showing a second step.
FIG. 3 is a cross-sectional view showing a third step.
FIG. 4 is a cross-sectional view showing another embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Base material 2 Base 3 Conductive layer 4 Laser processing machine 5 Cut 6 Necessary pattern 6a Necessary pattern 7 Unnecessary pattern 8 Resist 9 Cover resist 10 Circuit pattern 11 Resist
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13537499A JP4343327B2 (en) | 1999-05-17 | 1999-05-17 | Method for forming circuit pattern |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13537499A JP4343327B2 (en) | 1999-05-17 | 1999-05-17 | Method for forming circuit pattern |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000332386A JP2000332386A (en) | 2000-11-30 |
| JP4343327B2 true JP4343327B2 (en) | 2009-10-14 |
Family
ID=15150232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13537499A Expired - Fee Related JP4343327B2 (en) | 1999-05-17 | 1999-05-17 | Method for forming circuit pattern |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4343327B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011199579A (en) * | 2010-03-19 | 2011-10-06 | Seiko Epson Corp | Electronic device and method for manufacturing electronic device |
-
1999
- 1999-05-17 JP JP13537499A patent/JP4343327B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000332386A (en) | 2000-11-30 |
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