JP4338105B1 - High voltage generation circuit - Google Patents

High voltage generation circuit Download PDF

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JP4338105B1
JP4338105B1 JP2008322402A JP2008322402A JP4338105B1 JP 4338105 B1 JP4338105 B1 JP 4338105B1 JP 2008322402 A JP2008322402 A JP 2008322402A JP 2008322402 A JP2008322402 A JP 2008322402A JP 4338105 B1 JP4338105 B1 JP 4338105B1
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哲也 徳永
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Hugle Electronics Inc
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Abstract

【課題】比較的安価な部品を用いて構成し、消費電流や放電のおそれを少なくすると共に、出力電圧を低下させずに正負バランス良く高電圧を出力可能とした高電圧発生回路を提供する。
【解決手段】正電圧パルスを出力する第1の倍電圧整流回路9Pを備えた正側高電圧発生部10Pと、負電圧パルスを発生する第2の倍電圧整流回路9Nを備えた負側高電圧発生部10Nと、を有し、正側及び負側高電圧発生部10P,10Nの出力電圧を加算して出力する高電圧発生回路において、倍電圧整流回路9P,9N内の最終段のツェナーダイオードとコンデンサとの接続点21P,21N同士を直接接続し、電流制限抵抗8を介して出力端子23に接続する。
【選択図】図1
A high voltage generation circuit is provided that uses a relatively inexpensive part to reduce the current consumption and the risk of discharge, and that can output a high voltage with a positive and negative balance without lowering the output voltage.
A positive-side high voltage generator 10P having a first voltage doubler rectifier circuit 9P that outputs a positive voltage pulse and a negative high voltage generator 9N having a second voltage doubler rectifier circuit 9N that generates a negative voltage pulse. Voltage generator 10N, and a high-voltage generator circuit that adds and outputs the output voltages of positive and negative high-voltage generators 10P and 10N, and a final stage Zener in voltage doubler rectifier circuits 9P and 9N The connection points 21P and 21N between the diode and the capacitor are directly connected to each other and connected to the output terminal 23 through the current limiting resistor 8.
[Selection] Figure 1

Description

本発明は、例えばイオナイザの放電電極に印加される高電圧を発生するための高電圧発生回路に関するものである。   The present invention relates to a high voltage generation circuit for generating a high voltage applied to, for example, a discharge electrode of an ionizer.

図3は、特許文献1に記載されたイオナイザの回路構成図である。
図3において、制御回路1から出力される正側の制御信号は、主電源(図示せず)によりオンするスイッチ3Pを介して正側の発振回路2Pに入力されている。また、制御回路1から出力される負側の制御信号は、そのまま負側の発振回路2Nに入力されている。
FIG. 3 is a circuit configuration diagram of an ionizer described in Patent Document 1.
In FIG. 3, the positive control signal output from the control circuit 1 is input to the positive oscillation circuit 2P via a switch 3P that is turned on by a main power supply (not shown). Further, the negative control signal output from the control circuit 1 is input to the negative oscillation circuit 2N as it is.

正側の発振回路2Pからは高周波の交流電圧が出力され、この交流電圧は、正側高電圧発生部6P内のトランス4Pを介して倍電圧整流回路5Pにより昇圧、整流され、図4(a)に示すような正電圧パルス(振幅を+Pとする)として正側端子21Pから接続点22に出力される。なお、上記倍電圧整流回路5Pにおいて、C1〜C4はコンデンサ、D1〜D4はダイオード、ZD1〜ZD4はツェナーダイオードである。 A high-frequency AC voltage is output from the positive-side oscillation circuit 2P, and this AC voltage is boosted and rectified by the voltage doubler rectifier circuit 5P via the transformer 4P in the positive-side high-voltage generator 6P. is output from the positive side terminal 21P to the connection point 22 as) shows such a positive voltage pulse (a + P 1 amplitude). In the voltage doubler rectifier circuit 5P, C1 to C4 are capacitors, D1 to D4 are diodes, and ZD1 to ZD4 are zener diodes.

一方、負側の発振回路2Nからは高周波の交流電圧が出力され、この交流電圧は、負側高電圧発生部6N内のトランス4Nを介して倍電圧整流回路5Nにより昇圧、整流され、負側端子21Nから出力される。更に、この整流電圧は、抵抗7を介して、図4(b)に示すような負の直流バイアス電圧(振幅を−Nとする)となって接続点22に出力される。なお、倍電圧整流回路5Nにおいて、C5〜C8はコンデンサ、D5〜D8はダイオードである。   On the other hand, a high-frequency AC voltage is output from the negative-side oscillation circuit 2N, and this AC voltage is boosted and rectified by the voltage doubler rectifier circuit 5N via the transformer 4N in the negative-side high voltage generator 6N, and the negative side Output from terminal 21N. Further, this rectified voltage is output to the connection point 22 through the resistor 7 as a negative DC bias voltage (with an amplitude of −N) as shown in FIG. In the voltage doubler rectifier circuit 5N, C5 to C8 are capacitors, and D5 to D8 are diodes.

このため、接続点22の電圧は、図4(c)に示すように、図4(a)の正電圧パルスに図4(b)の負の直流バイアス電圧を重畳した交流パルス電圧となる。この交流パルス電圧の正側の振幅は+P、負側の振幅は−Nであり、P=P−Nである。
図4(c)に示す交流パルス電圧を、図3の電流制限抵抗8を介して出力端子23から放電電極(図示せず)に印加することにより、対向電極との間にコロナ放電を生じさせて放電電極の周囲の空気をイオン化し、正負イオンを発生させることになる。
Therefore, as shown in FIG. 4C, the voltage at the connection point 22 is an AC pulse voltage obtained by superimposing the negative DC bias voltage shown in FIG. 4B on the positive voltage pulse shown in FIG. The positive-side amplitude of this AC pulse voltage is + P, and the negative-side amplitude is -N, and P = P 1 -N.
By applying the AC pulse voltage shown in FIG. 4C to the discharge electrode (not shown) from the output terminal 23 via the current limiting resistor 8 shown in FIG. 3, a corona discharge is generated between the counter electrode and the counter electrode. Thus, the air around the discharge electrode is ionized to generate positive and negative ions.

上記従来技術では、例えば正側の発振回路2Pの発振周波数を可変とすることにより、図4(c)に示した交流パルス電圧の周波数を変化させることができると共に、図4(b)の負の直流バイアス電圧の大きさを変化させれば、図4(c)に示した交流パルス電圧の振幅を変化させることも可能となっている。   In the above prior art, for example, by making the oscillation frequency of the positive oscillation circuit 2P variable, the frequency of the AC pulse voltage shown in FIG. 4C can be changed, and the negative frequency shown in FIG. If the magnitude of the DC bias voltage is changed, the amplitude of the AC pulse voltage shown in FIG. 4C can be changed.

特許第4111348号公報([0013]〜[0026],図1,図2等)Japanese Patent No. 4111348 ([0013] to [0026], FIG. 1, FIG. 2, etc.)

しかしながら、図3の従来技術では、負の高電圧が印加される抵抗7として高耐圧の部品を用いなくてはならず、コストが高くなる懸念がある。
また、正側端子21Pと負側端子21Nとの間の電位差は、最大で|P+N|となって大きな値になるため、両端子21P,21N間で放電するおそれがある。
更に、抵抗7を通して図4(b)の直流バイアス電圧による電流が常時流れているので、抵抗7による消費電力、つまり損失が多くなり、その分、出力端子23から出力される電圧が低下してしまう等の問題があった。
However, in the prior art shown in FIG. 3, a high breakdown voltage component must be used as the resistor 7 to which a negative high voltage is applied, and there is a concern that the cost may increase.
In addition, since the potential difference between the positive terminal 21P and the negative terminal 21N is a maximum value of | P 1 + N |, which is a maximum value, there is a possibility of discharging between both terminals 21P and 21N.
Furthermore, since the current due to the DC bias voltage of FIG. 4B always flows through the resistor 7, the power consumption, that is, the loss due to the resistor 7 increases, and the voltage output from the output terminal 23 decreases accordingly. There was a problem such as.

そこで、本発明の解決課題は、比較的安価な部品を用いて構成することができ、放電等のおそれを少なくすると共に、出力電圧を低下させずに正負バランス良く高電圧を出力可能とした高電圧発生回路を提供することにある。   Accordingly, the problem to be solved by the present invention is that it can be configured by using relatively inexpensive parts, and it is possible to output a high voltage with good balance between positive and negative without reducing the risk of discharge and the like and without decreasing the output voltage. The object is to provide a voltage generation circuit.

上記課題を解決するため、請求項1に記載した発明は、交流電圧が入力されて正電圧パルスを出力する第1の倍電圧整流回路を備えた正側高電圧発生部と、交流電圧が入力されて負電圧パルスを発生する第2の倍電圧整流回路を備えた負側高電圧発生部と、を有し、正側及び負側高電圧発生部の出力電圧を加算して出力する高電圧発生回路において、
第1及び第2の倍電圧整流回路は、交流電圧の入力端子間にコンデンサとツェナーダイオードとダイオードとを接続してなる直列回路を接続し、前記ツェナーダイオードとダイオードとの直列回路の両端に、コンデンサとツェナーダイオードとダイオードとを接続してなる直列回路を順次接続すると共に、各直列回路内のツェナーダイオードとダイオードとを逆方向に接続し、かつ、各直列回路内のコンデンサ同士が直接接続されないように各コンデンサを配置して構成され、
第1の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、第2の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、を直接接続して電流制限抵抗を介し出力端子に接続したものである。
In order to solve the above-mentioned problem, the invention described in claim 1 is directed to a positive high-voltage generator having a first voltage doubler rectifier circuit that receives an AC voltage and outputs a positive voltage pulse, and an AC voltage is input. And a negative high voltage generator having a second voltage doubler rectifier circuit for generating a negative voltage pulse, and adding the output voltages of the positive and negative high voltage generators to output the high voltage In the generator circuit,
The first and second voltage doubler rectifier circuits connect a series circuit formed by connecting a capacitor, a Zener diode, and a diode between the input terminals of the AC voltage, and at both ends of the series circuit of the Zener diode and the diode, A series circuit composed of a capacitor, a Zener diode, and a diode is connected in sequence, and the Zener diode and the diode in each series circuit are connected in the opposite direction, and the capacitors in each series circuit are not directly connected to each other. Is configured by placing each capacitor as
A connection point between the Zener diode and the capacitor in the series circuit at the final stage in the first voltage doubler rectifier circuit, and a connection point between the Zener diode and the capacitor in the series circuit at the final stage in the second voltage doubler rectifier circuit. Are connected directly to the output terminal via a current limiting resistor.

請求項2に記載した発明は、交流電圧が入力されて正電圧パルスを出力する第1の倍電圧整流回路を備えた正側高電圧発生部と、交流電圧が入力されて負電圧パルスを発生する第2の倍電圧整流回路を備えた負側高電圧発生部と、を有し、正側及び負側高電圧発生部の出力電圧を加算して出力する高電圧発生回路において、
第1及び第2の倍電圧整流回路は、交流電圧の入力端子間にコンデンサとツェナーダイオードと抵抗とダイオードとを接続してなる直列回路を接続し、前記ツェナーダイオードと抵抗とダイオードとの直列回路の両端に、コンデンサとツェナーダイオードと抵抗とダイオードとを接続してなる直列回路を順次接続すると共に、各直列回路内のツェナーダイオードとダイオードとを逆方向に接続し、かつ、各直列回路内のコンデンサ同士が直接接続されないように各コンデンサを配置して構成され、
第1の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、第2の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、を直接接続して電流制限抵抗を介し出力端子に接続したものである。
According to the second aspect of the present invention, a positive high voltage generator having a first voltage doubler rectifier circuit that receives an AC voltage and outputs a positive voltage pulse, and generates a negative voltage pulse when the AC voltage is input. A high-voltage generation circuit including a negative high-voltage generation unit including a second voltage doubler rectifier circuit, and adding and outputting the output voltages of the positive and negative high-voltage generation units.
In the first and second voltage doubler rectifier circuits, a series circuit formed by connecting a capacitor, a Zener diode, a resistor, and a diode is connected between the input terminals of the AC voltage, and the series circuit of the Zener diode, the resistor, and the diode is connected. A series circuit formed by connecting a capacitor, a Zener diode, a resistor, and a diode is sequentially connected to both ends of the capacitor, and the Zener diode and the diode in each series circuit are connected in the opposite direction, and Each capacitor is arranged so that the capacitors are not directly connected,
A connection point between the Zener diode and the capacitor in the series circuit at the final stage in the first voltage doubler rectifier circuit, and a connection point between the Zener diode and the capacitor in the series circuit at the final stage in the second voltage doubler rectifier circuit. Are connected directly to the output terminal via a current limiting resistor.

本発明によれば、出力側の高耐圧の抵抗を不要にしてコストの削減を図ることができ、また、動作原理上、負側高電圧発生部に電流が常時、流れることがないので、消費電流及び損失の低減が可能である。
更に、正側及び負側高電圧発生部の回路構成は実質的に同一であり、これらの高電圧発生部の出力端子間の電位差を従来技術よりも小さくして放電の恐れを少なくすると共に、正負の出力電圧のバランスがとれた高電圧発生回路を実現することができる。
According to the present invention, it is possible to reduce the cost by eliminating the high withstand voltage resistance on the output side, and since the current does not always flow to the negative side high voltage generation unit in terms of operation principle, Current and loss can be reduced.
Furthermore, the circuit configurations of the positive and negative high voltage generators are substantially the same, and the potential difference between the output terminals of these high voltage generators is made smaller than in the prior art to reduce the risk of discharge, A high voltage generation circuit in which positive and negative output voltages are balanced can be realized.

以下、図に沿って本発明の実施形態を説明する。
図1は、請求項1に係る発明の実施形態を示す回路構成図であり、以下では、主として図3との相違点を中心に説明する。
図1において、制御回路1から出力される正側の制御信号は、主電源(図示せず)によりオンするスイッチ3Pを介して正側の発振回路2Pに入力され、また、制御回路1から出力される負側の制御信号は、同じくスイッチ3Nを介して負側の発振回路2Nに入力されている。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit configuration diagram showing an embodiment of the invention according to claim 1, and the following description will mainly focus on differences from FIG.
In FIG. 1, a positive control signal output from the control circuit 1 is input to the positive oscillation circuit 2P via a switch 3P that is turned on by a main power supply (not shown), and is output from the control circuit 1. The negative control signal is input to the negative oscillation circuit 2N via the switch 3N.

正側の発振回路2Pからは高周波の交流電圧が出力され、この交流電圧は、正側高電圧発生部10P内のトランス4Pを介して第1の倍電圧整流回路9Pにより昇圧、整流され、図2(a)に示すような正電圧パルス(振幅を+Pとする)として正側端子21Pから接続点22に出力される。上記倍電圧整流回路9Pは図3の倍電圧整流回路5Pと同一の構成であり、C1〜C4はコンデンサ、D1〜D4はダイオード、ZD1〜ZD4はツェナーダイオードである。 A high-frequency AC voltage is output from the positive-side oscillation circuit 2P, and this AC voltage is boosted and rectified by the first voltage doubler rectifier circuit 9P via the transformer 4P in the positive-side high voltage generator 10P. is output from the positive side terminal 21P to the connection point 22 as 2 (a) to indicate such a positive voltage pulse (and the + P 1 amplitude). The voltage doubler rectifier circuit 9P has the same configuration as the voltage doubler rectifier circuit 5P in FIG. 3, C1 to C4 are capacitors, D1 to D4 are diodes, and ZD1 to ZD4 are zener diodes.

倍電圧整流回路9Pの構成を詳述すると、トランス4Pの二次巻線の両端(交流電圧の入力端子間)にコンデンサC1、ツェナーダイオードZD1、ダイオードD1が直列に接続され、ツェナーダイオードZD1とダイオードD1との直列回路の両端にコンデンサC2、ツェナーダイオードZD2、ダイオードD2が直列に接続され、以下同様にコンデンサC3、ツェナーダイオードZD3、ダイオードD3の直列回路と、コンデンサC4、ツェナーダイオードZD4、ダイオードD4の直列回路とが接続されている。そして、最終段のコンデンサC4とツェナーダイオードZD4との接続点(ツェナーダイオードZD4のアノード)が正側端子21Pに接続されている。なお、ツェナーダイオードZD1とダイオードD1、同じくZD2とD2、ZD3とD3、ZD4とD4とは、それぞれ逆方向に接続されている。   The configuration of the voltage doubler rectifier circuit 9P will be described in detail. A capacitor C1, a Zener diode ZD1, and a diode D1 are connected in series to both ends (between AC voltage input terminals) of the secondary winding of the transformer 4P. The Zener diode ZD1 and the diode A capacitor C2, a Zener diode ZD2, and a diode D2 are connected in series to both ends of the series circuit with D1, and the series circuit of the capacitor C3, the Zener diode ZD3, and the diode D3, and the capacitor C4, the Zener diode ZD4, and the diode D4 are similarly connected. A series circuit is connected. A connection point (the anode of the Zener diode ZD4) between the final stage capacitor C4 and the Zener diode ZD4 is connected to the positive terminal 21P. Zener diode ZD1 and diode D1, ZD2 and D2, ZD3 and D3, and ZD4 and D4 are connected in opposite directions, respectively.

また、負側の発振回路2Nからも高周波の交流電圧が出力され、この交流電圧は、負側高電圧発生部10N内のトランス4Nを介して第2の倍電圧整流回路9Nにより昇圧、整流され、図2(b)に示すような負電圧パルス(振幅を−Nとし、|P|=|N|)とする)として負側端子21Nから接続点22に出力される。
倍電圧整流回路9Nは、ツェナーダイオード及びダイオードの極性以外は正側の倍電圧整流回路9Pと実質的に同一の構成であって、C5〜C8はコンデンサ、D5〜D8はダイオード、ZD5〜ZD8はツェナーダイオードを示し、最終段のコンデンサC8とツェナーダイオードZD8との接続点(ツェナーダイオードZD8のカソード)が負側端子21Nに接続されている。
この倍電圧整流回路9Nでは、ツェナーダイオードZD5とダイオードD5、同じくZD6とD6、ZD7とD7、ZD8とD8とが、それぞれ逆方向に接続されている。
A high-frequency AC voltage is also output from the negative-side oscillation circuit 2N, and this AC voltage is boosted and rectified by the second voltage doubler rectifier circuit 9N via the transformer 4N in the negative-side high voltage generator 10N. 2B, a negative voltage pulse (with an amplitude of −N 1 and | P 1 | = | N 1 |) is output from the negative terminal 21N to the connection point 22 as shown in FIG.
The voltage doubler rectifier circuit 9N has substantially the same configuration as the positive voltage doubler rectifier circuit 9P except for the zener diode and the polarity of the diode, C5 to C8 are capacitors, D5 to D8 are diodes, and ZD5 to ZD8 are A Zener diode is shown, and a connection point (a cathode of the Zener diode ZD8) between the capacitor C8 and the Zener diode ZD8 in the final stage is connected to the negative terminal 21N.
In this voltage doubler rectifier circuit 9N, a Zener diode ZD5 and a diode D5, ZD6 and D6, ZD7 and D7, and ZD8 and D8 are connected in opposite directions.

図2(a)の正電圧パルスと図2(b)の負電圧パルスとは、接続点22において加算され、図2(c)に示すような交流パルス電圧が生成される。この交流パルス電圧は、電流制限抵抗8を介して出力端子23から放電電極(図示せず)に印加され、対向電極との間にコロナ放電を生じさせて放電電極の周囲の空気をイオン化し、正負イオンを発生させるものである。   The positive voltage pulse in FIG. 2A and the negative voltage pulse in FIG. 2B are added at the connection point 22 to generate an AC pulse voltage as shown in FIG. This AC pulse voltage is applied to the discharge electrode (not shown) from the output terminal 23 via the current limiting resistor 8 to cause corona discharge between the counter electrode and ionize the air around the discharge electrode, It generates positive and negative ions.

本実施形態では、負側高電圧発生部10Nの出力側に、図3のごとく高耐圧が要求される抵抗7が存在しないため、その分の部品コストを低減することができる。
また、負側高電圧発生部10Nに常時電流が流れることがないので、消費電流を減少させて損失の低減、効率の向上が可能になる。
更に、図1の正側端子21Pと負側端子21Nとの間の電位差は、最大でも|P|(=|N|)であるから、図3の従来技術に比べて両端子21P,21N間の電位差を低下させて放電のおそれを少なくすることができる。
In the present embodiment, since there is no resistor 7 that requires a high breakdown voltage as shown in FIG. 3 on the output side of the negative high voltage generator 10N, the part cost can be reduced accordingly.
In addition, since no current always flows through the negative high voltage generator 10N, it is possible to reduce current consumption and reduce loss and improve efficiency.
Further, since the potential difference between the positive terminal 21P and the negative terminal 21N in FIG. 1 is | P 1 | (= | N 1 |) at the maximum, both terminals 21P, 21P, The potential difference between 21N can be reduced to reduce the risk of discharge.

ここで、以下の表1,表2は、図1の本実施形態及び図3の従来技術について、入力電圧(制御回路1の直流電源電圧)に応じた正側高電圧発生部,負側高電圧発生部の出力電圧最大値とピーク−ピーク値、従来技術を基準としたピーク−ピーク値の比を示している。表1,表2における「周波数」は発振回路2P,2Nの出力周波数(発振周波数)であり、これらは互いに等しい。   Here, Tables 1 and 2 below show the positive side high voltage generation unit and the negative side high voltage corresponding to the input voltage (DC power supply voltage of the control circuit 1) for the present embodiment of FIG. 1 and the prior art of FIG. The output voltage maximum value and peak-to-peak value of the voltage generator, and the peak-to-peak value ratio based on the prior art are shown. “Frequency” in Tables 1 and 2 is the output frequency (oscillation frequency) of the oscillation circuits 2P and 2N, which are equal to each other.

Figure 0004338105
Figure 0004338105

Figure 0004338105
Figure 0004338105

表1,表2において、本実施形態によれば、発振周波数を変化させても正側高電圧発生部10P、負側高電圧発生部10Nの正負の出力電圧最大値はほとんど変化がなく、入力電圧の変化率ほど出力電圧には大きな変化が現れていない。
一方、従来技術は、正側高電圧発生部6Pが正電圧パルスを出力し、負側高電圧発生部6Nが負の直流バイアス電圧を出力するものであるが、発振周波数を変化させると入力電圧が同じであっても正負の出力電圧最大値にバラツキが生じており、また、主として正の出力電圧最大値が本実施形態よりも著しく低下している。更に、従来技術を基準としたピーク−ピーク値の比からも明らかなように、本実施形態では従来技術よりも大きなピーク−ピーク値を出力させることが可能になっている。
In Tables 1 and 2, according to the present embodiment, the positive and negative output voltage maximum values of the positive high-voltage generator 10P and the negative high-voltage generator 10N hardly change even when the oscillation frequency is changed. The change in the output voltage does not appear as large as the voltage change rate.
On the other hand, in the prior art, the positive high voltage generator 6P outputs a positive voltage pulse and the negative high voltage generator 6N outputs a negative DC bias voltage. When the oscillation frequency is changed, the input voltage However, the maximum positive and negative output voltage values vary, and the maximum positive output voltage value is significantly lower than that of the present embodiment. Furthermore, as is clear from the peak-to-peak value ratio based on the prior art, in the present embodiment, it is possible to output a larger peak-peak value than the prior art.

また、表3,表4は、図1の本実施形態及び図3の従来技術について、入力電圧(制御回路1の直流電源電圧)に応じた正側高電圧発生部,負側高電圧発生部の出力電流及び平均電流、従来技術を基準とした平均電流の比を示している。表3,表4における「周波数」は、前記同様に発振回路2P,2Nの出力周波数(発振周波数)である。更に、「Pog」は正側高電圧発生部の出力電流を示し、「Neg」は負側高電圧発生部の出力電流を示している。   Tables 3 and 4 show the positive side high voltage generator and the negative side high voltage generator according to the input voltage (DC power supply voltage of the control circuit 1) for the present embodiment of FIG. 1 and the prior art of FIG. The ratio of the output current and the average current, and the average current based on the prior art is shown. “Frequency” in Tables 3 and 4 is the output frequency (oscillation frequency) of the oscillation circuits 2P and 2N as described above. Furthermore, “Pog” indicates the output current of the positive high voltage generator, and “Neg” indicates the output current of the negative high voltage generator.

Figure 0004338105
Figure 0004338105

Figure 0004338105
Figure 0004338105

表3,表4において、従来技術では負側高電圧発生部6Nに常時電流が流れているため、平均電流が大きくなり、言い換えれば、本実施形態によると消費電流が大幅に減少していることがわかる。   In Tables 3 and 4, since current always flows through the negative high voltage generator 6N in the prior art, the average current increases. In other words, according to this embodiment, the current consumption is greatly reduced. I understand.

なお、図示されていないが、請求項2に係る発明の実施形態として、第1及び第2の倍電圧整流回路9P,9N内のツェナーダイオードZD1とダイオードD1との間、同じくZD2とD2との間、ZD3とD3との間、ZD4とD4との間、ZD5とD5との間、ZD6とD6との間、ZD7とD7との間、ZD8とD8との間に、それぞれ抵抗を接続しても同等の作用効果を得ることができる。   Although not shown in the drawings, as an embodiment of the invention according to claim 2, between the Zener diode ZD1 and the diode D1 in the first and second voltage doubler rectifier circuits 9P and 9N, and similarly between ZD2 and D2 Between ZD3 and D3, between ZD4 and D4, between ZD5 and D5, between ZD6 and D6, between ZD7 and D7, and between ZD8 and D8, respectively. However, an equivalent effect can be obtained.

本発明の実施形態を示す回路構成図である。It is a circuit block diagram which shows embodiment of this invention. 図1における主要部の電圧波形を示す図である。It is a figure which shows the voltage waveform of the principal part in FIG. 従来技術を示す回路構成図である。It is a circuit block diagram which shows a prior art. 図3における主要部の電圧波形を示す図である。It is a figure which shows the voltage waveform of the principal part in FIG.

符号の説明Explanation of symbols

1:制御回路
2P,2N:発振回路
3P,3N:スイッチ
4P,4N:トランス
8:電流制限抵抗
9P,9N:倍電圧整流回路
10P,10N:高電圧発生部
21P:正側端子
21N:負側端子
22:接続点
23: 出力端子
C1〜C8:コンデンサ
D1〜D8:ダイオード
ZD1〜ZD8:ツェナーダイオード
1: Control circuit 2P, 2N: Oscillation circuit
3P, 3N: Switch 4P, 4N: Transformer 8: Current limiting resistor 9P, 9N: Voltage doubler rectifier circuit 10P, 10N: High voltage generator 21P: Positive side terminal 21N: Negative side terminal 22: Connection point 23: Output terminal C1 C8: Capacitor D1-D8: Diode ZD1-ZD8: Zener diode

Claims (2)

交流電圧が入力されて正電圧パルスを出力する第1の倍電圧整流回路を備えた正側高電圧発生部と、交流電圧が入力されて負電圧パルスを発生する第2の倍電圧整流回路を備えた負側高電圧発生部と、を有し、正側及び負側高電圧発生部の出力電圧を加算して出力する高電圧発生回路において、
第1及び第2の倍電圧整流回路は、交流電圧の入力端子間にコンデンサとツェナーダイオードとダイオードとを接続してなる直列回路を接続し、前記ツェナーダイオードとダイオードとの直列回路の両端に、コンデンサとツェナーダイオードとダイオードとを接続してなる直列回路を順次接続すると共に、各直列回路内のツェナーダイオードとダイオードとを逆方向に接続し、かつ、各直列回路内のコンデンサ同士が直接接続されないように各コンデンサを配置して構成され、
第1の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、第2の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、を直接接続して電流制限抵抗を介し出力端子に接続したことを特徴とする高電圧発生回路。
A positive high voltage generator having a first voltage doubler rectifier circuit that outputs a positive voltage pulse when an AC voltage is input, and a second voltage doubler rectifier circuit that generates a negative voltage pulse when an AC voltage is input A high-voltage generating circuit having a negative-side high-voltage generating unit, and adding and outputting the output voltages of the positive-side and negative-side high-voltage generating units,
The first and second voltage doubler rectifier circuits connect a series circuit formed by connecting a capacitor, a Zener diode, and a diode between the input terminals of the AC voltage, and at both ends of the series circuit of the Zener diode and the diode, A series circuit composed of a capacitor, a Zener diode, and a diode is connected in sequence, and the Zener diode and the diode in each series circuit are connected in the opposite direction, and the capacitors in each series circuit are not directly connected to each other. Is configured by placing each capacitor as
A connection point between the Zener diode and the capacitor in the series circuit at the final stage in the first voltage doubler rectifier circuit, and a connection point between the Zener diode and the capacitor in the series circuit at the final stage in the second voltage doubler rectifier circuit. Are connected directly to the output terminal via a current limiting resistor.
交流電圧が入力されて正電圧パルスを出力する第1の倍電圧整流回路を備えた正側高電圧発生部と、交流電圧が入力されて負電圧パルスを発生する第2の倍電圧整流回路を備えた負側高電圧発生部と、を有し、正側及び負側高電圧発生部の出力電圧を加算して出力する高電圧発生回路において、
第1及び第2の倍電圧整流回路は、交流電圧の入力端子間にコンデンサとツェナーダイオードと抵抗とダイオードとを接続してなる直列回路を接続し、前記ツェナーダイオードと抵抗とダイオードとの直列回路の両端に、コンデンサとツェナーダイオードと抵抗とダイオードとを接続してなる直列回路を順次接続すると共に、各直列回路内のツェナーダイオードとダイオードとを逆方向に接続し、かつ、各直列回路内のコンデンサ同士が直接接続されないように各コンデンサを配置して構成され、
第1の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、第2の倍電圧整流回路における最終段の前記直列回路内のツェナーダイオードとコンデンサとの接続点と、を直接接続して電流制限抵抗を介し出力端子に接続したことを特徴とする高電圧発生回路。
A positive high voltage generator having a first voltage doubler rectifier circuit that outputs a positive voltage pulse when an AC voltage is input, and a second voltage doubler rectifier circuit that generates a negative voltage pulse when an AC voltage is input A high-voltage generating circuit having a negative-side high-voltage generating unit, and adding and outputting the output voltages of the positive-side and negative-side high-voltage generating units,
In the first and second voltage doubler rectifier circuits, a series circuit formed by connecting a capacitor, a Zener diode, a resistor, and a diode is connected between the input terminals of the AC voltage, and the series circuit of the Zener diode, the resistor, and the diode is connected. A series circuit formed by connecting a capacitor, a Zener diode, a resistor, and a diode is sequentially connected to both ends of the capacitor, and the Zener diode and the diode in each series circuit are connected in the opposite direction, and Each capacitor is arranged so that the capacitors are not directly connected,
A connection point between the Zener diode and the capacitor in the series circuit at the final stage in the first voltage doubler rectifier circuit, and a connection point between the Zener diode and the capacitor in the series circuit at the final stage in the second voltage doubler rectifier circuit. Are connected directly to the output terminal via a current limiting resistor.
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