JP4337482B2 - Inverter test equipment - Google Patents

Description

  The present invention relates to an inverter test apparatus for testing an inverter under test mainly by a pseudo load that simulates a motor with an inverter for pseudo load, and particularly protects the inverter under test against an overvoltage generated by a pseudo load. The present invention relates to an inverter test apparatus provided with a circuit.

Conventionally, in an inverter test using a motor as a load, the inverter is replaced with a pseudo load consisting of a combination of L (inductor), R (resistor), and a switch group, which has a limited control freedom and tends to be complicated in configuration. Is used as a pseudo load, and the amplitude and phase of the output voltage are controlled to create a state in which the motor, which is the actual load, is simulated, and an inverter at any load under any operating condition A system capable of performing the above test has been developed (see, for example, Patent Document 1 and Patent Document 2).
JP 2003-153546 A JP 2003-153547 A

  However, the following problems may occur in the inverter test apparatus as shown in FIG. For example, the inverter under test 1 turns off all the switching elements Tr1 to Tr6 or stops the chopper circuit 6 that adjusts the DC voltage when an abnormality such as an overcurrent flowing or a temperature rise is detected during the test. Or stop abnormally. In this case, when the pseudo load 21 simulating the motor is stopped later than the inverter 1 to be tested, the output voltage of the pseudo load 21 passes through feedback diodes D1 to D6 connected between the emitters and collectors of the switching elements Tr1 to Tr6. The capacitor C1 on the DC side of the inverter under test 1 is charged. Normally, the pseudo load inverter 2 in the pseudo load 21 is designed so that a voltage higher than the maximum output voltage of the inverter under test 1 can be output for the convenience of testing. There is a possibility that a voltage higher than the withstand voltage is applied to C1 and its peripheral circuits (for example, a discharge circuit and a voltage detection circuit).

  Even in such a state, if the chopper circuit 6 is in an operating state, the DC input voltage E2 of the inverter under test 1 is lowered (for example, a regenerative operation), so there is no problem. However, generally, when the inverter under test 1 is abnormally stopped, the operation of the chopper circuit 6 is stopped. Therefore, the electric energy input from the pseudo load 21 is not absorbed by the chopper circuit 6, and thus the DC input voltage E2 is lowered. do not do. Therefore, there is a problem that the DC input capacitor C1 is charged with a voltage higher than the withstand voltage, causing the DC input capacitor C1 and its peripheral circuits to deteriorate or withstand voltage.

  Further, as a device for solving the above-mentioned problem, a device that directly takes out the DC input voltage E2 of the inverter under test 1 and inputs it to the test circuit can be considered, but the inverter under test 1 may be a facility on the customer side. There is also a problem that it may be difficult to extract a test signal.

The present invention has been made in view of the above circumstances, and its purpose is to occur when the inverter under test abnormally stops and the DC input capacitor and the DC input capacitor by applying a voltage higher than the withstand voltage to the peripheral circuit, and An object of the present invention is to provide an inverter test apparatus capable of preventing the peripheral circuit from being deteriorated or broken down.
Another object of the present invention is to provide an inverter test apparatus that can perform a test without taking out a test signal from an inverter under test on the customer side.

In order to achieve the above object, the present invention proposes the following means.
The invention according to claim 1 is an inverter test apparatus, in which a second inverter serving as a pseudo load for simulating the operation of the motor with respect to the first inverter to be tested, and the actual load of the first inverter In an inverter testing apparatus comprising control means for simulating the operation of a motor by generating a control signal for controlling the second inverter based on an operating condition and a motor characteristic set for the motor An overvoltage protection circuit is provided that detects the output voltage of one inverter and stops the operation of the second inverter according to the output voltage.
According to this invention, the overvoltage protection circuit in the inverter test apparatus detects the output voltage of the inverter under test and stops the operation of the inverter constituting the pseudo load according to the output voltage. If a high voltage is applied to the test inverter, the problem can be avoided.

The invention according to claim 2 is the inverter testing apparatus according to claim 1, wherein the overvoltage protection circuit includes phase voltage maximum value detecting means for detecting a peak value of the phase voltage of the output of the first inverter. And amplifying means for amplifying the output signal of the phase voltage maximum value detecting means, and comparing means for comparing the output signal of the amplifying means with a predetermined potential and outputting the result to the control means. Features.
According to the present invention, the circuit configuration is such that the maximum value of the phase voltage of the output of the inverter under test is held in the capacitor, and the pseudo load can be controlled based on the result of comparing the voltage with the predetermined voltage by the comparator. .

The invention according to claim 3 is the inverter test apparatus according to claim 2, wherein the amplifying means is an insulation amplifier that separates input and output grounds and transmits a signal.
According to the present invention, since the inverter test apparatus transmits the signal by separating the input / output ground by the insulating amplifier, it is possible to avoid the mutual interference between the main circuit system and the control system.

The invention according to claim 4 is the inverter testing apparatus according to claim 1, wherein the overvoltage protection circuit detects a line voltage of an output of the first inverter, and the line It comprises an amplifying means for amplifying the output signal of the inter-voltage detection means, and a comparing means for comparing the output signal of the amplifying means with a predetermined potential and outputting the result to the control means.
According to the present invention, the circuit configuration is such that the maximum value of the line voltage of the output of the inverter under test is held in the capacitor, and the pseudo load can be controlled based on the result of comparing the voltage with the predetermined voltage by the comparator. Become.

The invention according to claim 5 is the inverter testing apparatus according to claim 4, wherein the amplifying means is an isolation amplifier that separates input and output grounds and transmits signals.
According to the present invention, since the inverter test apparatus transmits the signal by separating the input / output ground by the insulating amplifier, it is possible to avoid the mutual interference between the main circuit system and the control system.

  According to the present invention, it is possible to prevent deterioration or breakdown of the DC input capacitor and its peripheral circuit due to the application of a voltage exceeding the breakdown voltage to the DC input capacitor and its peripheral circuit, which can occur when the inverter under test abnormally stops. There is an effect that can be done.

A first embodiment of the present invention will be described below with reference to the drawings.
FIG. 2 is a circuit diagram showing an inverter test apparatus according to an embodiment of the present invention. In this figure, the inverter test apparatus applies an inverter under test 1 (first inverter) (hereinafter referred to as inverter 1) and a pseudo load inverter 2 (second inverter) (hereinafter referred to as inverter 2). A pseudo load 21 simulating a motor, a DC power supply 5 (power supply means), a chopper circuit 6 (voltage adjustment means), and an overvoltage protection circuit 31 connected to the AC output terminal of the inverter 1. The inverter 1 outputs a rectangular wave voltage PWM1 PWM-modulated from the AC output terminal. The DC power supply 5 supplies the DC voltage E1 to the chopper circuit 6 for adjusting the test voltage, and the chopper circuit 6 adjusts the input DC voltage and outputs it to the inverter 1 as the DC voltage E2. The DC power supply 5 also supplies a DC voltage E1 to the inverter 2.

  The pseudo load 21 includes an inverter 2, a filter 7, a transformer 8, a filter 9, a current transformer 10, and a motor simulation operation control unit 11 (control means). Simulate the motor. The transformer 8 obtains a voltage necessary for simulating the motor with respect to the inverter 1 based on the turn ratio, and at the same time, prevents a current due to a neutral potential difference between the inverter 1 and the inverter 2. The transformer 8 is unnecessary if the DC voltage E1 and the DC voltage E2 are insulated from each other and have a voltage relationship necessary for control.

Next, the principle that the pseudo load 21 simulates an actual motor will be described.
The rectangular wave voltage PWM1 output from the inverter 1 is converted into a sine wave by the filter 7 including the inductance L and applied to the primary side of the transformer 8. On the other hand, the inverter 2 outputs a PWM-modulated rectangular wave voltage PWM2 from the AC output terminal, and the rectangular wave voltage PWM2 is a sine wave of a fundamental wave through a filter 9 including an inductance l, a capacitor c, and a resistor r. It is taken out and added to the secondary side of the transformer 8. As a result, the inverter 1 and the inverter 2 are connected via the transformer 8, and by controlling the amplitude and phase of the output voltage of the inverter 2, the impedance viewed from the inverter 1 changes, and the motor that is the actual load Can be set in a simulated driving state. Thereby, the test of the inverter 1 in an arbitrary load can be performed under an arbitrary operation condition.

  The motor simulation operation control unit 11 obtains the currents iu and iw detected by the current transformer 10 for the U phase and W phase of the rectangular wave voltage PWM1 output from the inverter 1 and the sine obtained from the rectangular wave voltage PWM1 through the filter 7. The operating conditions and motor constants of the motor as a load are input by the wave voltages Vu ′ and Vw ′ and the operator, and the inverter 2 is controlled based on these constants.

  Further, the motor simulation operation control unit 11 is provided with an angle sensor simulation control unit 12 (control means). The angle sensor simulation control unit 12 receives the sensor driving signal Se from the inverter 1 and outputs the simulated angle sensor signal Sθ to the inverter 1. The inverter 1 controls the voltage and current based on the simulated angle sensor signal Sθ. Note that switching circuits of IGBTs (Insulated Gate Bipolar Transistors) Tr1 to Tr6 of switching elements in the inverter 1 are included in the inverter 1.

  FIG. 1 is a block diagram showing a configuration of the overvoltage protection circuit 31a. Insulation amplifier InsOP (amplifying means) is an amplifier that separates the ground between input and output and transmits signals in order to prevent mutual interference between the main circuit system and the control system in the field of power electronics. In the present embodiment, the insulation amplifier InsOP performs signal transmission by separating the grounds of the inverters 1 and 2 and the ground of the overvoltage protection circuit 31a. Specifically, the ground on the input side of the insulation amplifier InsOP is connected to the grounds of the inverter 1 and the inverter 2, and the ground on the output side of the insulation amplifier InsOP is connected to the ground of the overvoltage protection circuit 31a. When the DC power sources of the inverter 1 and the inverter 2 are separated, measurement is performed by connecting the negative side of the DC power source 5 of the inverter 1 to the ground on the input side of the insulation amplifier InsOP.

  The overvoltage protection circuit 31a measures the peak value of the phase voltage at the output terminal of the inverter 1, indirectly detects E2, and stops the operation of the inverter 2 when the value is equal to or greater than a certain value. In the present embodiment, since the peak value of the phase voltage at the AC output terminal of the inverter 1 is equal to the DC input voltage E2 of the inverter 1, the direct current of the inverter 1 is indirectly determined by the phase voltage at the AC output terminal of the inverter 1. Observe the input voltage E2.

  Each phase (U, V, W) voltage Vu, Vv, Vw of the inverter 1 is connected to the anode side of the diodes D311 to D313 (phase voltage maximum value detecting means) from the input terminals Ipu, Ipv, Ipw, respectively. The cathodes of the diodes D311 to D313 are connected in common and are connected to one input terminal of the insulation amplifier InsOP via the resistor R311. The other input terminal of the insulation amplifier InsOP is connected to one input terminal of the insulation amplifier InsOP via a resistor R312 (phase voltage maximum value detection means) and a capacitor C311 (phase voltage maximum value detection means) connected in parallel. And connected to the ground input terminal Gndi. The ground input terminal Gndi is connected to the negative side of the DC power source 5, and the ground potential Gdc of the ground input terminal Gndi is made equal to the negative side potential of the DC power source 5.

  The output terminal of the insulation amplifier InsOP is connected to the non-inverting input terminal of the comparator CP (comparison means) via the resistor R313 and grounded to the ground potential Gpc of the overvoltage protection circuit 31 via the capacitor C313. The positive side of the reference voltage source E3 is connected to the inverting input terminal of the comparator CP. The negative side of the reference voltage source E3 is grounded to the ground potential Gpc of the overvoltage protection circuit 31a. The output terminal OUT of the comparator CP is connected to the motor simulation operation control unit 11.

Next, the operation of the first embodiment will be described with reference to FIG.
Each part of the inverter test equipment is powered on and the test starts. The DC power supply 5 supplies a DC voltage E1 to the chopper circuit 6. The chopper circuit 6 adjusts the DC voltage E1 to control the operation state of the inverter 1 and supplies the DC voltage E2 to the inverter 1. The inverter 1 outputs a sensor driving signal Se to the angle sensor simulation control unit 12, and the angle sensor simulation control unit 12 outputs a simulation angle sensor signal Sθ to the inverter 1. The inverter 1 controls the voltage and current based on the simulated angle sensor signal Sθ, and supplies the rectangular wave voltage PWM 1 to the transformer 8 via the filter 7.

  On the other hand, in the pseudo load 21, the inverter 2 is supplied with the DC voltage E1 from the DC power source 5. The motor simulation operation control unit 11 receives a motor operation condition, motor constants, voltages Vu ′ and Vw ′, currents iu and iw, calculates a gate signal for controlling the inverter 2, and controls the inverter 2. The inverter 2 is controlled so as to simulate the motor by the above constant, outputs a rectangular wave voltage PWM 2, and supplies it to the transformer 8 via the filter 9. With the above operation, an operation for simulating an actual motor is performed.

Next, the operation of the overvoltage protection circuit 31a in this embodiment will be described with reference to FIG. 1 and FIG.
The phase voltages Vu, Vv, Vw output from the inverter 1 are input to a circuit including diodes D311 to D313, resistors R311, R312 and a capacitor C311. The peak values of the phase voltages Vu, Vv, Vw are held in the capacitor C311. At this time, R311, R312, R311, R312, R311, R312, R311, R312, R311, R312, R311, R312, D311, D312, R312 C311 is determined. Therefore, C311 is quickly charged when the peak values of the phase voltages Vu, Vv, and Vw are updated to higher values, while the peak values of the phase voltages Vu, Vv, and Vw are less than the voltage accumulated in the C311. Since the voltage is slowly discharged, the currently accumulated voltage value can be held. Information on the peak value of this voltage is amplified by the insulation amplifier InsOP. The output of the insulation amplifier InsOP is input to the non-inverting input terminal of the comparator CP through a low-pass filter including a resistor R313 and a capacitor C313. On the other hand, the reference voltage E3 is input to the inverting input terminal of the comparator CP, and is compared with the input voltage at the non-inverting input terminal of the comparator CP described above.

  Here, when the inverter 1 is stopped due to the occurrence of some abnormality (all the IGBTs Tr1 to Tr6 are turned off), the output voltage of the inverter 2 is supplied to the output side of the inverter 1 through the transformer 8 and the filter 7, thereby 1 phase voltages Vu, Vv, Vw on the output side rise. When the phase voltage Vu, Vv, Vw on the output side of the inverter 1 increases, the voltage across the capacitor C311 of the overvoltage protection circuit 31 increases, and the output of the insulation amplifier InsOP increases. When the output of the insulation amplifier InsOP exceeds the reference voltage E3, the output of the comparator CP is inverted, and this inverted output is output to the motor simulation operation control unit 11. The motor simulation operation control unit 11 receives this inverted output and stops the inverter 2.

  According to the above embodiment, the inverter test apparatus includes the circuit for observing the output voltage of the inverter under test and stopping the operation of the pseudo load inverter when the value is above a certain value. It is possible to prevent deterioration or breakdown due to voltage application exceeding the withstand voltage to the DC input capacitor of the inverter and its peripheral circuits.

Next explained is the second embodiment of the invention.
The block configuration of the inverter test apparatus according to the second embodiment is similar to that of FIG. 2, but the overvoltage protection circuit 31b and the peripheral configuration and operation are different from those of the overvoltage protection circuit 31a and the peripheral in the first embodiment. FIG. 3 is a block diagram showing a configuration of the overvoltage protection circuit 31b according to the second embodiment. FIG. 4 is a block diagram showing the configuration of the inverter test apparatus of the same embodiment.
The configuration of this embodiment will be described below with reference to the drawings.

  Compared to the overvoltage protection circuit 31a according to the first embodiment, the overvoltage protection circuit 31b has the same insulation amplifier InsOP, comparator CP, resistor R313, capacitor C313, and reference voltage source E3, but the input terminals Ipu and Ipv. , Ipw and the insulation amplifier InsOP are different in circuit configuration. 3 and 4 differ from FIGS. 1 and 2 in that the input terminal Gndi is unnecessary.

  The phase (U, V, W) voltages Vu, Vv, Vw of the inverter 1 are respectively input from the input terminals Ipu, Ipv, Ipw, the anode of the diode D321 and the cathode of the diode D322, the anode of the diode D323, and the diode D324. It is inputted to each connection point between the anode of the diode D325 and the cathode of the diode D326 with the cathode. (D321 to D326) Connected to the anode side of the line voltage detecting means. The cathodes of the diodes D321, D323, and D325 are connected in common and are connected to one input terminal of the insulation amplifier InsOP. The other input terminal of the insulation amplifier InsOP is connected to one input terminal of the insulation amplifier InsOP via a resistor R321 (line voltage detection means) and a capacitor C321 (line voltage detection means) connected in parallel. The diodes D322, D324, and D326 are commonly connected to the anode side. Since the configuration from the output terminal of the insulation amplifier InsOP to the output terminal OUT of the comparator CP is the same as that shown in FIG.

Next, the operation of the overvoltage protection circuit 31b of the second embodiment will be described with reference to FIG.
The phase voltages Vu, Vv, Vw output from the inverter 1 are input to a circuit including diodes D321 to D326, a resistor R321, and a capacitor C321, and are rectified. The rectified voltage is amplified by an insulation amplifier InsOP. The output of the insulation amplifier InsOP is input to the non-inverting input terminal of the comparator CP through a low-pass filter including a resistor R313 and a capacitor C313. On the other hand, the reference voltage E3 is input to the inverting input terminal of the comparator CP, and is compared with the input voltage at the non-inverting input terminal of the comparator CP described above.

  Here, when some abnormality occurs, the inverter 1 is stopped (all the IGBTs Tr1 to Tr6 are turned off) and the chopper circuit 6 is also stopped, and the output voltage of the inverter 2 is output from the inverter 1 via the transformer 8 and the filter 7. Thus, phase voltages Vu, Vv, and Vw are applied to the output side of the inverter 1. When phase voltages Vu, Vv, and Vw are applied to the output side of the inverter 1, feedback diodes D1 to D6 of the inverter 1 form a rectifier circuit, and the inverter 1 does not perform PWM control. Is equal to the DC voltage E2 of the inverter 1. The line voltage is output to the insulation amplifier InsOP. When the output of the insulation amplifier InsOP exceeds the reference voltage E3, the output of the comparator CP is inverted, and this inverted output is output to the motor simulation operation control unit 11. The motor simulation operation control unit 11 receives this inverted output and stops the inverter 2.

According to the above embodiment, the inverter test apparatus rectifies the three-phase output voltage of the inverter 1 under test, and when the value is above a certain value, the circuit configuration is such that the operation of the pseudo load inverter is stopped. The line connected from the inverter under test 1 to the overvoltage protection circuit 31b is only for the three-phase output. Therefore, the negative side of the DC power source 5 of the inverter under test 1 and the ground on the input side of the insulation amplifier InsOP in the overvoltage protection circuit 31b are not connected, but compared with a method of observing the peak value of the output voltage of the inverter under test. Thus, the number of connection points from the overvoltage protection circuit 31b to the inverter under test 1 can be reduced to prevent deterioration or breakdown due to voltage application to the DC input capacitor of the inverter under test 1 and its peripheral circuits. it can.
In particular, when the DC power source of the inverter under test 1 and the DC power source of the pseudo load inverter 2 are isolated, it is not necessary to connect the negative side of the DC power source of the inverter under test 1 to the pseudo load device. Thus, the present invention is effective.

  In the first embodiment and the second embodiment, the output signal of the insulation amplifier InsOP is input to the comparator CP in the overvoltage protection circuit 31 and processed in hardware. An output signal may be input to the CPU via the A / D converter, and when the value is equal to or greater than a certain value, the inverter 2 may be stopped by an instruction from the CPU.

  As mentioned above, although embodiment of this invention was explained in full detail with reference to drawings, the concrete structure is not restricted to this embodiment, The design change in the range which does not deviate from the summary of this invention is also included.

It is a circuit diagram which shows the structure of the overvoltage protection circuit 31a in the structure of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the inverter test apparatus of the same embodiment. It is a circuit diagram which shows the structure of the overvoltage protection circuit 31b in the structure of the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the inverter test apparatus of the same embodiment.

Explanation of symbols

1 Inverter under test (first inverter)
2 Pseudo load inverter (second inverter)
5 DC power supply (power supply means)
6 Chopper circuit (voltage adjustment means)
7, 9 Filter 8 Transformer 10 Current transformer 11 Motor simulation operation control unit (control means)
12 Angle sensor simulation controller (control means)
21 Pseudo load 31a, 31b Overvoltage protection circuit

Claims (5)

A second inverter serving as a pseudo load that simulates the operation of the motor with respect to the first inverter under test;
Control means for simulating the operation of the motor by generating a control signal for controlling the second inverter based on the operating conditions and motor characteristics set for the motor that is the actual load of the first inverter;
In an inverter testing apparatus comprising:
An inverter test apparatus comprising: an overvoltage protection circuit that detects an output voltage of the first inverter and stops the operation of the second inverter according to the output voltage. Phase voltage maximum value detecting means for detecting the peak value of the phase voltage of the output of the first inverter, the overvoltage protection circuit;
Amplifying means for amplifying the output signal of the phase voltage maximum value detecting means;
Comparing means for comparing the output signal of the amplifying means with a predetermined potential and outputting the result to the control means;
The inverter test apparatus according to claim 1, comprising:   3. The inverter testing apparatus according to claim 2, wherein the amplifying means is an insulation amplifier that separates input and output grounds and transmits signals. The overvoltage protection circuit detects a line voltage of the output of the first inverter;
Amplifying means for amplifying the output signal of the line voltage detecting means;
Comparing means for comparing the output signal of the amplifying means with a predetermined potential and outputting the result to the control means;
The inverter test apparatus according to claim 1, comprising: The inverter test apparatus according to claim 4, wherein the amplifying means is an insulation amplifier that separates input and output grounds and transmits a signal.

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