JP4336678B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to image compression / decompression.

As a technique studied by the present inventor, for example, the following technique is conceivable in MPEG (Moving Picture Experts Group) image compression / decompression.
In moving image compression standards such as ISO / IEC14496-2 (MPEG4), ISO / IEC13818-2 (MPEG2), and ISO / IEC11172-2 (MPEG1), motion vectors are detected for each block by dividing the digitized image into blocks. Discrete cosine transform (DCT), quantization, and AC / DC prediction are performed, and Huffman coding is performed to compress the image data.
Further, the decompression process of the compressed data is realized by generating a compensation image from a procedure reverse to the above-described compression, that is, Huffman decoding, AC / DC prediction, inverse quantization, inverse DCT, and motion vector information.

By the way, as a result of the study of the image compression / decompression technique as described above, the following has been clarified.
In the case of MPEG compressed stream data, Huffman-encoded variable length bit string data must be handled. At the time of image decompression, it is necessary to display / acquire variable-length bit string data from the memory storing the compressed image data, and at the time of image compression, a process of writing the variable-length bit string data to the memory is necessary. When these processes are performed by software, the bit pointer is managed in fixed-length bit data at the time of memory read / write, memory access while updating the offset value to the byte boundary, display / acquisition / write of variable-length bit string data Need to do. Further, it is necessary to mask the upper bits that have not been acquired / written on the data bus of the processor.
If the above-described processing is performed by a general-purpose processor, about 10 to 20 cycles are required to acquire and write one word of variable-length bit string data, and these processing is performed for each word, so that the system performance is deteriorated.
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of performing high-speed processing in variable-length bit string data processing such as image compression / decompression.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
That is, in the semiconductor device according to the present invention, a buffer and a control circuit for variable length bit string data operation are provided between the compressed data storage memory and the processor, and a display / acquisition / write command for variable length bit string data is provided to the processor. Is.
The buffer for variable length bit string data manipulation preferably has a bit capacity twice as large as the bit width of the compressed data storage memory.
Further, the processor has the following instructions for manipulating the variable length bit string data as display / acquisition / write instructions of the variable length bit string data.
(1) Variable length bit string data acquisition command (image decompression command)
(A) Designated bit number display instruction (no bit pointer update)
(B) Specified bit number acquisition instruction (with bit pointer update)
(C) Bit number acquisition instruction to byte boundary (d) Designated bit number bit pointer update instruction (e) Designated bit number display instruction from byte boundary (2) Variable length bit string data write instruction (image compression instruction)
(A) Specified number of bits write instruction (b) “0” or “1” write instruction to byte boundary (c) Bit number acquisition instruction to byte boundary By executing the above instructions, variable length bit string data can be manipulated. This can be done in one cycle.
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) Since variable length bit string data processing necessary for image compression / decompression can be realized in one cycle, system performance can be improved.
(2) A small-scale, low-frequency operation processor configuration enables image processing such as moving picture compression / decompression represented by MPEG to be performed in real time. With a semiconductor device that can be mounted on a home appliance, it is possible to realize an image processing function with a higher pixel density than in the past.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram showing the variable length bit string data acquisition operation in the semiconductor device according to the embodiment of the present invention.
FIG. 3 is an explanatory diagram showing a write operation of variable-length bit string data in the semiconductor device according to the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that in all the drawings for explaining the embodiments, the same members are denoted by the same reference numerals, and the repeated explanation thereof is omitted.
First, an example of the configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. In the following, although not limited to this, a case of a 32-bit bus configuration will be described as an example.
The semiconductor device of the present embodiment is, for example, an MPEG image compression / decompression system, and includes a compressed data storage memory 10, a processor 20, a variable length bit string data operation buffer 30, a control circuit 40, a mask circuit 50, and the like. It is composed of The processor 20 includes an arithmetic unit 21, a register file 22, a control unit 23, and the like.
The compressed data storage memory 10 is connected to an image compressed data stream bus 60 and is connected to the buffer 30 via a 32-bit bus. The buffer 30 is connected to the mask circuit 50 via a 32-bit bus, and is connected to the control circuit 40 via a signal line. The control circuit 40 is connected to the control unit 23 in the processor 20 via a dedicated instruction bus 70. The mask circuit 50 is connected to the register file 22 in the processor 20 via a 32-bit variable length data bus 80.
The compressed data storage memory 10 is a memory having an n-bit width (n is a natural number), and stores MPEG image compressed data and the like.
The processor 20 is a processing device such as a DSP (Digital Signal Processor), and executes processing such as MPEG image compression / decompression Huffman encoding / decoding.
The computing unit 21 in the processor 20 is a computing unit such as an adder or ALU. Further, the register file 22 is composed of, for example, eight 32-bit wide registers, and the arithmetic unit 21 uses them for arithmetic processing. The control unit 23 includes a microprogram, a program decoder, a program control circuit, and the like, and executes various instructions. In addition, a command for variable length bit string data operation is transmitted to the control circuit 40 via the dedicated command bus 70.
The buffer 30 is a buffer for manipulating variable-length bit string data, and is composed of, for example, one register having a bit capacity twice as large as the bit width n of the compressed data storage memory 10.
The control circuit 40 performs control of writing / reading of the compressed data storage memory 10, operation of variable length bit string data in the buffer 30, mask processing in the mask circuit 50, etc., according to instructions from the control unit 23 in the processor 20. Circuit.
The mask circuit 50 is a circuit that performs mask processing of variable-length bit string data. For example, the mask circuit 50 performs processing of embedding “0” data in a portion other than the designated bit for variable-length bit string data.
Further, the processor 20 has the following instructions for manipulating the variable-length bit string data as display / acquisition / write instructions for the variable-length bit string data.
(1) Variable length bit string data acquisition command (image decompression command)
(A) Designated bit number display instruction (no bit pointer update)
(B) Specified bit number acquisition instruction (with bit pointer update)
(C) Bit number acquisition instruction to byte boundary (d) Designated bit number bit pointer update instruction (e) Designated bit number display instruction from byte boundary (2) Variable length bit string data write instruction (image compression instruction)
(A) Designated bit number write instruction (b) “0” or “1” write instruction up to byte boundary (c) Bit number acquisition instruction up to byte boundary Next, referring to FIG. 2, the variable in the semiconductor device of the present embodiment The operation when acquiring long bit string data will be described. FIG. 2 is an explanatory diagram showing the variable length bit string data acquisition operation in the case of a 32-bit bus configuration (the bit width n of the compressed data storage memory 10 is 32 bits).
First, when data exists in the compressed data storage memory 10, the control circuit 40 reads 32-bit data from the compressed data storage memory 10 and writes it into the upper bits (bit 63 to bit 32) of the buffer 30. Next, the next 32-bit data is read from the compressed data storage memory 10 and written into the lower bits (bit 31 to bit 0) of the buffer 30.
In accordance with a variable length bit string data acquisition command from the control unit 23 in the processor 20, the control circuit 40 outputs the data in the buffer 30 to the register file 22 in the processor 20 via the variable length data bus 80. At this time, the mask circuit 50 sequentially performs mask processing on the variable-length bit string data and outputs it to the register file 22 as 32-bit data.
When the remaining amount of data in the buffer 30 becomes 32 bits or less, the control circuit 40 shifts the data of the lower bits (bit 31 to bit 0) of the buffer 30 to the upper bits (bit 63 to bit 32) by 32 bits, The next 32-bit data is read from the compressed data storage memory 10 and written to the lower bits (bit 31 to bit 0) of the buffer 30.
For example, when the variable length bit string data acquisition instruction from the processor 20 is an 8-bit acquisition instruction, the 8-bit data A in the buffer 30 is output to the register file 22 in the processor 20 as shown in FIG. At this time, mask processing such as embedding “0” data in the upper 24 bits is performed, and the data is output to the register file 22 as 32-bit data.
Subsequently, when the next instruction is also an 8-bit acquisition instruction, similarly, the 8-bit data B in the buffer 30 is output to the register file 22 in the processor 20. At this time, mask processing is performed and the data is output to the register file 22 as 32-bit data.
Subsequently, when the next instruction is a 32-bit acquisition instruction, the 32-bit data C in the buffer 30 is output to the register file 22 in the processor 20. At this time, since the remaining amount of data in the buffer 30 has become 32 bits or less, the data D is shifted by 32 bits, the next 32-bit data (data E) is read from the compressed data storage memory 10, and the lower order of the buffer 30 Write to bits (bit 31 to bit 0).
By repeating the above operation, variable length bit string data can be acquired in one cycle.
Next, an operation at the time of writing variable-length bit string data in the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 3 is an explanatory diagram showing a write operation of variable-length bit string data in the case of a 32-bit bus configuration (the bit width n of the compressed data storage memory 10 is 32 bits).
First, according to the variable length bit string data write command from the processor 20, the control circuit 40 sequentially writes the variable length bit string data from the register file 22 to the upper bits of the buffer 30.
When 32-bit data is stored in the buffer 30, the control circuit 40 writes the upper 32 bits (bit 63 to bit 32) data in the buffer 30 into the compressed data storage memory 10. Then, the data of the lower 32 bits (bit 31 to bit 0) in the buffer 30 is shifted by 32 bits to the upper bit side.
For example, when the variable length bit string data write command from the processor 20 is an 8-bit write command, the lower 8 bits in the 32-bit data from the register file 22 in the processor 20 are transferred to the buffer 30 as shown in FIG. Write as data A sequentially from the upper bits.
Subsequently, when the next instruction is also an 8-bit write instruction, the lower 8 bits in the 32-bit data from the register file 22 are written as data B from the next bit of data A in the buffer 30.
Subsequently, when the next instruction is a 32-bit write instruction, 32-bit data from the register file 22 is written as data C from the next bit of data B in the buffer 30.
Next, since 32-bit data is stored in the buffer 30, the upper 32 bits (bits 63 to 32) of the buffer 30 (the upper 16 bits of data A, data B, and data C) are stored as compressed data. Write to the memory 10. Then, the lower 16-bit data of data C is shifted 32 bits to the upper bit side.
By repeating the above operation, variable length bit string data can be written in one cycle.
Therefore, according to the semiconductor device of the above-described embodiment, variable length bit string data processing necessary for MPEG video compression / decompression can be realized in one cycle, so that system performance can be improved.
In addition, a small-scale, low-frequency operation processor configuration enables image processing such as moving image compression / decompression represented by MPEG to be performed in real time. It can be realized by a semiconductor device that can be mounted on a portable home appliance driven with low power consumption such as a video camera.
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, in the above-described embodiment, MPEG video compression / decompression has been described. However, the present invention is not limited to this, and can be applied to other image compression / decompression such as JPEG (Joint Photographic Experts Group).
In the above description, the case where the invention mainly made by the present inventor is applied to the image processing that is the technical field to which the present invention is applied has been described. However, the present invention is not limited to this. For example, other image processing and audio processing are performed. The present invention can be applied to all electronic devices that process variable-length bit string data such as Huffman encoding / decoding.

  As described above, the semiconductor device according to the present invention is suitable for use in electronic devices that perform compression / decompression of moving images, such as digital video cameras, video decks, and information terminals. Further, the present invention can be applied to all electronic devices that process variable length bit string data including other image processing and audio processing.

Claims (5)

A memory that is connected to an image compression data stream bus and stores compressed data transmitted to and received from the image compression data stream bus ;
And a processor,
A buffer provided between the memory and the processor;
Have a, and a control circuit for controlling the buffer by an instruction from the processor,
The processor includes an arithmetic unit, a register file that stores data used by the arithmetic unit for arithmetic processing, and a control unit that executes various instructions.
For the instruction, an operation instruction for executing processing for acquiring variable-length bit string data from the memory and writing it to the register file, and processing for acquiring variable-length bit string data stored in the register file and writing to the memory are executed. Operation instructions to be included,
In response to the operation instruction from the processor, the control circuit reads the variable-length bit string data from the memory into the buffer and writes the variable-length bit string data from the buffer to the register file, and the variable-length bit string data stored in the register file. A semiconductor device characterized in that the buffer is controlled so that each process of fetching into the buffer and writing from the buffer to the memory is executed in one cycle . The semiconductor device according to claim 1,
The semiconductor device, wherein the processor has a command for displaying, acquiring or writing the variable-length bit string data. The semiconductor device according to claim 1 or 2 ,
The semiconductor device according to claim 1, wherein the buffer has a bit capacity that is twice the bit width of the memory. The semiconductor device according to any one of claims 1 to 3 ,
A semiconductor device characterized in that a mask circuit is further provided between the processor and the buffer for performing mask processing on the variable-length bit string data . The semiconductor device according to any one of claims 1 to 4 ,
The semiconductor device , wherein the compressed data stored in the memory is compressed image data, and the variable-length bit string data is Huffman encoded data .

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