JP4314717B2 - Transmission rate discrimination method and circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention executes a transmission rate discrimination method in a digital interface for extracting and reproducing a digital interface signal transmitted at any one of a plurality of predetermined transmission rates, and the transmission rate discrimination method For the circuit.
[0002]
[Prior art]
As an example of a general system that handles a signal with a specific pattern length with a digital transmission format that can be transmitted at a plurality of predetermined transmission rates and with a wavelength limited to a maximum / minimum, There is a variable rate high density recording / reproducing apparatus for a recording medium using a baseband digital modulation system.
[0003]
As an example of a related interface system, EIAJ (Electronic Industries Association of Japan) standard CP1201 in a general-purpose digital audio interface is well known, and this format is In the field, it is called “SPDIF format” (SPDIF is an abbreviation of Sony Philips Digital audio InterFace and refers to a format defined in “EIAJ / CP1201 Digital Audio Interface Specification”).
[0004]
In a system using such a transmission format, there is no problem because the side that records or transmits the signal is the side that determines the rate of the signal itself, but the side that reproduces or receives it first sets the rate. If it cannot be discriminated first, there is a problem that PLL cannot be applied and data for each bit cannot be detected. Therefore, many methods for discriminating the rate have been known so far. However, these discrimination methods are simple ones that simply count the wavelength of the unique pattern with a high-speed clock, and for this reason, it is necessary to count the wavelength using a considerably high frequency.
[0005]
[Problems to be solved by the invention]
An object of the present invention is to determine the transmission rate using a relatively low-speed clock in a digital interface that is likely to be transmitted at a plurality of predetermined transmission rates in view of the state of the prior art. Another object of the present invention is to provide a transmission rate discriminating method and circuit that can be used.
[0006]
[Means for Solving the Problems]
According to the first aspect of the present invention, in the digital interface for reproducing the digital interface signal transmitted at any one of a plurality of predetermined transmission rates, the characteristic in the transmitted digital interface signal is unique. Measuring the pattern length with a clock of a fixed frequency, a pattern length detecting step for detecting a predetermined pattern length from each measured pattern length, and calculating the number of detections of the predetermined pattern length in a predetermined period There is provided a transmission rate determination method comprising: a detection frequency calculation step, a step of determining the calculated detection frequency, and a step of determining a transmission rate of a digital interface signal to be transmitted based on the determined detection frequency. According to this transmission rate discrimination method In a digital interface for reproducing a digital interface signal transmitted at any one of a plurality of predetermined transmission rates, the pattern length of a specific pattern in the transmitted digital interface signal is set to a fixed frequency. A first counter that measures with a first clock, a first comparison circuit that detects the predetermined pattern length by comparing the measured pattern length with a first threshold, and a predetermined pattern length detected by the first comparison circuit during a predetermined period A second counter for calculating the number of times, a second comparison circuit for comparing the calculated number of times with a second threshold, and an output for outputting a transmission rate signal of the digital interface signal to be transmitted based on the determined number of times A transmission rate discriminating circuit is provided.
[0007]
Further, according to the second feature, in the digital interface for reproducing the digital interface signal transmitted at any one of a plurality of predetermined transmission rates, the characteristic of the digital interface signal transmitted is unique. Measuring the pattern length with a clock of a fixed frequency, a pattern length detecting step for detecting a predetermined pattern length from each measured pattern length, and calculating the number of detections of the predetermined pattern length in a predetermined period Detection rate calculation step, determining the calculated detection count, and determining the transmission rate of the digital interface signal to be transmitted based on the determined pattern length or detection count Is provided.
[0008]
Further, according to another feature, in each of the transmission rate determination methods described above, an excessive or excessive pattern length that cannot occur in the digital interface format is determined for the pattern length measured in the pattern length detection step. In such a case, the operation in the detection frequency calculation step is reset, and control is performed to start the time counting for a predetermined period and the calculation operation for the detection frequency.
[0009]
[Effects of the Invention]
According to the first aspect of the present invention, in a digital interface that is likely to be transmitted at a plurality of predetermined transmission rates, first, an arbitrary arbitrary pattern in a transmitted digital format signal is targeted. The pattern length is counted by a fixed frequency clock. Here, with respect to the first count value representing the measured pattern length, a first threshold value is determined according to each transmission rate, and the first count value is determined based on the first threshold value in the pattern length detection step. Then, it is detected that the predetermined pattern length is preset as a condition for determining the transmission rate.
[0010]
Next, a second threshold value is determined according to the plurality of transmission rates for a second count value representing the number of times that a predetermined pattern length has been detected during a certain measurement period. The range to which the second count value belongs is determined based on the two threshold values. That is, the transmission rate of the received digital interface signal is determined by determining how many times the predetermined pattern length occurs during a certain period.
[0011]
According to the second feature of the present invention, in addition to the first feature, in the pattern length detection step, the pattern length is determined based on the first threshold value to roughly classify the transmission rate, and there are a plurality of specified rates. A predetermined pattern length that may belong to the transmission rate is detected. Next, for a pattern having a predetermined pattern length, the range to which the second count value belongs is determined based on the second threshold value in the detection frequency calculation step. Then, the transmission rate of the received digital interface signal is determined by comprehensively dividing the transmission rate based on the pattern length discrimination based on the first threshold and the detection frequency discrimination based on the second threshold.
[0012]
According to another feature of the present invention, a shortest pattern length and a longest pattern length that are not originally generated on the digital interface format are set for the first threshold value, and the first count value is smaller than the shortest pattern length ( If it is too small) or larger than the longest pattern length (is too large), an immediate error flag is generated, and the operation of counting the second count value with respect to the second threshold is reset, and again Control is performed to count only for a predetermined measurement period.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, a case where an SPDIF format signal is used as a digital interface signal will be described. However, this is merely an example and can be applied to various digital interface signals having a predetermined pattern. Furthermore, not only special reproduction but also the extracted reproduction signal in variable speed reproduction proportional to the system is not possible with recording / reproduction media using baseband digital modulation, etc. A reproduction circuit that automatically adapts to the speed can also be realized.
[0014]
[SPDIF format]
Before specifically describing the embodiment of the present invention, first, the frequency required for determining the existing format and its rate will be described. FIG. 1 shows an SPDIF format that is a format of the above-mentioned “EIAJ-CP1201 digital audio interface”.
[0015]
In SPDIF format data, bit data “0” and “1” per bit rate (for each time slot) shown in FIGS. 1A and 1A are as shown in FIGS. Furthermore, the same state is maintained for a period corresponding to one time slot ("bit rate corresponding pattern length") 2T, or the phase is inverted in half of the period ("minimum pattern length") T. [Hereinafter referred to as “Biφ”. ] Is transmitted with a kind of FM modulation called a method. That is, the signal pattern to be transmitted is a frequency pattern having a bit rate corresponding pattern length 2T or a minimum pattern length T that is a half thereof, and these patterns 2T, T respectively indicate data “0”, “0” in one time slot. 1 "is transmitted.
[0016]
Furthermore, on the premise of transmitting digital audio data of two stereo channels, as shown in FIG. 1 (2), 32 bits per frame for L channel (Lch) / L with respect to the sampling rate Fs of the audio signal. An R channel (Rch) is allocated as a subframe. In each subframe, pure audio data is 24 bits each, and finally, redundant data V / U / C / P bits are assigned, validity flag “V”, user data “U”, channel status (various types) Control information) "C" and parity bit "P" are added bit by bit. The “C” bit constitutes one block with 192 frames.
[0017]
Also, as shown in FIG. 1 (2), a preamble signal PA for synchronizing at the time of reproduction is added to the first 4 bits of each channel data (subframe). This preamble is a special pattern removed from the Biφ mark modulation rule described with reference to FIG. 1 (1). As shown in FIG. 1 (3), the preamble has a pattern length three times the minimum pattern length T (“ “Maximum pattern length”) 3 types of patterns “B”, “M”, and “W”, which are combinations of frequency patterns having 3T. Among these, the preamble of the “B” pattern indicates that it is a subframe which is the head of the block corresponding to the “C” bit carrying various control information in units of 192 frames, and other Lch data and Rch Preambles of “M” and “W” patterns are arranged at the heads of the data subframes, respectively.
[0018]
As described above, one frame is composed of two subframes for both channels (Lch / Rch) arranged within the sampling rate Fs. Therefore, in this format, the longest pattern is limited by the maximum pattern length 3T, the shortest pattern is limited by the minimum pattern length T, and the actual transmission rate is a × Fs = 2 (ch) × 32 (bit). For example, when Fs = 48 kHz, the frequency is 6.1 MHz (the minimum pattern length T is T≈163 ns), and depends on the transmission rate Fs. In order to determine the value of the transmission rate Fs used for transmission at this time, in order to identify at the lowest possible frequency, the maximum pattern length 3T in the preamble PA which is the longest pattern is measured. Is the most advantageous.
[0019]
However, when there are three transmission rates Fs of 48 kHz, 44.1 kHz, and 32 kHz, it is common sense to count at a measurement frequency of 46 MHz at least in consideration of asynchronous errors. This is because the 3T pattern at Fs = 48 kHz is 488 ns, and when counted at 46 MHz, the count number “22” or “23” is counted, and the 3T pattern at Fs = 44.1 kHz is 531 ns and the same. This is because 48 kHz and 44.1 kHz having a small frequency difference can be separated by the count value only when the count number “24” or “25” is counted when counting at 46 MHz.
[0020]
[Rate discrimination algorithm]
According to one embodiment of the present invention, for a unique pattern of a signal received at a digital interface (for example, the longest pattern 3T of a preamble in an SPDIF format signal), this is simply counted with a fixed frequency clock. Instead, the fixed frequency of the measurement clock can be lowered by determining the transmission rate of the received signal in consideration of the number of occurrences of the unique pattern within the predetermined period. FIG. 2 is a flowchart representing a rate discrimination algorithm according to one embodiment of the present invention.
[0021]
First, in step S1, a wavelength (pattern length) generated from each input signal is counted as a first count value at a fixed predetermined clock frequency fc. The first count value n counted in step S1 is determined for each wavelength (pattern length) to be measured. In subsequent steps S2 to S4, the first count value n is sequentially compared with a predetermined first threshold value C1x = C10 to C12. Determined.
[0022]
The first threshold C1x = C10 in step S2 is set to a value smaller than the count value Cmin when a predetermined minimum wavelength (pattern length) is counted at the fixed clock frequency fc (C10 <Cmin). Therefore, if it is the original format data, n> C10 is determined in step S2 and the process proceeds to step S3. If not, it is an error and the process proceeds to step S5. The first threshold value C1x = C11 in step S3 is set to a value larger than the count value Cmax when a predetermined maximum wavelength (pattern length) is counted at the fixed clock frequency fc (C11> Cmax). Therefore, if it is the original format data, it is determined in step S3 that n <C11 and the process proceeds to step S4. If not, an error occurs and the process proceeds to step S5. In step S5, an error flag is set and the second count value m is reset.
[0023]
The first threshold value C1x = C12 in step S4 is set to a value larger than the count value Cmax2 when the next longest wavelength (pattern length) of the longest pattern in the format is counted at the fixed clock frequency fc (Cmax2 <C12). <Cmax), if n> C12 is determined in step S4, the process proceeds to step S6, and if not, the process returns to step S1. When the process proceeds to step S6, C12 <n <C11, which means detection of the longest pattern. Therefore, in step S6, the number of detections of the maximum pattern length is counted up as the second count value m using another counter (“ +1 ”count).
[0024]
In the next step S7, when it is determined that a certain predetermined sufficiently long measurement period Tc has not elapsed, the process returns to step S1 and such a step S1 → until the measurement period Tc elapses. The counting operation of the second count value m of S2->S3->S4-> S6 is repeated, and after this measurement time Tc has elapsed, the process proceeds from step S7 to step S8.
[0025]
In step S8, the second count value m is compared with the second threshold value C2, and if m> C2, the process proceeds to step S9 to determine that the transmission rate Fs is the rate A. Otherwise, the step S10 Then, it is determined that the transmission rate Fs is another rate B, and the rate discrimination algorithm for one time is finished.
[0026]
Of course, it goes without saying that the above-described measurement period Tc and the second threshold C2 are set so that the transmission rate Fs can be identified. For example, if the transmission rate is Fs = 48 kHz and 44.1 kHz in a format having a predetermined pattern that occurs only once per frame, the measurement period Tc is set to 1 kHz (1 ms). If Fs = 48 kHz signal, the number of times m = “48” should be counted, and if Fs = 44.1 kHz, the number of times m = “44” should be counted. Accordingly, by setting C2 = “46” or so as the reliable second threshold value C2 including the asynchronous error, Fs = 48 kHz / 44.1 kHz can be reliably identified. Further, when there are two or more rates to be identified, a plurality of second threshold values C2 can be prepared as C2 = C21, C22,.
[0027]
Thus, according to one embodiment of the present invention, not only the first threshold value C1x is used, but also the number of occurrences that satisfy the first threshold value C1x is counted based on the result m obtained by counting in a certain measurement period Tc. Thus, when the first threshold C1x is set, the transmission rate is determined by using a fixed measurement clock frequency fc lower than a common measurement frequency. be able to. Furthermore, since the clock for extracting each bit data can be digitally generated by the fixed frequency fc, a data extraction circuit can be realized without using an analog PLL. Thereby, in an actual circuit, it is possible to suppress power consumption, and to ensure an operation margin with a low measurement frequency and stability due to a digital circuit configuration.
[0028]
[First threshold setting method]
A numerical value setting method will be described when the rate discrimination algorithm according to one embodiment of the present invention is applied when the SPDIF format signal (SPDIF signal) described in FIG. 1 is received. FIG. 3 shows a waveform diagram and a table (1) for explaining a first threshold setting method in rate discrimination according to the present invention. In FIGS. 3 a) and b), a maximum rate (for example, 48 kHz) of transmission rate Fs candidates (for example, 48 kHz, 44.1 kHz, 32 kHz) is defined as Fsmax, and three patterns 3T to 3T at the maximum rate Fsmax are illustrated. T (3T = 3Tmin, 2T = 2Tmin, T = Tmin) is shown. The fixed clock frequency fc used for rate discrimination (measurement of the first count value n) is fc = b · Fsmax [for example, b = 512, fc = 24.576 MHz = 512 ×, as shown in FIG. 48 kHz] and is not clear in the figure, but is a completely asynchronous clock with respect to the SPDIF signal to be discriminated.
[0029]
First, the input signal has three patterns 3T to T as shown in FIGS. 3A and 3B. However, the input signal does not depend on the polarity, and the wavelength (pattern length) 3T to T has a meaning. is there. The signal for bit strobe of each wavelength is the minimum pattern length T, that is, the frequency a · Fs which is a times the transmission rate Fs as described above, and at least the maximum rate as shown in FIG. For Fsmax, a · Fsmax must be established, and it must be generated from the fixed clock frequency fc shown in FIG.
[0030]
Therefore, for example, a = 128 and b = 512 can be set for the maximum rate Fsmax. In this case, the magnification c = b / a of the clock frequency fc with respect to the minimum pattern length T = Tmin at the maximum rate Fsmax is c = 4, and the period t of the measurement clock with the fixed frequency fc is t = Tmin / c = Tmin / 4 as shown in FIG. 3d).
[0031]
As a process for setting each threshold value, in order to simplify the explanation, first, when the measurement clock frequency fc is synchronized with the transmission rate Fs, the above numerical example (a = 128, b = 512, c = 4), the count values of the patterns 3T, 2T, and T at the respective transmission rates Fs = 48 kHz, 44.1 kHz, and 32 kHz are shown in columns (a), (b), and (c) of the table (1) in FIG. It is as follows. Here, when the transmission rate Fs of the SPDIF signal and the fixed frequency fc are asynchronous, it should be noted that an asynchronous error occurs at each location. For example, whether the measurement clock with the frequency fc = 512Fsmax is slightly faster or slower with crystal accuracy than the frequency a · Fs = 128Fs of the SPDIF signal pattern, an asynchronous error occurs with a width of about ± 1 clock (Ck). To do.
[0032]
Therefore, in this case, if the longest pattern 3T is detected from the table (1) for rate discrimination, the first count value m that can be counted at the fixed clock frequency fc for each transmission rate Fs is When Fs = 48 kHz in column A, m = “12 ± 1” (meaning “11” to “13”), and when Fs = 44.1 kHz in column B, m = “13 + 1” (“13”). Or “14”), and in the case of Fs = 32 kHz in column C, m = “18 ± 1” (“17” to “19”). Therefore, the transmission rate Fs of 48 kHz and 44.1 kHz has an overlap in the first count value m that can be measured and cannot be completely identified.
[0033]
[Second threshold setting method]
Therefore, in the present invention, a method is used in which the measurement period Tc is provided and the number of detections of the longest pattern 3T is determined by the second threshold C2. FIG. 4 shows a table (2) for explaining a second threshold setting method in rate discrimination according to the present invention. This table (2) sets the measurement period Tc to k times the one cycle of the maximum rate Fsmax = 48 kHz of the transmission rate Fs, and k = 8, 16, 24, 32 (Tc = 166.7 μs, 333). (3 μs, 500 μs, 666.7 μs), the number of subframes (P) at each transmission rate Fs = 48 kHz (A), 44.1 kHz (B), 32 kHz (C) ), The number of detections (Q) of the longest pattern 3T and the second threshold value C2. As a result, the measurement period magnification k = 32, that is, the measurement period Tc = 666.7 μs (48 kHz / 32 = 1.5 kHz in terms of frequency) is extended to 48 kHz of the transmission rate Fs by the second threshold C2. And 44.1 kHz can be discriminated.
[0034]
In addition to the method of setting the second threshold C2 by the number of detections of the longest pattern 3T, the number of detected preambles can be set as the second count value. In this case, as described above, Therefore, the second threshold C2 may be set to “46” with Tc = 1 ms (1 kHz frequency).
[0035]
[Specific example of rate discrimination algorithm]
FIG. 5 shows a more detailed example of the rate discrimination algorithm according to one embodiment of the present invention. In step R1, when the first count value n corresponding to each pattern length is obtained with respect to the first threshold value Clx, the comparison is sequentially performed in subsequent steps R2 to R4. In step R2, it is determined whether or not 2 <n <19. When 2 <n <19, the process proceeds to step R3. When n ≦ 2 or n ≧ 19, the range of maximum 3T / minimum T is set. This is a case where an excessive pattern length is input. In this case, the process proceeds to step R5 and is treated as an error. For example, it is possible to determine a state in which no signal is input. Accordingly, when the routine proceeds to step R5, the error flag f0 is set and the routine proceeds to step R6, where the calculation operation of the second count value m (function of step R8) to be described later is reset.
[0036]
On the other hand, in step R3, it is further determined whether or not n <16. If n <16, the process proceeds to step R4. Otherwise, if n ≧ 16 (16 ≦ n ≦ 18), the process proceeds to step R4. Proceeding to R7, it is determined that Fs = 32 kHz alone, and the first state flag f1 representing the state of Fs = 32 kHz is set, and then the processing proceeds to step R6. In this case, as a process for demodulating the data bits of the SPDIF reception signal, step R7 ′ is inserted between steps R3 and R7 as indicated by a broken line, and a strobe clock for data bit demodulation is switched (a bit extraction pulse train described later). (See p1 and p2). If n <16 and the process proceeds to step R4, it is determined in this step R4 whether or not 10 ≦ n ≦ 15. If 10 ≦ n ≦ 15, the process proceeds to step R8, and if not, the process proceeds to step R1. Return.
[0037]
Here, when 10 ≦ n ≦ 15, it is a case where the longest pattern 3T at the time of Fs = 48 kHz or 44.1 kHz is detected. This is the second count value corresponding to the second threshold value C2 in step R8. Find m. At this time, the second count value m is counted by the m counter in the measurement period Tc = 666.7 μs (1.5 kHz), and the process proceeds to step R9. In Step R9, the second count value m is determined by the second threshold C2, and specifically, it is determined whether m <92. Here, when m <92, the process proceeds to step R10 to set Fs = 44.1 kHz, sets the second state flag f2 indicating the state of Fs = 44.1 kHz, and then proceeds to step R6. Otherwise, the process proceeds to step R11 to set Fs = 48 kHz, sets a third state flag f3 representing the state of Fs = 48 kHz, and then proceeds to step R6. That is, it is determined that Fs is 48 kHz or 44.1 kHz depending on whether the second count value m is larger or smaller than the second threshold C2 = 92.
[0038]
In step R6, the results obtained in steps R7, R10, and R11 are latched and output in units of the measurement period Tc, and the m counter that counts the second count value m is reset to clear the contents. At the same time, in the next step R12, the error flag f0 is canceled when the error is not the error described above, that is, when any of the first to third state flags f1, f2, and f3 is detected. To do.
[0039]
[Transmission rate discrimination and data extraction circuit example]
FIG. 6 shows a transmission rate discrimination and data extraction circuit according to an embodiment of the present invention. The transmission rate discrimination and data extraction circuit RS shown in FIG. 6 is an example of a circuit that realizes the above-described transmission rate discrimination algorithm, and includes a change point detection circuit 1 that detects a change point (edge) of the input signal Si, and wavelength measurement. A first counter 2, a first comparison circuit 3, a decoder 4, a switching circuit 5, a demodulation circuit 6, a timing circuit 7 for generating a measurement timing signal for determining a measurement period Tc, and a maximum wavelength. A second counter 8 for counting the number of detected times m, a second counter 8 for counting the number of times of detection of the predetermined pattern, a second comparison circuit 9 for the second threshold C2, and an output circuit for latching each output state from both comparison circuits 3 and 9 in the measurement period Tc. 10, the rate discrimination block RD is mainly composed of the circuits 1 to 3 and 7 to 10, and the data extraction block DS is composed of the circuits 4 to 6. That.
[0040]
The input signal Si is, for example, a modulated signal in SPDIF format, and the clock Ck is set to a fixed frequency fc of 24.576 MHz as in the above example. The change point detection circuit 1 detects the change point (edge) of the pattern of the SPDIF input signal Si using the clock Ck, and the wavelength measurement counter 2 detects from the change point of the detected pattern of the signal Si to the change point. Count with clock Ck.
[0041]
The first count value n output from the first counter 2 represents the wavelength of the predetermined pattern of the input signal Si, and is compared with a predetermined first threshold C1x = C10 to Cl2 by the first comparison circuit 3, The decoder 4 generates timing pulse trains p1 and p2 of the frequency a · Fs (= 128Fs) for extracting the preamble and data bits with respect to the transmission rate Fs that is input to the decoder 4 and assumed for the input signal Si. .
[0042]
More specifically, the decoder 4 can output two types of bit extraction pulse trains p1 and p2 assuming (a) Fs = 32 kHz and (b) other (Fs = 48 kHz and Fs = 44.1 kHz). These pulse trains p1 and p2 are switched to either one by the switching circuit 5 and output to the demodulation circuit 6, and are used to demodulate the input signal Si. The output switching of the bit extraction pulse trains p1 and p2 by the switching circuit 5 is determined by whether or not the transmission rate Fs = 32 kHz is detected as a result of determining the first count value n in the first comparison circuit 3, and (a) Fs When detecting = 32 kHz, the corresponding pulse train p1 is output. (B) Otherwise, the pulse train p2 is output. In the demodulating circuit 6, the Biφ modulation of the SPDIF input signal Si is demodulated using the bit extraction pulse train p1 or p2 from the switching circuit 5, and at the same time, each data is serial-parallel converted in units of words to extract data. The extracted data SD is output.
[0043]
The first comparison circuit 3 determines that the first count value n is n <3 with respect to the minimum value “3”, the maximum value “18”, and the intermediate values “10” and “16” of the first threshold C1x, for example. When n> 18, the error signal Sf0 is output to the timing circuit 7 and the latch circuit 10, and when 16 ≦ ns ≦ 18, the first determination signal Sf1 representing the transmission rate Fs = 32 kHz is output to the switching circuit 5 and the latch circuit 10. Output to. Further, when 10 ≦ n <16, a second determination signal Sfa representing other values (Fs = 48 kHz and Fs = 44.1 kHz) is output from the comparison circuit 3, and the number of times this signal Sfa is generated is counted second. The value m is counted by the second counter 8.
[0044]
The measurement period Tc for counting the number m is determined by a measurement timing signal generated by the timing circuit 7 that divides the clock Ck by the timing circuit 7. In this example, a measurement timing signal Stc of 1.5 kHz is output from the timing circuit to the second counter 8, and the measurement period Tc of the number m of times in the second counter 8 is defined. The second count value m counted during the period of the measurement timing signal Stc is given from the second counter 8 to the second comparison circuit 9, where it is compared with the second threshold C2 = “92”. As a result of this comparison, it is determined whether Fs = 48 kHz or 44.1 kHz, and a third determination signal Sfb representing the determination content is output to the latch circuit 10.
[0045]
In the latch circuit 10, the signals Sf0, Sf1, and Sfb are latched in units of a predetermined measurement period Tc by the timing signal Stc from the timing circuit 7, and the state data f0 to f3 representing the corresponding contents are output at the same timing. Is done. For example, the error flag f0 and the first state flag f1 are output in response to the error signal Sf0 and the first determination signal Sf1 from the first comparison circuit 3, respectively. Further, the second or third state flags f2 and f3 are output according to the content (Fs = 48 kHz or Fs = 44.1 kHz) represented by the third determination signal Sfb input from the second comparison circuit 9.
[0046]
〔The invention's effect〕
As described above, according to the present invention, the transmission rate is determined by targeting a specific arbitrary pattern in the digital interface signal. In this case, the transmission rate is determined only by determining the pattern length based on the predetermined first threshold value C1x. In addition to determining the transmission rate, a process for counting the number of occurrences of the predetermined pattern length in a certain measurement period Tc is added to determine the transmission rate. Therefore, it is possible to realize transmission rate discrimination using a lower fixed frequency for pattern length discrimination.
[0047]
Further, according to the present invention, it is possible to digitally generate a clock for extracting each bit data at the fixed frequency, so that a data extraction circuit can be realized without using an analog PLL. As a result, power consumption can be suppressed in an actual circuit, and an operation margin due to a low frequency and stability due to a digital circuit configuration can be ensured.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a transmission format (“SPDIF format”) to which the present invention is applicable.
FIG. 2 is a flowchart showing a transmission rate discrimination algorithm according to one embodiment of the present invention.
FIG. 3 is a waveform diagram and a table (1) for explaining a first threshold setting method in a transmission rate discrimination algorithm according to an embodiment of the present invention.
FIG. 4 is another table (2) for explaining a second threshold setting method in the transmission rate discrimination algorithm according to one embodiment of the present invention.
FIG. 5 is a flowchart showing a more detailed example of a transmission rate determination algorithm according to an embodiment of the present invention.
FIG. 6 is a diagram showing a transmission rate discrimination and data extraction circuit according to one embodiment of the present invention.
[Explanation of symbols]
Fs transmission rate (sampling frequency),
T Minimum pattern length or shortest pattern,
2T bit rate compatible pattern length (corresponding to 1 time slot),
3T maximum pattern length or longest pattern,
PA preamble pattern,
n First count value (pattern length count value),
m second count value (number of specific pattern detections),
Fsmax maximum rate (maximum transmission rate among candidates for transmission rate Fs),
Tmin Minimum pattern length at maximum rate Fsmax,
2Tmin Bit rate corresponding pattern length at maximum rate Fsmax,
3Tmin Maximum pattern length at maximum rate Fsmax,
fc Measurement clock frequency with period t,
a Magnification factor for the transmission rate Fs of the frequency corresponding to the minimum pattern length,
b The magnification of the measurement clock frequency fc with respect to the maximum rate Fsmax,
c Measurement clock frequency magnification with respect to minimum pattern length Tmin,
RS transmission rate discrimination and data extraction circuit,
p1 bit extraction pulse train corresponding to transmission rate Fs = 32 kHz,
p2 bit extraction pulse train corresponding to transmission rate Fs = 44.1 kHz / 48 kHz,
error flag obtained based on the f0 error signal Sfo,
f1 a first state flag obtained based on the first determination signal Sf1,
Sfa second discrimination signal,
f2, f3 second and third state flags obtained based on the contents of the third discrimination signal Sfb,
f4 State confirmation result flag.

Claims (4)

In a digital interface for reproducing a digital interface signal transmitted at any one of a plurality of predetermined transmission rates,
Measuring a pattern length with a fixed frequency clock for a specific pattern in a transmitted digital interface signal;
A pattern length detection step for detecting a predetermined pattern length from each measured pattern length;
A detection frequency calculation step for calculating the detection frequency of a predetermined pattern length in a predetermined period;
Determining the calculated number of detections;
Determining the transmission rate of the transmitted digital interface signal based on the determined number of detections. In a digital interface for reproducing a digital interface signal transmitted at any one of a plurality of predetermined transmission rates,
Measuring a pattern length with a fixed frequency clock for a specific pattern in a transmitted digital interface signal;
A pattern length detection step for detecting a predetermined pattern length from each measured pattern length;
A detection frequency calculation step for calculating the detection frequency of a predetermined pattern length in a predetermined period;
Determining the calculated number of detections;
Determining a transmission rate of a digital interface signal to be transmitted based on the determined pattern length or number of detections. In the pattern length detection step, when an insufficient or excessive pattern length that cannot be generated in the digital interface format is detected for the measured pattern length, the operation in the detection number calculation step is reset, The transmission rate determination method according to claim 1, wherein control is performed so as to start a calculation operation of the number of detection times. In a digital interface for reproducing a digital interface signal transmitted at any one of a plurality of predetermined transmission rates,
A first counter that measures a pattern length of a specific pattern in a transmitted digital interface signal with a clock having a fixed frequency;
A first comparison circuit that compares the measured pattern length with a first threshold and detects a predetermined pattern length;
A second counter for calculating the number of times the predetermined pattern length is detected by the first comparison circuit during the predetermined period;
A second comparison circuit for comparing and determining the calculated number of times with a second threshold;
An output circuit for outputting transmission rate information of a digital interface signal to be transmitted based on the determined number of times.

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