JP4312771B2 - Differential differential amplifier - Google Patents

Description

  The present invention generally relates to differential differential amplifiers.

  Low voltage differential signaling (LVDS) interfaces are increasingly being used for large scale integrated circuits in electronic consumer devices. An LVDS receiver having at least one differential differential amplifier (DDA) is used to receive and amplify LVDS signals for use by other electronic circuits.

  An example of a conventional LVDS receiver 110 is shown in the circuit diagram of FIG. The LVDS receiver 110 includes two DDAs 120 a and 120 b, one differential amplifier 130, and a multiplexer 140. A conventional example of DDA 120a and 120b is illustrated in the circuit diagram of FIG. The DDA 120 has a first pair of P-channel metal oxide semiconductor (PMOS) transistors 210a, b and a second pair of PMOS transistors 220a, b. The DDA 120 further includes four N-channel metal oxide semiconductor (NMOS) transistors 230a to 230d and four PMOS transistors 240a to 240d, and is configured as shown in FIG.

However, the conventional LVDS receiver 110 of FIG. 1 is susceptible to signal noise. The LVDS receiver 110 can also operate at a low voltage, as is sometimes required by portable applications. Moreover, this conventional LVDS receiver 110, the input voltage versus (PAD, PADN) common mode voltage of, for example, close to a ground _{V SS,} whereas, a common mode voltage of the reference voltage versus _{(V ref1,} V _ref2) However, when it is close to V _DD / 2, it may not operate normally. V _DD corresponds to a power supply voltage. In this state, the drain voltage of the first transistor set 210a, b shown in FIG. 2 is pulled to the level of the drain voltage of the second transistor set 220a, b. The respective drain-source voltages of the first transistor set 210a, b and the second transistor set 220a, b cause the first transistor set 210a, b to operate in the tripolar region. The tripolar region is also called a resistive region. On the other hand, the second set of transistors 220a, 220b operates in the pentapole region. The pentode region is also called the saturation region. Such a difference in the operating region of each of the two transistor sets 210a, b, 220a, b is the difference between the input voltage pair (PAD, PADN) and the reference voltage pair (V _ref1 , V _ref2 ) at node 250. This results in an output voltage _Vout having an amplitude that is not proportional to the difference between.

  Another variation of the LVDS receiver is a conventional differential operational amplifier (op-amp) 310 shown in the circuit diagram of FIG. The differential operational amplifier 310 includes NMOSFETs 320a to 320j, PMPSFETs 330a to 330j, a capacitor 350, and an inverter 360, and is configured as shown in FIG. Differential operational amplifier 310 may allow operation over a wider common mode range (CMR). However, the differential operational amplifier 310 is also susceptible to signal noise, and generally cannot operate at a low voltage.

  Accordingly, it is an object of the present invention to provide a DDA configured to operate efficiently over a wider CMR. Another object of the present invention is to provide a DDA having an increased tolerance for noise. Another object of the present invention is to provide a DDA that can operate at a low voltage.

  The differential differential amplifier has first and second low power output terminals and first and second high power output terminals, and one or more of the first and second low power output terminals. And one or more of the first and second high power output terminals are coupled to a low voltage terminal and a high voltage terminal, respectively. The first bias regulator has a first output terminal that supplies a first bias voltage, and a second output terminal that supplies a second bias voltage. The second bias regulator has first and second output terminals.

  First, second, third and fourth current control PMOS transistors are also provided, each having a gate, source and drain. The sources of these transistors are coupled to each other and to the high power supply output terminal. The gates of the first and second current control PMOS transistors are respectively coupled to the first and second terminals of the first pair of differential input terminals. The gates of the third and fourth current control PMOS transistors are coupled to the first and second terminals of the second pair of differential input terminals, respectively.

  The differential differential amplifier further includes first and second load current control PMOS transistors each having a gate, a source and a drain. The sources of the first and second load current control PMOS transistors are coupled to the first high power supply output terminal, and the gates of the first and second load current control PMOS transistors are connected to the first high power output PMOS transistor. Coupled to the first output terminal of the bias regulator.

  First, second, third, and fourth current control NMOS transistors are also provided, each having a gate, source, and drain. The sources of the first, second, third and fourth current control NMOS transistors are coupled to each other and to the low power supply output terminal. The gates of the first and second current control NMOS transistors are coupled to first and second terminals of a first pair of differential input terminals, respectively. The gates of the third and fourth current control NMOS transistors are coupled to the first and second terminals of the second pair of differential input terminals, respectively.

  The differential differential amplifier further includes first and second load current control NMOS transistors each having a gate, a source and a drain. The sources of the first and second load current control NMOS transistors are coupled to the first low power output terminal, and the gates of the first and second load current control NMOS transistors are the first and second load current control NMOS transistors. Coupled to the second output terminal of the bias regulator.

  First and second voltage controlled PMOS transistor circuits are also provided, each having a gate terminal, at least one source terminal, and a drain terminal. At least one source terminal of the first voltage control PMOS transistor circuit is coupled to the drains of the first and fourth current control PMOS transistors and to the drain of the first load current control PMOS transistor. At least one source terminal of the second voltage control PMOS transistor circuit is coupled to the drains of the second and third current control PMOS transistors and to the drain of the second load current control PMOS transistor. The gate terminal of the first voltage control PMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control PMOS transistor circuit is coupled to the second output terminal of the second bias regulator.

  In addition, first and second voltage controlled NMOS transistor circuits each having a gate terminal, at least one source terminal, and a drain terminal are provided. At least one source terminal of the first voltage control NMOS transistor circuit is coupled to the drains of the first and fourth current control NMOS transistors and to the drain of the first load current control NMOS transistor. At least one source terminal of the second voltage control NMOS transistor circuit is coupled to the drains of the second and third current control NMOS transistors and to the drain of the second load current control NMOS transistor. The gate terminal of the first voltage controlled NMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage controlled NMOS transistor circuit is coupled to the second output terminal of the second bias regulator.

  The drain terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit are coupled to a first terminal of a pair of differential output terminals. The drain terminals of the first voltage control PMOS transistor circuit and the first voltage control NMOS transistor circuit are coupled to a second terminal of the pair of differential output terminals.

  In another embodiment, the gates of the first and second load current control PMOS transistors are coupled to first and second output terminals of the second bias regulator, respectively. The gates of the first and second load current control NMOS transistors are coupled to first and second output terminals of the second bias regulator, respectively. The gate terminal of the first voltage control PMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage control PMOS transistor circuit is coupled to the second output terminal of the second bias regulator. The gate terminal of the first voltage controlled NMOS transistor circuit is coupled to the first output terminal of the second bias regulator. The gate terminal of the second voltage controlled NMOS transistor circuit is coupled to the second output terminal of the bias regulator.

  In yet another embodiment, the gates of the first and second load current control PMOS transistors are coupled to first and second output terminals of the second bias regulator, respectively. The gates of the first and second load current control NMOS transistors are coupled to first and second output terminals of the second bias regulator, respectively. The gate terminals of the first and second voltage control PMOS transistor circuits are coupled to the first output terminal of the first bias regulator. The gate terminals of the first and second voltage controlled NMOS transistor circuits are coupled to a second output terminal of the first bias regulator.

  The present invention makes it possible to provide a DDA configured to operate efficiently over a wider CMR. Desirably, the DDA can also have an increased tolerance for noise. Also more desirably, the DDA can operate at a low voltage.

  The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the following description, are useful for explaining the advantages and principles of the invention. is there.

  Hereinafter, embodiments of the present invention will be described in detail. These embodiments are illustrated in the accompanying drawings. Wherever possible, the same reference numbers may be used throughout the drawings to refer to the same or like parts.

A differential differential amplifier (DDA) is configured to amplify the difference between two different inputs applied to the DDA as a set of input voltages (V _PP , V _PN ) and a set of reference voltages (V _NP , V _NN ). Is done. The DDA can be used in a variety of applications, including as part of a “low voltage differential signal” (LVDS) configured to receive and amplify an LVDS signal for use by downstream circuitry.

  FIG. 4 is a circuit diagram of an exemplary embodiment of DDA 410 according to the present invention. The DDA 410 of FIG. 4 is provided only to illustrate the present invention and should not be used to limit the scope of the present invention or equivalents of the exemplary embodiments provided herein. Throughout some of the remaining drawings, the DDA 410 is represented by the objects shown in the circuit diagram of FIG.

As shown in FIG. 4, the DDA 410 includes a first set of differential input terminals having first and second terminals 420a and 420b that receive a set of input voltages V _PP and V _PN , respectively, and a reference voltage And a second set of differential input terminals having first and second terminals 420c, 420d for receiving the sets V _NP and V _{NN respectively} . The DDA 410 also has a pair of differential output terminals having first and second terminals 430a, 430b.

The DDA 410 has a low voltage terminal 470 at a low voltage (V _SS ) and a high voltage terminal 480 at a high voltage (V _DD ). One or more of the low voltage V _SS and the high voltage V _DD are derived from a power source. In one embodiment, the low voltage V _SS is ground as shown in FIG. The DDA 410 also includes first and second low power output terminals 450a and 450b, and first and second high power output terminals 460a and 460b. One or more of the first and second low power output terminals 450a, 450b are coupled to the low voltage terminal 470 and one of the first and second high power output terminals 460a, 460b or The further is coupled to the high voltage terminal 480.

The first bias regulator 490 has a first output terminal 500 that supplies a first bias voltage, and a second output terminal 510 that supplies a second bias voltage. In one embodiment, as represented in FIG. 4, the first bias regulator 490 includes a source having a source coupled to the high voltage V _DD and a drain and a source coupled to the first output terminal 500. A transistor 520 is included. First bias regulator 490 also includes a source coupled to the low voltage _{V SS,} and a drain coupled to the drain of the PMOS transistor, an NMOS transistor 530 having a gate coupled to the second output terminal 510 Have.

  The DDA 410 further includes first, second, third, and fourth current control PMOS transistors 540a-540d. Each of the transistors 540a to 540d has a gate, a source, and a drain. The sources of current control PMOS transistors 540a-540d are coupled to each other and to the second high power output terminal 460b. The gates of the first and second current control PMOS transistors 540a, 540b are respectively coupled to the first and second terminals 420a, 420b of the first pair of differential input terminals. The gates of the third and fourth current control PMOS transistors 540c, 540d are coupled to the first and second terminals 420c, 420d of the second pair of differential input terminals, respectively.

  The DDA 410 further includes first and second load current control PMOS transistors 550a and 550b. Each of the transistors 550a and 550b has a gate, a source, and a drain. The sources of the load current control PMOS transistors 550a, 550b are coupled to the first high power output terminal 460a. The gates of the load current control PMOS transistors 550a, 550b are coupled to the first output terminal 500 of the first bias regulator 490.

  The DDA 410 further includes first, second, third, and fourth current control NMOS transistors 560a to 560d. Each of transistors 560a-560d also has a gate, a source, and a drain. Their sources are coupled to each other and to the second low power output terminal 450b. The gates of the first and second current control NMOS transistors 560a, 560b are respectively coupled to the first and second terminals 420a, 420b of the first pair of differential input terminals. The gates of the third and fourth current control NMOS transistors 560c, 560d are coupled to the first and second terminals 420c, 420d of the second pair of differential input terminals, respectively.

  Further, the DDA 410 further includes first and second load current control NMOS transistors 570a and 570b. Each of the load current control NMOS transistors 570a and 570b has a gate, a source, and a drain. The sources of these transistors are coupled to the first low power supply output terminal 450a and the gates are coupled to the second output terminal 510 of the first bias regulator 490.

  The first, second, third and fourth current control PMOS transistors 540a-540d may have substantially the same electrical characteristics. The first and second load current control PMOS transistors 550a and 550b have substantially the same electrical characteristics and higher conductivity than the first, second, third and fourth current control PMOS transistors 540a to 540d. You may have. The first, second, third and fourth current control NMOS transistors 560a-560d may also have substantially the same electrical characteristics. Further, the first and second load current control NMOS transistors 570a, 570b have substantially the same electrical characteristics as each other and higher conductivity than the first, second, third, and fourth current control NMOS transistors 560a-560d. You may have.

  The DDA 410 includes first and second voltage control PMOS transistor circuits 610a and 610b. Each of the circuits 610a, 610b has one or more PMOS transistors 610a1, 610b1, each having a gate terminal, a source terminal, and a drain terminal. The source terminal of the first voltage control PMOS transistor circuit 610a is coupled at node 590a to the drains of the first and fourth current control PMOS transistors 540a, 540d and to the drain of the first load current control PMOS transistor 550a. Yes. The source terminal of the second voltage control PMOS transistor circuit 610b is coupled at node 590b to the drains of the second and third current control PMOS transistors 540b, 540c and to the drain of the second load current control PMOS transistor 550b. Yes. First and second voltage controlled NMOS transistor circuits 620a, 620b are also provided, each of the circuits 620a, 620b having one or more NMOS transistors 620a1, 620b1, each having a gate terminal, a source terminal, and a drain terminal. . The source terminal of the first voltage control NMOS transistor circuit 620a is coupled at node 590c to the drains of the first and fourth current control NMOS transistors 560a, 560d and to the drain of the first load current control NMOS transistor 570a. Yes. The source terminal of the second voltage control NMOS transistor circuit 620b is coupled at node 590d to the drains of the second and third current control NMOS transistors 560b, 560c and to the drain of the second load current control PMOS transistor 570b. Yes.

  The first terminal 430a of the pair of differential output terminals is coupled to the drain terminal of the second voltage control PMOS transistor circuit 610b and to the drain terminal of the second voltage control NMOS transistor circuit 620b. The second terminal 430b of the pair of differential output terminals is coupled to the drain terminal of the first voltage control PMOS transistor circuit 610a and to the drain terminal of the first voltage control NMOS transistor circuit 620a.

  The first and second voltage control PMOS transistor circuits 610a and 610b may have substantially the same electrical characteristics. The first and second voltage control PMOS transistor circuits 610a, 610b may also have a higher conductivity than the first, second, third and fourth current control PMOS transistors 540a-540d. Further, the first and second voltage controlled NMOS transistor circuits 620a and 620b may have substantially the same electrical characteristics. Further, the first and second voltage controlled NMOS transistor circuits 620a, 620b may have a higher conductivity than the first, second, third and fourth current controlled NMOS transistors 560a-560d.

  The second bias regulator 630 is coupled to the gate terminal of the first voltage control PMOS transistor circuit 610a and the gate terminal of the first voltage control NMOS transistor circuit 620a at the first output terminal 635a to provide a second voltage control. The second output terminal 635b is coupled to the gate terminal of the PMOS transistor circuit 610b and the gate terminal of the second voltage control NMOS transistor circuit 620b.

One exemplary embodiment of the second bias regulator 630 is shown in FIG. In this embodiment, the second bias regulator 630 includes a first resistor 640a having a first terminal and a second terminal. The first terminal of the first resistor 640a is coupled to the second terminal 430b of the pair of differential output terminals. The second resistor 640b also has a first terminal and a second terminal. The first terminal of the second resistor 640b is connected to the second terminal of the first resistor 640a, to the gate terminals of the first and second voltage control PMOS transistor circuits 610a, 610b, and to the first and second terminals. Two NMOS transistor circuits 620a and 620b are coupled to the gate terminals. The second terminal of the second resistor 640b is coupled to the first terminal 430a of the pair of differential output terminals. Approximately a pair of differential output terminals 430a, first and center voltage _{V CM} magnitude of which is the magnitude of the average value of the second differential output voltage _{V CP, V CN} at 430b occurs at node 645 . As an example, the first and second resistors 640a and 640b of the second bias regulator 630 have substantially the same electrical resistance.

FIG. 6 shows a circuit diagram of another embodiment of the second bias regulator 630. This embodiment relates to the second bias regulator 630 is also a pair of differential output terminals _{V CP,} generates a center voltage _{V CM} of the _{V CN.} The second bias regulator 630 includes first, second, third, fourth, fifth and sixth NMOS transistors 650a to 650f. Further, first and second PMOS transistors 660a and 660b are provided. Each of the transistors 650a to 650f, 660a, and 660b has a gate, a source, and a drain.

First, the source of the second, third and fourth NMOS transistors 650a~650d is to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470. The drains of the first and second NMOS transistors 650a, 650b are coupled to the source of the fifth NMOS transistor 650e. The drains of the third and fourth NMOS transistors 650c, 650d are coupled to the source of the sixth NMOS transistor 650f. The drain of the fifth NMOS transistor 650e is connected to the gate of the fifth NMOS transistor 650e, to the gate of the sixth NMOS transistor 650f, to the drain of the first PMOS transistor 660a, and to the first and second PMOS transistors 660a. , 660b. The drain of the sixth NMOS transistor 650f is coupled to the drain of the second PMOS transistor 660b. The sources of the first and second PMOS transistors 660a, 660b are coupled to the high voltage terminal 480 to receive the high voltage V _DD . The gates of the third and fourth NMOS transistors 650c, 650d are coupled to each other to the drain of the sixth NMOS transistor 650f and to the first and second output terminals 635a, 635b. The gate of the first NMOS transistor 650 a is coupled to the second terminal 430 b of the pair of differential output terminals of the DDA 410. The gate of the second NMOS transistor 650b is coupled to the first terminal 430a of the pair of differential output terminals of the DDA 410.

  FIG. 7 is a circuit diagram of yet another exemplary embodiment of the second bias regulator 630. In this embodiment for the second bias regulator 630, the first and second output terminals 635a, 635b are coupled to the second terminal 430b of the pair of differential output terminals of the DDA 410. Accordingly, the gate terminals of the first voltage control NMOS transistor circuit 620a and the first voltage control PMOS transistor circuit 610a are connected to the gate terminals of the second voltage control PMOS transistor circuit 610b and the second voltage control NMOS transistor circuit 620b. And a second terminal 430b of the pair of differential output terminals.

  FIG. 8 is a circuit diagram of a further exemplary embodiment of the second bias regulator 630. The second bias regulator 630 of this embodiment includes first, second, and third resistors 670a to 670c. Each of resistors 670a-670c has a first terminal and a second terminal. The second terminal of the first resistor 670a and the first terminal of the second resistor 670b are coupled to each other to provide a second voltage control PMOS transistor circuit 610b and a second voltage control NMOS transistor circuit. Coupled to the second output terminal 635b for coupling to the gate terminal of 620b. The second terminal of the second resistor 670b and the first terminal of the third resistor 670c are coupled to each other to provide a first voltage control PMOS transistor circuit 610a and a first voltage control NMOS transistor circuit. Coupled to the first output terminal 635a for coupling to the gate terminal of 620a. The first terminal of the first resistor 670 a is coupled to the second terminal 430 b of the pair of differential output terminals of the DDA 410. The second terminal of the third resistor 670 c is coupled to the first terminal 430 a of the pair of differential output terminals of the DDA 410.

For the voltage control PMOS and NMOS transistor circuits 610a, 610b, 620a, 620b, the common mode voltage between the first and second output terminals 635a and 635b of the second bias regulator 630 is the differential output voltage of the DDA 410. V _CP provides a negative feedback to the center voltage V _{CM of} V _CN , while the positive differential voltage between the first and second output terminals 635a and 635b of the second bias regulator 630 is the DDA 410 Provides positive feedback to the differential output voltage V _CP , V _CN . Therefore, the second bias regulator 630 in FIG. 8 causes the DDA 410 to function as a comparator.

DDA410, as shown in FIG. 4, to couple the low voltage _{V SS} and the high voltage _{V DD} to DDA410, may have a switching voltage source 440. The switching voltage source 440 includes (i) a first low power output terminal 450a and a second high power output terminal 460b, respectively, or (ii) a second low power output terminal 450b and a first high power output terminal 460a. Are selectively coupled to the low voltage terminal 470 and the high voltage terminal 480.

One embodiment of the switching voltage source 440 of FIG. 4 is represented in FIG. This embodiment for the switching voltage source 440 includes first and second switching NMOS transistors 680a and 680b. Each of the transistors 680a and 680b has a gate, a source, and a drain. The drain of the first switching NMOS transistor 680a is coupled to the first low power output terminal 450a. The drain of the second switching NMOS transistor 680b is coupled to the second low power output terminal 450b. First and second switching NMOS transistor 680a, source 680b is to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470.

The switching voltage source 440 of the present embodiment also includes first and second switching PMOS transistors 690a and 690b. Each of the transistors 690a and 690b has a gate, a source, and a drain. The drain of the first switching PMOS transistor 690a is coupled to the first high power output terminal 460a. The drain of the second switching PMOS transistor 690b is coupled to the second high power output terminal 460b. The sources of the first and second switching PMOS transistors 690a, 690b are coupled to the high voltage terminal 480 to receive the high voltage V _DD .

The first and second inverters 700 a and 700 b are also provided in the present embodiment relating to the switching voltage source 440. Each of the first and second inverters 700a and 700b has an input terminal and an output terminal. The output terminal of the first inverter 700a is coupled to the output terminal of the second inverter 700b and to the gates of the first switching NMOS transistor 680a and the first switching PMOS transistor 690a. Input terminal of the first inverter 700a is to receive a first input voltage V _PP, is coupled to a first terminal 420a of the first pair of differential input terminals, the input terminal of the second inverter 700b It is to receive the second input terminal V _PN, is coupled to the second terminal 420b of the first pair of differential input terminals.

  The switching voltage source 440 further includes a third inverter 710 having an input terminal and an output terminal. The input terminal of the third inverter 710 is coupled to the output terminals of the first and second inverters 700a, 700b, and the output terminal of the third inverter 710 is connected to the second switching NMOS transistor 680b and the second switching NMOS transistor 680b. Coupled to the gate of switching PMOS transistor 690b.

A load current control PMOS transistor 720 having a gate, a source and a drain is also provided. The source of the load current control PMOS transistor 720 is coupled to the high voltage terminal 480 to receive the high voltage V _DD . The drain of the load current control PMOS transistor 720 is coupled to the output terminals of the first and second inverters 700a and 700b, and the gate of the load current control PMOS transistor 720 is coupled to the output terminal of the third inverter 710. ing.

Further, a load current control NMOS transistor 730 having a gate, a source and a drain is provided. The source of the load current control NMOS transistor 730, to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470. The drain of the load current control NMOS transistor 730 is coupled to the output terminals of the first and second inverters 700a and 700b, and the gate of the load current control NMOS transistor 720 is coupled to the output terminal of the third inverter 710. ing.

In operation, the values of the first pair of differential input voltages V _PP , V _{PN and} the second pair of differential input voltages V _NP , V _NN are the first and second inverters 700a, 700b of FIG. When the load current is determined by the control PMOS transistor 720 is higher than the higher threshold voltage, the second low power supply output terminal 450b is to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470, first high Power supply output terminal 460a is coupled to high voltage terminal 480 to receive high voltage V _DD . The current control NMOS transistors 560a to 560d and the load current control PMOS transistors 550a and 550b are activated, and the currents I _NPP , I _NPN , I _NNP , and I _NNN are respectively converted into the differential input terminal voltages V _PP , V _PN , V _NP , in each corresponding magnitude V _NN, it flows through the first, second, third and fourth current control NMOS transistor 560A～560d.

Returning to FIG. 4, the first and second load current control PMOS transistors 550a and 550b, the first and second voltage control PMOS transistor circuits 610a and 610b, and the first and second voltage control NMOS transistor circuits 620a and 620b. Is greater than the conductivity of the first, second, third and fourth current control NMOS transistors 560a-560d, the first and second current control NMOS transistors 560a, 560b are: Formula 1,
(1) V _DNP , V _DNN = V _DD −V _thN − | V _thP | −V _DSP
As shown by, the drain voltages V _DNP and V _DNN are kept sufficiently constant at nodes 590c and 590d, respectively. V _thP is a threshold voltage of the PMOS transistors of the first and second voltage control PMOS transistor circuits 610a and 610b, and V _thN is an NMOS transistor of the first and second voltage control NMOS transistor circuits 620a and 620b. V _DSP is a drain-source voltage of the load current control PMOS transistors 550a and 550b. Since the conductivity of the load current control PMOS transistors 550a, 550b is greater than the conductivity of the current control NMOS transistors 560a-560d, V _DSP is sufficiently small (ie, V _DSP ˜0).

The drain voltages V _DNP and V _{DNN of} the first and second current control NMOS transistors 560a and 560b are lower than the voltages V _PP −V _thN , V _PN −V _thN , V _NP −V _thN , and V _NN −V _thN. When held, the first, second, third and fourth current control NMOS transistors 560a-560d operate in the tripolar (non-saturated) region and have a pair of differential input voltages (V _PP −V _PN , V _NP −V _NN ), the difference between the respective voltages is:
_{(2) I P -I N =} G 1 · (V DD -V thN - | V thP | -V DSP) [(V PP -V PN) - (V NP -V NN)]
As it is shown by the results in the differential current _I P -I _N proportional to the voltage _V PP _{-V PN} and _V NP _{-V NN.} Incidentally, a _{G 1} is constant. Differential current _I P -I _N results in a differential output voltage _V CP _{-V CN} to approximately proportional to the difference current _I P -I _N. Therefore, the differential voltage V _CP −V _CN is given by Equation 3,
_{(3) V CP -V CN =} R · (I P -I N)
= R · G ₁ · (V _DD −V _thN − | V _thP | −V _DSP ) [(V _PP −V _PN ) − (V _NP −V _NN )]
Given by. Note that R is constant.

The first and second pair values of the differential input voltages V _PP , V _PN , V _NP , V _NN are determined by the first and second inverters 700a, 700b and the load current control NMOS transistor 730 of FIG. When lower than a lower threshold voltage, the first low power supply output terminal 450a is to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470, a second high power supply output terminal 460b, a high voltage _{V DD} Coupled to the high voltage terminal 480, the current control PMOS transistors 540a-540d and the load current control NMOS transistors 570a, 570b are activated. The currents I _PPP , I _PPN , I _PNP , and I _PNN have magnitudes corresponding to the differential input terminal voltages V _PP , V _PN , V _NP , and V _NN , respectively. 4 current control PMOS transistors 540a-540d. The conductivity of the first and second load current control NMOS transistors 570a, 570b, the first and second voltage control PMOS transistor circuits 610a, 610b, and the first and second voltage control NMOS transistor circuits 620a, 620b are: When the conductivity of the first, second, third, and fourth current control PMOS transistors 540a to 540d is larger than the drain voltages V _DPP and V _{DPN of} the first and second current control PMOS transistors 540a and 540b. Respectively in nodes 590a and 590b, respectively,
(4) V _DPP , V _DPN = V _thN + | V _thP | + V _DSN
Is kept at the same voltage sufficiently. V _DSN is a drain-source voltage of the load current control NMOS transistors 570a and 570b.

The drain voltages V _DPP and V _{DPN of} the first, second, third and fourth current control PMOS transistors 540a to 540d are the voltages V _PP + | V _thP |, V _PN + | V _thP |, V _NP + | When V _thP |, V _NN + | V _thP | are kept higher than the first, second, third and fourth current control PMOS transistors 540a to 540d, they operate in the three-pole region, and voltage V _PP −V _PN and V _NP −V _NN are expressed by the following equation (5):
_{(5) I P -I N =} G 2 · (V DD -V thN - | V thP | -V DSN) [(V PP -V PN) - (V NP -V NN)]
As indicated by the results in the differential current _I P -I _N be approximately proportional to the difference between the two differential input voltage _V PP _{-V PN} and _V NP _{-V NN.} Incidentally, a _{G 2} is constant. Differential current _I P -I _N results in a differential output voltage _V CP _{-V CN} proportional to the difference current _I P -I _N. Therefore, the difference between the differential voltages (V _CP −V _CN ) is
_{(6) V CP -V CN =} R 2 · (I P -I N)
= R ₂ · G ₂ · (V _DD −V _thN − | V _thP | −V _DSP ) [(V _PP −V _PN ) − (V _NP −V _NN )]
Given by. R ₂ is constant.

  Thus, the DDA 410 can operate efficiently over a desirable wide common mode range (CMR). This wide CMR can be advantageous in applications that require a wide input range. For example, the DDA 410 may have improved performance over a wide input range upon application of the DDA 410 in an LVDS receiver, as described in more detail below.

Since the drain-source voltages V _DSP and V _DSN of the load current control PMOS transistors 550a and 550b and the load current control NMOS transistors 570a and 570b can be made relatively small, respectively, the current control PMOS transistors 540a to 540d and the current When the drain-source voltages of the control NMOS transistors 560a to 560d are also relatively small, the high voltage V _DD is expressed by Equation 7:
(7) V _DD > V _thN + | N _thP |
Accordingly, the threshold voltage V _thN of the NMO transistor of the voltage control NMOS transistor circuits 620a and 620b and the sum of the threshold voltage | V _thP | of the PMOS transistor of the voltage control PMOS transistor circuits 610a and 610b are substantially close. Thus, DDA 410 can operate at a desirably low level of high voltage V _DD . The current flowing through the current control transistors 540a-540d, 560a-560d in the DDA 410 is limited by the voltage control transistor circuits 610a, 610b, 620a, 620b and by the load current control transistors 550a, 550b, 570a, 570b. Even if the high voltage V _DD increases, the total current consumption of the DDA 410 is sufficient by maintaining the voltage from the first output terminal 500 of the first bias regulator 490 to the load current control PMOS transistors 550a, 550b. It can be kept constant and at a low level.

  Furthermore, the DDA 410 can be controlled without the need for a special analog circuit component such as a bandgap reference circuit or a precision capacitor or resistor. Further, the individual electronic components of DDA 410 can be manufactured according to conventional CMOS logic manufacturing processes.

  As an example, as represented in the schematic diagram of the exemplary embodiment of FIG. 10, a single output DDA 720 includes a DDA 410 and a single output operational amplifier 730 having first and second input terminals 745a, 745b. Have The first and second terminals 430a, 430b of the pair of differential output terminals of the DDA 410 are coupled to the first and second input terminals 745a, 745b of the single output operational amplifier 730, respectively.

FIG. 11 is a circuit diagram of an exemplary embodiment of a single output operational amplifier 730 in the single output DDA 720 of FIG. The single output operational amplifier 730 includes first and second NMOS transistors 740a and 740b. First and second PMOS transistors 750a, 750b are also provided. Each of the NMOS and PMOS transistors has a gate, a source, and a drain. First and second NMOS transistors 740a, a source of 740b is to receive the low voltage _{V SS,} such as ground shown in FIG. 11, is coupled to the low voltage terminal 470. The sources of the first and second PMOS transistors 750a, 750b are coupled to the high voltage terminal 480 to receive the high voltage V _DD . The drain of the first NMOS transistor 740a is coupled to the drain of the first PMOS transistor 750a and to the gates of the first and second PMOS transistors 750a, 750b. The gate of the second NMOS transistor 740 b is coupled to the second input terminal 745 b of the single output operational amplifier 730. The gate of the first NMOS transistor 740a is coupled to the first input terminal 745a of the single output operational amplifier 730. The drains of the second NMOS transistor 740b and the second PMOS transistor 750b are coupled to a single-ended output 760 of a single output operational amplifier 730, as shown in FIG.

  As another example, as shown in the circuit diagram of the exemplary embodiment of FIG. 12, the differential output DDA 770 includes a DDA 410 and a differential output operational amplifier 775. The differential output operational amplifier 775 has first and second input terminals 780a and 780b. The first and second terminals 430a and 430b of the pair of differential output terminals of the DDA 410 are coupled to the first and second input terminals 780a and 780b of the differential output operational amplifier 775, respectively.

  FIG. 13 is a circuit diagram of an exemplary embodiment of a differential output operational amplifier 775 in the differential output DDA 770. The differential output operational amplifier 775 includes first and second NMOS transistors 782a and 782b. First and second PMOS transistors 784a, 784b are also provided. Each NMOS and PMOS transistor has a gate, a source and a drain. The differential output operational amplifier 775 further includes first and second resistors 786, 788, each resistor having a first terminal and a second terminal.

First and second NMOS transistors 782a, a source of 782b is to receive the low voltage _{V SS,} such as ground shown in FIG. 13, is coupled to the low voltage terminal 470. The sources of the first and second PMOS transistors 784a, 784b are coupled to the high voltage terminal 480 to receive the high voltage V _DD . The second terminal of the first resistor 786 is coupled to the first terminal of the second resistor 788 and to the gates of the first and second PMOS transistors 784a, 784b. The gate of the first NMOS transistor 782a is coupled to the first input terminal 780a of the differential output operational amplifier 775. The gate of the second NMOS transistor 782b is coupled to the second input terminal 780b of the differential output operational amplifier 775. The drain of the first NMOS transistor 782a is connected to the drain of the first PMOS transistor 784a, to the first terminal of the first resistor 786, and to the second terminal 790b of the pair of amplified differential output terminals. Are combined. The drain of the second NMOS transistor 782b is connected to the drain of the second PMOS transistor 784b, to the second terminal of the second resistor 788, and to the first terminal 790a of the pair of amplified differential output terminals. Are combined.

  As yet another example, the differential output differential differential comparator 820 includes a DDA 410 and a differential output comparator 830, as shown in the circuit diagram of the exemplary embodiment of FIG. The differential output comparator 830 has first and second input terminals 880a and 880b, and first and second terminals 910a and 910b of a pair of comparator differential output terminals. The first and second terminals 430a, 430b of the pair of differential output terminals of the DDA 410 are coupled to the first and second input terminals 880a, 880b of the differential output comparator 830, respectively.

  FIG. 15 is a circuit diagram of an exemplary embodiment of a differential output comparator 830 in the differential output differential differential comparator 820 of FIG. The differential output comparator 830 includes first and second NMOS transistors 850a and 850b. First and second PMOS transistors 860a and 860b are also provided. Each transistor 850a, 850b, 860a, 860b has a gate, a source and a drain. First, second and third resistors 870, 880, 890 are also provided. Each resistor has a first terminal and a second terminal.

First and second NMOS transistors 850a, a source of 850b is to receive the low voltage _{V SS,} such as ground shown in FIG. 15, is coupled to the low voltage terminal 470. The sources of the first and second PMOS transistors 860a, 860b are coupled to the high voltage terminal 480 to receive the high voltage V _DD . The second terminal of the first resistor 870 and the first terminal of the second resistor 880 are coupled to the gate of the second PMOS transistor 860b. The second terminal of the second resistor 880 and the first terminal of the third resistor 890 are coupled to the gate of the first PMOS transistor 860a. The gate of the first NMOS transistor 850a is coupled to the first input terminal 880a of the differential output comparator 830. The gate of the second NMOS transistor 850 b is coupled to the second input terminal 880 b of the differential output comparator 830. The drain of the first NMOS transistor 850a is coupled to the drain of the first PMOS transistor 860a, to the first terminal of the first resistor 870, and to the second terminal 910b of the pair of comparator differential output terminals. Has been. The drain of the second NMOS transistor 850b is coupled to the drain of the second PMOS transistor 860b, to the second terminal of the third resistor 890, and to the first terminal 910a of the pair of comparator differential output terminals. Has been.

FIG. 16 is a circuit diagram of an exemplary embodiment of a differential receiver 920 having a single output DDA, such as DDA 720 shown in FIG. The differential receiver 920 has an offset generator 930. The offset generator 930 includes first, second, and third capacitors 940a to 940c. Each of the capacitors has a first terminal and a second terminal. First, second, third and fourth switches 950a-950d are also provided. Each switch has a first terminal and a second terminal. The first terminal of the first switch 950a is coupled to the high voltage terminal 480 to receive the high voltage V _DD . The second terminal of the first switch 950a is coupled to the first terminal of the first capacitor 940a and to the second terminal of the second switch 950b. The first terminal of the second switch 950b is connected to the first terminal of the third switch 950c, to the second terminal of the second capacitor 940b, to the second terminal of the third capacitor 940c, and high. it is coupled to voltage _{V DD} / 2 is approximately half the voltage level of the voltage _{V DD.} The second terminal of the third switch 950c is coupled to the second terminal of the first capacitor 940a, to the first terminal of the second capacitor 940b, and to the first terminal of the fourth switch 950d. ing. The second terminal of the fourth switch 950d is coupled to the first terminal of the third capacitor 940c.

  The differential voltage selector 960 connects the second pair of first and second terminals 420c, 420d of the differential input terminal of the single output DDA 720 to (i) the first and second terminals of the third capacitor 940c. Or (ii) each of the second and first terminals of the third capacitor 940c is selectively coupled depending on the output of the single output DDA 720. For example, the differential voltage selector 960 may have a further pair of switches, as shown in FIG.

  FIG. 17 is a circuit diagram of another exemplary embodiment of a differential receiver 970 having a differential output DDA, such as the differential output DDA 770 shown in FIG. Another exemplary embodiment of the offset voltage generator 990 is configured to generate an offset voltage that is applied to the reference voltage input of the differential output DDA 770.

  The offset voltage generator includes first, second and third resistors 1000a to 1000c. Each of resistors 1000a-1000c has first and second terminals. The first terminal of the first resistor 1000a is coupled to the first terminal 430a of the pair of differential output terminals of the differential output DDA770. The second terminal of the first resistor 1000a is coupled to the first terminal of the second resistor 1000b and to the second terminal 420d of the second pair of differential input terminals of the differential output DDA770. ing. The second terminal of the second resistor 1000b is coupled to the first terminal of the third resistor 1000c and to the first terminal 420c of the second pair of differential input terminals of the differential output DDA770. ing. The second terminal of the third resistor 1000c is coupled to the second terminal 430b of the pair of differential output terminals of the differential output DDA770.

  FIG. 18 is configured to provide a reference offset voltage that is applied to the first and second terminals 420c, 420d of the second pair of differential input terminals of the DDA 410 to form a differential receiver. 12 is a circuit diagram of yet another exemplary embodiment of an offset voltage generator 1010. FIG.

The offset voltage generator 1010 includes a center voltage generator 1030 having first, second, third, fourth, fifth and sixth NMOS transistors 1040a to 1040f. Each transistor has a gate, a source and a drain. First, the source of the second, third and fourth NMO transistor 1040a~1040d is to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470. The drains of the first and second NMOS transistors 1040a, 1040b are coupled to the source of the fifth NMOS transistor 1040e. The drains of the third and fourth NMOS transistors 1040c, 1040d are coupled to the source of the sixth NMOS transistor 1040f. The gate of the first NMOS transistor 1040a is coupled to the second terminal 430b of the pair of differential output terminals. The gate of the second NMOS transistor 1040b is coupled to the first terminal 430a of the pair of differential output terminals.

The center voltage generator 1030 further includes first and second PMOS transistors 1050a and 1050b. Each transistor has a gate, a source and a drain. The drain of the fifth NMOS transistor 1040e is connected to the gate of the fifth NMOS transistor 1040e, to the gate of the sixth NMOS transistor 1040f, to the drain of the first PMOS transistor 1050a, and to the first and second PMOS transistors 1050a. 1050b coupled to the gate. The gate of the third NMOS transistor 1040c is coupled to the gate of the fourth NMOS transistor 1040d, to the drain of the sixth NMOS transistor 1040f, and to the drain of the second PMOS transistor 1050b. The sources of the first and second PMOS transistors 1050a, 1050b are coupled to the high voltage terminal 480 to receive the high voltage V _DD . Center voltage _{V CM} of the differential output voltage _{V CP} and _{V CN} are supplied at the drain of the sixth NMOS transistor 1040f.

The offset voltage generator 1010 further includes a first offset voltage circuit 1055 having a PMOS transistor 1060 having a gate, a source, and a drain. First, second and third NMOS transistors 1070a-1070b are also provided, each transistor having a gate, a source and a drain. The source of PMOS transistor 1060 is coupled to high voltage V _DD . The gate of PMOS transistor 1060 is coupled to the gate of second PMOS transistor 1050b of center voltage generator 1030. The drain of the third NMOS transistor 1070c is coupled to the drain of the PMOS transistor 1060, to the gate of the first NMOS transistor 1070a, and to the first terminal 420c of the second pair of differential input terminals of the DDA 410. . The gate of the second NMOS transistor 1070b, at node 645, to receive the center voltage _{V CM,} is coupled to the gate of the fourth NMOS transistor 1040d of the center voltage generator 1030. The gate of the third NMOS transistor 1070c is coupled to the gate of the sixth NMOS transistor 1040f of the center voltage generator 1030.

The offset voltage generator 1010 further includes a second offset voltage circuit 1075 having a PMOS transistor 1080 having a gate, a source, and a drain. The gate of the PMOS transistor 1080 is coupled to the gate of the PMOS transistor 1060 of the first offset voltage circuit 1055 and to the gate of the second PMOS transistor 1050b of the center voltage generator 1030. The source of PMOS transistor 1080 is coupled to high voltage V _DD . First, second and third NMOS transistors 1090a-1090c are also provided, each transistor having a gate, a source and a drain. The drain of the third NMOS transistor 1090c is coupled to the drain of the PMOS transistor 1080, to the gate of the first NMOS transistor 1090a, and to the second terminal 420d of the second pair of differential input terminals of the DDA 410. . The gate of the second NMOS transistor 1090b is coupled to the gate of the second NMOS transistor 1070b of the first offset voltage circuit 1055. The gate of the third NMOS transistor 1090c is coupled to the gate of the third NMOS transistor 1070c of the first offset voltage circuit 1055.

  The first, second, third and fourth NMOS transistors 1040a to 1040d of the center voltage generator 1030 and the second NMOS transistors 1070b and 1090b of the first and second offset voltage circuits 1055 and 1075 are substantially the same. It may have electrical characteristics. The first NMOS transistor 1070a of the first offset voltage circuit 1055 may have a conductivity smaller than that of the second NMOS transistor 1070b. The first NMOS transistor 1090a of the second offset voltage circuit 1075 may have a conductivity that is greater than the conductivity of the second NMO transistor 1090b.

  The fifth and sixth NMOS transistors 1040e and 1040f of the center voltage generator 1030 and the third NMOS transistors 1070c and 1090c of the first and second offset voltage circuits 1055 and 1075 have substantially the same electrical characteristics. May be. The first and second PMOS transistors 1050a and 1050b of the center voltage generator 1030 and the PMOS transistors 1060 and 1080 of the first and second offset voltage circuits 1055 and 1075 may have substantially the same electrical characteristics. .

If offset voltage generators 930, 990, 1010, as represented in the exemplary embodiments of FIGS. 16, 17, and 18, are used, respectively, LVDS receivers 920, 970, respectively described with respect to those figures. _Each output voltage of 1010 (V _{out for} a single output, V _out = V _outP −V _{outN for} a differential output) is the first and second differential input voltages (V _in = V _PP −V _PN ). It is adapted to have a hysteresis voltage V _h for the difference between. The hysteresis voltage V _h is provided at a node between the two terminals 420c and 420d of the offset voltage generators 930, 990, and 1010. Hysteresis voltage _{V h may} be a V _h = V NP _{-V NN.}

FIG. 19 shows that the input voltage difference increases to a higher threshold voltage (V _h ), crosses the higher threshold voltage, returns to the lower threshold voltage (−V _h ), and crosses the lower voltage. FIG. 6 is a graph showing a plot of output voltage (V _out ) as a function of input voltage difference (V _in ).

FIG. 20 is a circuit diagram of a DDA 1100 having a gain modulation input terminal 1110. Modulator 1120 coupled to gain modulation input terminal 1110 can input the modulated signal to DDA 410 to modulate the output signal (V _CP , V _CN ). As shown in the equation (3) or (6), the gain of the DDA 410 is determined by the high voltage V _DD from the power source and the drain-source voltages V _DSP and V _{DSN of the} load current control transistors 550a, 550b, 570a, and 570b. Can be modulated. The drain-source voltages V _DSP and V _DSN of the load current control transistors 550 a, 550 b, 570 a and 570 b can be controlled by the first and second output terminals 500 and 510 of the first bias regulator 490. For example, the modulator 1120 modulates to the second bias output terminal 510 of the first bias regulator 490 shown in FIG. 4 to modulate the output signals (V _CP , V _CN ) at the differential output terminals 430a, 430b. A signal may be input.

FIG. 21 is a circuit diagram of another embodiment of the DDA 1200. In this embodiment, the sources of the first, second, third and fourth current control PMOS transistors 540a to 540d and the sources of the first and second load current control PMOS transistors 550a and 550b receive the high voltage V _DD . The high voltage terminal 480 is coupled to receive. First, second, third and the source of the fourth current control NMOS transistor 560a~560d and the first and second load current control NMOS transistor 570a, source 570b is to receive the low voltage _{V SS,} low voltage Coupled to terminal 470.

The first bias regulator 490 includes first and second resistors 1210a and 1210b. Each of the resistors 1210a and 1210b has a first terminal and a second terminal. A Schmitt inverter 1220 having an input terminal and an output terminal is also provided. The second terminal of the first resistor 1210a is coupled to the second terminal of the second resistor 1210b and to the input terminal of the Schmitt inverter 1220. The output terminal of the Schmitt inverter 1220 is coupled to the first and second output terminals 500, 510 of the first bias regulator 490. The first terminal of the first resistor 1210a is to receive a first input voltage V _PP, is coupled to a first terminal 420a of the first pair of differential input terminals, whereas, the second the first terminal of the resistor 1210b is to receive a second input voltage V _PN, is coupled to the second terminal 420b of the first pair of differential input terminals.

When the first and second pairs of differential input voltages V _PP , V _PN , V _NP , V _NN are higher than the higher threshold voltage of the Schmitt inverter 1220 of the first bias regulator 490, the Schmitt inverter 1220 is low voltage. Is output. As a result, the load current control PMOS transistors 550a and 550b are turned on, and the load current control NMOS transistors 570a and 570b are turned off. When the load current control PMOS transistors 550a and 550b have a conductivity sufficiently higher than the conductivity of the current control NMOS transistors 560a to 560d, the drain-source voltage V _DSP of the load current control PMOS transistors 550a and 550b is relative. Small. Accordingly, since the current flowing through the current control PMOS transistors 540a-540d is sufficiently smaller than the current flowing through the current control NMOS transistors 560a-560d, the current flowing through the current control PMOS transistors 540a-540d is for the purpose of approximate calculation. It can be ignored. The difference between the differential output voltages (V _CP −V _CN ) can be approximated by the above equation (3).

Similarly, when the first and second pairs of differential input voltages V _PP , V _PN , V _NP , V _NN are lower than the lower threshold voltage of the Schmitt inverter 1220 of the first bias regulator 490, the Schmitt inverter 1220. Outputs a high voltage. As a result, the load current control PMOS transistors 550a and 550b are turned off, and the load current control NMOS transistors 570a and 570b are turned on. When the load current control NMOS transistors 570a and 570b have a conductivity sufficiently higher than that of the current control PMOS transistors 540a to 540d, the drain-source voltage V _DSN of the load current control NMOS transistors 570a and 570b is relative. Small. Accordingly, since the current flowing through the current control NMOS transistors 560a to 560d is sufficiently smaller than the current flowing through the current control PMOS transistors 540a to 540d, the current flowing through the current control NMOS transistors 560a to 560d is used for the purpose of approximate calculation. It can be ignored. The difference between the differential output voltages (V _CP −V _CN ) can be approximated by equation (6) above, which indicates that the DDA 1200 operates as desired.

  The DDA 1200 of FIG. 21 may be advantageous in certain applications because it occupies a smaller physical area, such as a smaller area of the silicon substrate, than other differential differential amplifiers. For example, the DDA 1200 of FIG. 21 is smaller than the DDA 410 of FIG. 4 because the first and second resistors 1210a, 1210b and the Schmitt inverter 1220 of the DDA 1200 are replaced with the first bias regulator 490 and switching voltage source of the DDA 410. Can occupy.

FIG. 22 is a circuit diagram of another embodiment of the DDA 1300. In this embodiment, the sources of the first, second, third and fourth current control PMOS transistors 540a to 540d and the sources of the first and second load current control PMOS transistors 550a and 550b receive the high voltage V _DD . The high voltage terminal 480 is coupled to receive. First, second, third and the source of the fourth current control NMOS transistor 560a~560d and the first and second load current control NMOS transistor 570a, source 570b is to receive the low voltage _{V SS,} low voltage Coupled to terminal 470.

The source of PMOS transistor 520 of first bias regulator 490 is coupled to high voltage terminal 480 to receive high voltage V _DD . The drain and gate of the PMOS transistor 520 are coupled to the first output terminal 500 of the first bias regulator 490. The source of the NMOS transistor 530 of the first bias regulator 490, to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470. The drain and gate of NMOS transistor 530 are coupled to the drain of PMOS transistor 520 and to the second output terminal 510 of first bias regulator 490. The gates of the first and second load current control PMOS transistors 550a, 550b of the DDA 1300 are coupled to the first output terminal 500 of the first bias regulator 490, and the first and second load current control NMOS transistors. The gates of 570 a and 570 b are coupled to the second output terminal 510 of the first bias regulator 490.

In operation, the first and second load current control PMOS transistors 550a, 550b and the first and second load current control NMOS transistors 570a, 570b supply a sufficiently constant current for a long time. The current control PMOS transistors 540a to 540d and the current control NMOS transistors 560a to 560d are turned on almost simultaneously. If the drain-source voltage V _{DSP of the} load current control PMOS transistors 550a, 550b and the drain-source voltage V _{DSN of the} load current control NMOS transistors 570a, 570b are selected to be small,
(8) V _CM = V _thN + Δ
(9) V _DD = V _thN + | V _thP | + Δ
The center voltage V _CM (at node 645) of the differential output voltages V _CP , V _CN reaches the threshold voltage V _thN of the voltage controlled NMOS transistors 620a, 620b and the high voltage V _DD is The sum (V _thN + | V _thP |) is reached. Note that Δ is a relatively small value.

When the first and second pairs of differential input voltages V _PP , V _PN , V _NP , V _NN are higher than the center voltage V _CM (at node 645) of differential output voltages V _CP , V _CN , current control PMOS Transistors 540a-540d are turned off, and current control NMOS transistors 560a-560d operate in a tripolar region. Therefore, the difference between the differential output voltages (V _CP −V _CN ) is given by Equation 10.

(10) V _CP −V _CN = R · G ₁ · V _DSN · [(V _PP −V _PN ) − (V _NP −V _NN )]
When the first and second pairs of differential input voltages V _PP , V _PN , V _NP , V _NN are lower than the center voltage V _CM (at node 645) of differential output voltages V _CP , V _CN , current control NMOS Transistors 560a-560d are turned off, and current control PMOS transistors 540a-540d operate in the tripolar region. Therefore, the difference (V _CP −V _CN ) between the differential output voltages is given by Equation 11.

(11) V _CP −V _CN = R · G ₂ · V _DSP · [(V _PP −V _PN ) − (V _NP −V _NN )]
Accordingly, DDA 1300 operates as desired.

If the second pair of differential inputs V _NP , V _NN is constant near the center voltage V _CM , the third and fourth current control PMOS transistors 540c, 540d and the third and fourth current control NMOS Transistors 560c and 560d are turned on almost simultaneously and operate in the tripolar region. Since the first and second load current control PMOS transistors 550a and 550b and the first and second load current control NMOS transistors 570a and 570b are turned on substantially simultaneously, the first of the differential inputs V _PP and V _PN The pair can vary from a value close to V _SS to a value close to V _DD , while the second pair of differential inputs V _NP , V _NN is constant near the center voltage V _CM . Without a voltage switching power supply such as the voltage switching power supply 440 of FIG. 4 or a Schmitt inverter such as the Schmitt inverter 1220 of FIG. 21, there is no transition region between the two threshold voltages, and the operation of the DDA 1300 is Continue over a sufficiently wide common mode input range.

FIG. 23 is a circuit diagram of another embodiment of the DDA 1400. In this embodiment, the sources of the first, second, third and fourth current control PMOS transistors 540a to 540d and the sources of the first and second load current control PMOS transistors 550a and 550b receive the high voltage V _DD . The high voltage terminal 480 is coupled to receive. First, second, third and the source of the fourth current control NMOS transistor 560a~560d and the first and second load current control NMOS transistor 570a, source 570b is to receive the low voltage _{V SS,} low voltage Coupled to terminal 470.

  The first bias regulator 490 does not include any individual electronic components. Rather, the first bias regulator 490 in this embodiment is coupled to the first output terminal 500 of the first bias regulator 490 to the second output terminal 510 of the first bias regulator 490 and the second bias. A coupling to the first output terminal 635a of the regulator 630 is provided. Accordingly, the gate of the first load current control PMOS transistor 550a and the gate of the first load current control NMOS transistor 570a are coupled to the first output terminal 635a of the second bias regulator 630. Further, the gate of the second load current control PMOS transistor 550 b and the gate of the second load current control NMOS transistor 570 b are coupled to the second output terminal 635 b of the second bias regulator 630.

In operation, first, second, third and fourth current control PMOS transistors 540a-540c, first, second, third and fourth current control NMO transistors 560a-560d, first and second loads The current control PMOS transistors 550a and 550b and the first and second load current control NMOS transistors 570a and 570b are turned on almost at the same time as the transistors in the DDA 1300 of FIG. The drain-source voltage V _DSP of the first and second load current control PMOS transistors 550a, 550b and the drain-source voltage V _{DSN of} the first and second load current control NMOS transistors 570a, 570b are reduced. If selected, Equations 12 and 13,
(12) V _CM = V _thN + Δ
(13) V _DD = V _thN + V _thP + Δ
, The center voltage V _CM (at node 645) of the differential output voltages V _CP , V _CN is approximately close to the threshold voltage V _thN , and the high voltage V _DD is the threshold voltage V _thN , | V _thP | Nearly the sum of

When the first pair of differential input voltages V _PP and V _PN is higher than the center voltage V _CM , the first and second current control NMOS transistors 560a and 560b operate in the tripolar region, while the first The second current control PMOS transistors 540a and 540b are turned off. When the first pair of differential input voltages V _PP and V _PN is lower than the center voltage V _CM , the first and second current control PMOS transistors 540a and 540b operate in the tripolar region, while the first pair The second current control NMOS transistors 560a and 560b are turned off.

When the second pair of differential input voltages V _NP and V _NN is close to the center voltage V _CM , the third and fourth current control PMOS transistors 540c and 540d and the third and fourth current control NMOS transistors 560c and 560d Is turned on and operates in the tripolar region.

First and second output terminals 635a of the second bias regulator 630, the voltage of 635b, as shown in FIG. 23, when about the same as the center voltage _{V CM} at node 645, the first and second load The currents flowing through the current control PMOS transistors 550a and 550b have substantially the same magnitude, and the currents flowing through the first and second load current control NMOS transistors 570a and 570b have substantially the same magnitude. Under such circumstances, the DDA 1400 shown in FIG. 23 operates similar to the DDA 1300 shown in FIG.

However, when the second bias regulator 630 of FIG. 8 is used in the DDA 1400 of FIG. 23, the voltage of the first output terminal 635a and the voltage of the second output terminal 635b of the second bias regulator 630 are different. . This voltage difference is the difference between the current flowing through the first load current control NMOS transistor 570a and the current flowing through the second load current control NMOS transistor 570b, as well as the current flowing through the first load current control PMOS transistor 550a. And the current flowing through the second load current control PMOS transistor 550b, such a difference provides positive feedback to the differential output voltages V _CP , V _CN . Under such circumstances, the DDA 1400 operates as a differential differential comparator while increasing the gain.

The use of voltage control PMO transistor circuits 610a, 610b and voltage control NMO transistor circuits 620a, 620b, and load current control PMOS transistors 550a, 550b and load current control NMOS transistors 570a, 570b allows the first bias regulator 630 to and second output terminals 635a, a common mode voltage of 635b results in a negative feedback to the center voltage _{V CM,} while the first and second output terminals 635a of the second bias regulator 630, between 635b The positive differential voltage provides positive feedback to the differential output voltages V _CP and V _CN . Therefore, the DDA 1400 may have a more stable center voltage and a larger gain than the differential differential comparator.

  Further, since the first bias regulator 490 of the DDA 1400 of FIG. 23 does not include any electronic components, the DDA 1400 can be manufactured to be advantageously small. For example, the DDA 1400 can be formed on a desirably small area of silicon.

FIG. 24 is a circuit diagram of another embodiment of the DDA 1500. In this embodiment, the sources of the first, second, third and fourth current control PMOS transistors 540a to 540d and the sources of the first and second load current control PMOS transistors 550a and 550b receive the high voltage V _DD . The high voltage terminal 480 is coupled to receive. First, second, third and the source of the fourth current control NMOS transistor 560a~560d and the first and second load current control NMOS transistor 570a, source 570b is to receive the low voltage _{V SS,} low voltage Coupled to terminal 470.

The source of PMOS transistor 520 of first bias regulator 490 is coupled to high voltage terminal 480 to receive high voltage V _DD . The drain and gate of the PMOS transistor 520 are coupled to the first output terminal 500 of the first bias regulator 490. The source of the NMOS transistor 530 of the first bias regulator 490, to receive the low voltage _{V SS,} is coupled to the low voltage terminal 470. The drain and gate of NMOS transistor 530 are coupled to second output terminal 510 of first bias regulator 490. The drains of PMOS transistor 520 and NMOS transistor 530 are coupled to resistor 1510. The first output terminal 500 of the first bias regulator 490 is coupled to the gate terminals of the first and second voltage control PMOS transistor circuits 610a, 610b, and the second output terminal of the first bias regulator 490. 510 is coupled to the gate terminals of the first and second voltage controlled NMOS transistor circuits 620a, 620b.

  The gates of the first load current control PMOS transistor 550a and the first load current control NMOS transistor 570a of the DDA 1500 are coupled to the first output terminal 635a of the second bias regulator 630. The gates of the second load current control PMOS transistor 550b and the second load current control NMOS transistor 570b are coupled to the second output terminal 635b of the second bias regulator 630.

In operation, the drain-source voltage V _{DSP of the} load current control PMOS transistors 550 a, 550 b and the drain-source voltage V _DSN of the load current control NMOS transistors 570 a, 570 b are the first and second voltages of the first bias regulator 490. The center voltage V _CM (at node 645) of the differential output voltages V _CP , V _CN is kept at approximately V _DD / 2, if selected to be reduced by selecting the output terminal voltage of The first and second load current control PMOS transistors 550a and 550b and the first and second load current control NMOS transistors 570a and 570b are turned off to supply a sufficiently constant current for a long time. The current control PMOS transistors 540a to 540d and the current control NMOS transistors 560a to 560d are turned on almost simultaneously and operate in a tripolar region.

Since the voltages at the gate terminals of the voltage control PMOS transistor circuits 610a and 610b and the gate terminals of the voltage control NMOS transistor circuits 620a and 620b are kept sufficiently constant over a wide range of V _DD , the current control PMOS transistors 540a to 540d and Current control NMOS transistors 560a-560d operate in a tripolar region over a wide range of V _DD .

  FIG. 25 is a circuit diagram of another embodiment of the DDA 1600. Compared to the DDA 1500 in FIG. 24, the first bias regulator 490 of the DDA 1600 is the first bias regulator 490 shown in FIG. The second bias regulator 630 is the second bias regulator 630 of FIG. 7 so as to have a single output. The lack of resistors in the DDA 1500 circuit allows for easier implementation using standard logic processes.

  FIG. 26 is a circuit diagram of still another embodiment of the DDA 1700. Compared to the DDA 1600 of FIG. 25, the voltage controlled PMOS transistor circuits 610a, 610b and the voltage controlled NMOS transistor circuits 620a, 620b, respectively, have three PMOS transistors (shown as PMOS transistors 610a1-610a3, 610b1-610b3) and , Three NMOS transistors (shown as NMOS transistors 620a1-620a3, 620b1-620b3). The sources of the first PMOS transistors 610a1, 610b1 of the first and second voltage control PMOS transistor circuits 610a, 610b are coupled to the drains of the first and second current control PMOS transistors 540a, 540b, respectively. The sources of the second PMOS transistors 610a2, 610b2 of the first and second voltage control PMOS transistor circuits 610a, 610b are coupled to the drains of the fourth and third current control PMOS transistors 540d, 540c, respectively. The sources of the third PMOS transistors 610a3, 610b3 of the first and second voltage control PMOS transistor circuits 610a, 610b are coupled to the drains of the first and second load current control PMOS transistors 550a, 550b, respectively. .

  The sources of the first NMOS transistors 620a1, 620b1 of the first and second voltage control NMOS transistor circuits 620a, 620b are coupled to the drains of the first and second current control NMOS transistors 560a, 560b, respectively. The sources of the second NMOS transistors 620a2, 620b2 of the first and second voltage control NMOS transistor circuits 620a, 620b are coupled to the drains of the fourth and third current control NMOS transistors 560d, 560c, respectively. The sources of the third PMOS transistors 620a3, 620b3 of the first and second voltage control NMOS transistor circuits 620a, 620b are coupled to the drains of the first and second load current control NMOS transistors 570a, 570b, respectively. . The first and second load current control PMOS transistors 550a and 550b and the current control PMOS transistors 540a to 540d are separated by the PMOS transistors 610a1 to 610a3m 610b1 to 610b3 of the first and second voltage control PMOS transistor circuits 610a and 610b. Thus, the DDA 1700 can be more stable when the differential input changes.

  While the embodiments making up the present invention have been described in considerable detail with reference to those embodiments, other variations are possible. For example, the individual electronic components of the DDA 410 may have other electronic structures equivalent to those listed as examples of specific structures in the present application. Furthermore, terms that are relative or context dependent, such as “first”, “second”, “third”, and “fourth” are used with respect to the exemplary embodiments and are interchangeable. Accordingly, the scope of the appended claims should not be limited to the description of the embodiments contained herein.

1 is a circuit diagram of one embodiment of a conventional low voltage differential signaling (LVDS) receiver. FIG. FIG. 2 is a circuit diagram of an embodiment of a conventional differential differential amplifier (DDA) in the LVDS receiver of FIG. 1. It is a circuit diagram of one Example of the conventional LVDS which is a differential operational amplifier. 1 is a circuit diagram of one embodiment of a differential differential amplifier (DDA) according to the present invention. FIG. FIG. 6 is a schematic circuit diagram representing a differential differential amplifier. FIG. 5 is a circuit diagram of an example of the second bias control of FIG. 4. FIG. 6 is a circuit diagram of another embodiment of the second bias control of FIG. 4. FIG. 10 is a circuit diagram of still another embodiment of the second bias control of FIG. 4. FIG. 5 is a circuit diagram of an embodiment of the voltage source control circuit of FIG. 4. 1 is a circuit diagram of one embodiment of a single output DDA having a DDA and a single output operational amplifier (op amp). FIG. FIG. 11 is a circuit diagram of an embodiment of the single output operational amplifier of FIG. 10. FIG. 3 is a circuit diagram of an embodiment of a differential output DDA having a DDA and a differential output operational amplifier. FIG. 13 is a circuit diagram of an example of the differential output operational amplifier of FIG. 12. FIG. 3 is a circuit diagram of an embodiment of a differential differential comparator having a DDA and a differential output comparator. FIG. 15 is a circuit diagram of an embodiment of the differential output comparator of FIG. 14. FIG. 3 is a circuit diagram of an embodiment of an LVDS receiver with a single output DDA. FIG. 3 is a circuit diagram of an embodiment of an LVDS receiver having a differential output DDA. FIG. 6 is a circuit diagram of one embodiment of a small offset voltage circuit configured to generate a pair of offset voltages. 18 is a graph showing a plot of the output voltage of the LVDS receiver of FIGS. 16 and 17 as a function of input voltage. FIG. 2 is a circuit diagram of a DDA having a gain modulation input and a modulation device coupled to the gain modulation input of the DDA. It is a circuit diagram of other examples of DDA. FIG. 6 is a circuit diagram of still another embodiment of the DDA. FIG. 6 is a circuit diagram of still another embodiment of the DDA. FIG. 6 is a circuit diagram of still another embodiment of the DDA. FIG. 6 is a circuit diagram of still another embodiment of the DDA. FIG. 6 is a circuit diagram of still another embodiment of the DDA.

Explanation of symbols

110, 920, 970, 1010 LVDS receiver 410, 1100-1700 DDA
420a, b, c, d Differential input terminal 430a, b Differential output terminal 440 Switching voltage source 450a, b Low power output terminal 460a, b High power output terminal 470 Low voltage terminal 480 High voltage terminal 490, 630 Bias regulator 540a ˜540d Current control PMOS transistor 550a, b Load current control PMOS transistor 560a˜560d Current control NMOS transistor 570a, b, 720 Load current control NMOS transistor 610a, b Voltage control PMOS transistor circuit 620a, b Voltage control NMOS transistor circuit 640a, b Resistors 700a, b,
710 Inverter 720 Single output DDA
730 Single Output Operational Amplifier 770 Differential Output DDA
775 differential output operational amplifier 820 differential output differential differential comparator 830 differential output comparator 920, 970 differential output receiver 930, 990, 1010 offset voltage generator 1030 center voltage generator V _DD , V _SS voltage V _PP , V _PN input voltage V _NP , V _NN reference voltage V _CP , V _CN differential output voltage V _CM center voltage V _DNP , V _DNN drain-source voltage V _thP , V _thN threshold voltage

Claims (17)

One or more of the first and second low power output terminals and one or more of the first and second high power output terminals are coupled to the low voltage terminal and the high voltage terminal, respectively. The first and second low power supply output terminals and the first and second high power supply output terminals,
A first bias regulator having a first output terminal for supplying a first bias voltage and a second output terminal for supplying a second bias voltage;
A second bias regulator having first and second output terminals;
A first having a source coupled to each other and to the second high power output terminal, a gate coupled to the first and second terminals of the first pair of differential input terminals, and a drain, respectively. First and second current control PMOS transistors and a source coupled to each other and to the second high power supply output terminal, and a first and second terminals of a second pair of differential input terminals, respectively. Third and fourth current control PMOS transistors each having a gate and a drain,
First and second load current control PMOS each having a source coupled to the first high power supply output terminal, a gate coupled to the first output terminal of the first bias regulator, and a drain. A transistor,
A first having a source coupled to each other and to the second low power output terminal, a gate coupled to the first and second terminals of the first pair of differential input terminals, and a drain, respectively. First and second current control NMOS transistors and a source coupled to each other and to the second low power supply output terminal, and to a first and second terminals of a second pair of differential input terminals, respectively. Third and fourth current control NMOS transistors each having a gate and a drain;
First and second load current control NMOS each having a source coupled to the first low power supply output terminal, a gate coupled to a second output terminal of the first bias regulator, and a drain. A transistor,
At least one source terminal coupled to the drains of the first and fourth current control PMOS transistors and to the drain of the first load current control PMOS transistor and to the first output terminal of the second bias regulator. A first voltage controlled PMOS transistor circuit having a coupled gate terminal and a drain terminal; to the drains of the second and third current controlled PMOS transistors; and to the drain of the second load current controlled PMOS transistor A second voltage controlled PMOS transistor circuit having at least one source terminal coupled, a gate terminal coupled to a second output terminal of the second bias regulator, and a drain terminal;
At least one source terminal coupled to the drains of the first and fourth current control NMOS transistors and to the drain of the first load current control NMOS transistor, and to the first output terminal of the second bias regulator. A first voltage controlled NMOS transistor circuit having a coupled gate terminal and a drain terminal; to the drains of the second and third current controlled NMOS transistors; and to the drain of the second load current controlled NMOS transistor A second voltage controlled NMOS transistor circuit having at least one source terminal coupled, a gate terminal coupled to a second output terminal of the second bias regulator, and a drain terminal;
Have
The drain terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit are coupled to a first terminal of a pair of differential output terminals, and the first voltage control PMOS transistor circuit and A drain terminal of the first voltage controlled NMOS transistor circuit is coupled to a second terminal of the pair of differential output terminals;
A differential differential amplifier characterized by that.   Either (i) the first low power output terminal or the second high power output terminal, or (ii) either the second low power output terminal or the first high power output terminal. The differential differential amplifier of claim 1, further comprising a switching voltage source capable of selectively coupling to the low voltage terminal and the high voltage terminal. The switching voltage source is:
A first switching NMOS transistor having a drain coupled to the first low power output terminal, a source coupled to the low voltage terminal, and a gate; and coupled to the second low power output terminal A second switching NMOS transistor having a drain, a source coupled to the low voltage terminal, and a gate;
A first switching PMOS transistor having a drain coupled to the first high power output terminal; a source coupled to the high voltage terminal; and a gate; and coupled to the second high power output terminal. A second switching PMOS transistor having a drain, a source coupled to the high voltage terminal, and a gate;
A second inverter having an output terminal and an input terminal coupled to a second terminal of the first pair of differential input terminals; and to the output terminal of a second inverter and to the first switching NMOS A first inverter having a transistor and an output terminal coupled to the first switching PMOS transistor; and an input terminal coupled to a first terminal of the first pair of the differential input terminals;
A third inverter having an input terminal coupled to the output terminals of the first and second inverters, and an output terminal coupled to the gates of the second switching NMOS transistor and the second switching PMOS transistor; ,
Load current control having a source for coupling to the high voltage terminal, a drain coupled to the output terminals of the first and second inverters, and a gate coupled to the output terminal of the third inverter. A PMOS transistor;
Load current control having a source for coupling to the low voltage terminal, a drain coupled to the output terminals of the first and second inverters, and a gate coupled to the output terminal of the third inverter. An NMOS transistor;
The differential differential amplifier according to claim 2, further comprising: The sources of the first, second, third and fourth current control PMOS transistors and the sources of the first and second load current control PMOS transistors are coupled to the high voltage terminal;
The sources of the first, second, third and fourth current control NMOS transistors and the sources of the first and second load current control NMOS transistors are coupled to the low voltage terminal;
The differential differential amplifier according to claim 1. The second bias regulator includes:
A first terminal coupled to a second terminal of the pair of differential output terminals; and a first resistor having a second terminal;
A first terminal coupled to a second terminal of the first resistor and to the first and second output terminals of the second bias regulator; and a first terminal of the pair of differential output terminals A second resistor having a second terminal coupled to the
The differential differential amplifier according to claim 1, comprising:   5. The differential differential amplifier according to claim 4, wherein the first and second resistors of the second bias regulator have substantially the same electrical resistance. The second bias regulator includes:
First, second, third, fourth, fifth and sixth NMOS transistors each having a gate, a source and a drain;
Sources of the first, second, third and fourth NMOS transistors for coupling to the low voltage terminal;
The drains of the first and second NMOS transistors coupled to the source of the fifth NMOS transistor;
Drains of the third and fourth NMOS transistors coupled to a source of the sixth NMOS transistor;
A gate of the first NMOS transistor coupled to a second terminal of the pair of differential output terminals;
A gate of the second NMOS transistor coupled to a first terminal of the pair of differential output terminals;
First and second PMOS transistors each having a gate, a source and a drain;
The fifth NMOS coupled to the gate of the fifth NMOS transistor, to the gate of the sixth NMOS transistor, to the drain of the first PMOS transistor, and to the gates of the first and second PMOS transistors. The drain of the transistor;
A drain of the sixth NMOS transistor coupled to a drain of the second PMOS transistor;
A gate of a third NMOS transistor coupled to the gate of the fourth NMOS transistor, to the drain of the sixth NMOS transistor, and to the first and second output terminals of the second bias regulator;
Sources of the first and second PMOS transistors for coupling to the high voltage terminal;
The differential differential amplifier according to claim 1, comprising: Gate terminals of the first and second voltage control NMOS transistor circuits and the first and second voltage control PMOS transistor circuits are coupled to a second terminal of the pair of differential output terminals;
The differential differential amplifier according to claim 1. The second bias regulator includes:
Having first, second and third resistors each having a first terminal and a second terminal;
The second terminal of the first resistor is coupled to the first terminal of the second resistor and to the gate terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit. And
The second terminal of the second resistor is coupled to the first terminal of the third resistor and to the gate terminals of the first voltage control PMOS transistor circuit and the first voltage control NMOS transistor circuit. And
A first terminal of the first resistor is coupled to a second terminal of the pair of differential output terminals;
A second terminal of the third resistor is coupled to a first terminal of the pair of differential output terminals;
The differential differential amplifier according to claim 1. The first, second, third and fourth current control PMOS transistors have substantially the same electrical characteristics;
The first and second load current control PMOS transistors have substantially the same electrical characteristics;
The first and second voltage controlled PMOS transistor circuits have substantially the same electrical characteristics;
The first and second load current control PMOS transistors and the first and second voltage control PMOS transistor circuits have greater conductivity than the first, second, third and fourth current control PMOS transistors. Have
The first, second, third and fourth current control NMOS transistors have substantially the same electrical characteristics;
The first and second load current control NMOS transistors have substantially the same electrical characteristics;
The first and second voltage controlled NMOS transistor circuits have substantially the same electrical characteristics;
The first and second load current control NMOS transistors and the first and second voltage control NMOS transistor circuits have greater conductivity than the first, second, third and fourth current control NMOS transistors. Have
The differential differential amplifier according to claim 1. The first bias regulator includes:
A PMOS transistor having a source for coupling to the high voltage terminal and a drain and gate coupled to a first output terminal of the first bias regulator;
An NMOS transistor having a source for coupling to the low voltage terminal, and a drain and gate coupled to a drain of the PMOS transistor and a second output terminal of the first bias regulator;
The differential differential amplifier according to claim 1, comprising: The first bias regulator includes:
A Schmitt inverter having an input terminal and an output terminal;
A first resistor and a second resistor each having a first terminal and a second terminal;
A second terminal of the first resistor is coupled to a second output terminal of the second resistor and to an input terminal of the Schmitt inverter;
An output terminal of the Schmitt inverter is coupled to first and second output terminals of the first bias regulator;
A first terminal of the first resistor is coupled to a first pair of first terminals of the differential input terminal;
A first terminal of the second resistor is coupled to a second pair of second terminals of the differential input terminal;
The differential differential amplifier according to claim 1. The first bias regulator includes:
A PMOS transistor and an NMOS transistor each having a gate, a source and a drain;
A resistor having a first terminal and a second terminal;
The source of the PMOS transistor is coupled to the high voltage terminal;
The drain of the PMOS transistor is coupled to the gate of the PMOS transistor and to the first output terminal of the first bias regulator;
A source of the NMOS transistor is coupled to the low voltage terminal;
The drain of the NMOS transistor is coupled to the gate of the NMOS transistor and to the second output terminal of the first bias regulator;
The first and second terminals of the resistor are coupled to first and second output terminals of the first bias regulator, respectively.
The differential differential amplifier according to claim 1. Each of the first and second voltage control PMOS transistor circuits includes a plurality of PMOS transistors,
At least one source terminal of each of the first and second voltage controlled PMOS transistor circuits has a plurality of source terminals;
The gate of each PMOS transistor of the first and second voltage controlled PMOS transistor circuits is coupled to the gate terminal of the PMOS transistor circuit, the drain of the PMOS transistor is coupled to the drain terminal of the PMOS transistor circuit, The sources of the PMOS transistors are respectively coupled to the source terminals of the PMOS transistor circuit;
The first and second voltage control NMOS transistor circuits each have a plurality of NMOS transistors,
At least one source terminal of each of the first and second voltage controlled NMOS transistor circuits has a plurality of source terminals;
The gate of each MMOS transistor of the first and second voltage controlled NMOS transistor circuits is coupled to the gate terminal of the NMOS transistor circuit, the drain of the NMOS transistor is coupled to the drain terminal of the NMOS transistor circuit, The sources of the NMOS transistors are respectively coupled to the source terminals of the NMOS transistor circuits;
The differential differential amplifier according to claim 1. The sources of the first, second, third and fourth current control PMOS transistors and the sources of the first and second load current control PMOS transistors are coupled to the high voltage terminal;
The sources of the first, second, third and fourth current control NMOS transistors and the sources of the first and second load current control NMOS transistors are coupled to the low voltage terminal;
Gates of the first and second load current control PMOS transistors are coupled to a first output terminal of the first bias regulator;
Gates of the first and second load current control NMOS transistors are coupled to a second output terminal of the first bias regulator;
The differential differential amplifier according to claim 1. The sources of the first, second, third and fourth current control PMOS transistors and the sources of the first and second load current control PMOS transistors are coupled to the high voltage terminal;
The sources of the first, second, third and fourth current control NMOS transistors and the sources of the first and second load current control NMOS transistors are coupled to the low voltage terminal;
Gates of the first and second load current control PMOS transistors are respectively coupled to first and second output terminals of the second bias regulator;
The gates of the first and second load current control NMOS transistors are coupled to first and second output terminals of the second bias regulator, respectively.
The differential differential amplifier according to claim 1. One or more of the first and second low power output terminals and one or more of the first and second high power output terminals are coupled to the low voltage terminal and the high voltage terminal, respectively. The first and second low power supply output terminals and the first and second high power supply output terminals,
A first bias regulator having a first output terminal for supplying a first bias voltage and a second output terminal for supplying a second bias voltage;
A second bias regulator having first and second output terminals;
A first having a source coupled to each other and to the second high power output terminal, a gate coupled to the first and second terminals of the first pair of differential input terminals, and a drain, respectively. First and second current control PMOS transistors and a source coupled to each other and to the second high power supply output terminal, and a first and second terminals of a second pair of differential input terminals, respectively. Third and fourth current control PMOS transistors each having a gate and a drain,
First and second each having a source coupled to the first high power supply output terminal, a gate coupled to the first and second output terminals of the second bias regulator, and a drain, respectively. A load current control PMOS transistor;
A first having a source coupled to each other and to the second low power output terminal, a gate coupled to the first and second terminals of the first pair of differential input terminals, and a drain, respectively. First and second current control NMOS transistors and a source coupled to each other and to the second low power supply output terminal, and to a first and second terminals of a second pair of differential input terminals, respectively. Third and fourth current control NMOS transistors each having a gate and a drain;
First and second each having a source coupled to the first low power supply output terminal, a gate coupled to the first and second output terminals of the second bias regulator, and a drain, respectively. A load current control NMOS transistor;
At least one source terminal coupled to the drains of the first and fourth current control PMOS transistors and to the drain of the first load current control PMOS transistor, and to the first output terminal of the first bias regulator. A first voltage controlled PMOS transistor circuit having a coupled gate terminal and a drain terminal; to the drains of the second and third current controlled PMOS transistors; and to the drain of the second load current controlled PMOS transistor A second voltage controlled PMOS transistor circuit having at least one source terminal coupled, a gate terminal coupled to a first output terminal of the first bias regulator, and a drain terminal;
At least one source terminal coupled to the drains of the first and fourth current control NMOS transistors and to the drain of the first load current control NMOS transistor, and to the second output terminal of the first bias regulator. A first voltage controlled NMOS transistor circuit having a coupled gate terminal and a drain terminal; to the drains of the second and third current controlled NMOS transistors; and to the drain of the second load current controlled NMOS transistor A second voltage controlled NMOS transistor circuit having at least one source terminal coupled, a gate terminal coupled to a second output terminal of the first bias regulator, and a drain terminal;
Have
The drain terminals of the second voltage control PMOS transistor circuit and the second voltage control NMOS transistor circuit are coupled to a first terminal of a pair of differential output terminals, and the first voltage control PMOS transistor circuit and A drain terminal of the first voltage controlled NMOS transistor circuit is coupled to a second terminal of the pair of differential output terminals;
A differential differential amplifier characterized by that.

Images