JP4311689B2 - Solid-state imaging device and electronic apparatus provided with the same - Google Patents

Solid-state imaging device and electronic apparatus provided with the same Download PDF

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JP4311689B2
JP4311689B2 JP2006332731A JP2006332731A JP4311689B2 JP 4311689 B2 JP4311689 B2 JP 4311689B2 JP 2006332731 A JP2006332731 A JP 2006332731A JP 2006332731 A JP2006332731 A JP 2006332731A JP 4311689 B2 JP4311689 B2 JP 4311689B2
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敏行 大嶋
信行 福場
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
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Description

本発明は、固体撮像装置、特に出力部の最終段がソースフォロワ回路からなる固体撮像素子を有する固体撮像装置及びこれを備える電子機器に関する。   The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a solid-state imaging device whose final stage of an output unit is a source follower circuit, and an electronic apparatus including the same.

一般的に固体撮像素子の出力部は、ソースフォロワ回路からなり、当該ソースフォロワ回路の負荷部とともに一つの半導体パッケージ内に設けられている。そして、従来の一般的な固体撮像素子では、固定撮像素子がどんな状態であっても、出力部であるソースフォロワ回路の負荷部がソースフォロワ回路の駆動トランジスタに常に電流を供給しているため、固体撮像素子が発熱し、S/Nの悪化及び暗時出力ムラ、白欠陥が発生していた。
特開２００２−３３５４４９号公報 特開平４−２９１５８１号公報 In general, the output unit of the solid-state imaging device is composed of a source follower circuit, and is provided in one semiconductor package together with the load unit of the source follower circuit. And in the conventional general solid-state image sensor, the load part of the source follower circuit that is the output part always supplies current to the drive transistor of the source follower circuit, regardless of the state of the fixed image sensor. The solid-state image sensor generated heat, resulting in S / N deterioration, dark output unevenness, and white defects.
JP 2002-335449 A Japanese Patent Laid-Open No. 4-291582

したがって、発熱による性能悪化の抑制が性能向上のために必要となっている。また、省エネルギー化の観点から消費電流の低減も必要となってきている。   Therefore, suppression of performance deterioration due to heat generation is necessary for performance improvement. In addition, it is necessary to reduce current consumption from the viewpoint of energy saving.

特許文献１に記載された固体撮像素子は、駆動ＭＯＳトランジスタＤＭ１〜ＤＭ３及び負荷トランジスタＬＭ１〜ＬＭ３からなる３段ソースフォロワ回路の出力部を固体撮像素子に内蔵し、出力部を流れる電流を制御する電流制御用ＭＯＳトランジスタＴｒ１を負荷ＭＯＳトランジスタＬＭ１〜ＬＭ３のソース側に設けており、電流制御用ＭＯＳトランジスタＴｒ１のゲートに垂直転送クロックパルスＶφ2（固体撮像素子の信号蓄積期間でＬｏｗバイアス、固体撮像素子の信号出力期間でＨｉｇｈバイアスとなるパルス）で代用した制御クロックパルスを印加することで、固体撮像素子の信号蓄積期間中に出力部に流れる電流を抑制している（図２参照）。しかしながら、特許文献１に記載された固体撮像素子は、出力部を固体撮像素子に内蔵しているため、発熱による性能悪化を抑制することができない。なお、特許文献１に記載された固体撮像素子は、出力部を流れる電流を制御する電流制御手段（電流制御用ＭＯＳトランジスタＴｒ１）を固体撮像素子内部に設けることにより、簡易な構成を実現していることを特徴としている（特許文献１の段落０００９及び００１２参照）。 The solid-state imaging device described in Patent Document 1 incorporates an output unit of a three-stage source follower circuit including driving MOS transistors DM1 to DM3 and load transistors LM1 to LM3 in a solid-state imaging device, and controls a current flowing through the output unit. A current control MOS transistor Tr1 is provided on the source side of the load MOS transistors LM1 to LM3, and a vertical transfer clock pulse Vφ 2 (Low bias in the signal accumulation period of the solid-state imaging device, solid-state imaging is applied to the gate of the current control MOS transistor Tr1. By applying a control clock pulse substituted with a pulse that becomes a high bias during the signal output period of the element, the current flowing through the output unit during the signal accumulation period of the solid-state imaging element is suppressed (see FIG. 2). However, since the solid-state image sensor described in Patent Document 1 has an output unit built in the solid-state image sensor, performance deterioration due to heat generation cannot be suppressed. Note that the solid-state imaging device described in Patent Document 1 realizes a simple configuration by providing current control means (current control MOS transistor Tr1) for controlling the current flowing through the output unit inside the solid-state imaging device. (See paragraphs 0009 and 0012 of Patent Document 1).

特許文献２に記載された固体撮像素子は、出力部の最終段がソースフォロワ回路からなり、出力部の最終段の定電流源部（負荷トランジスタＱｄ、抵抗Ｒａ、及び定電圧手段Ｅからなる回路）を固体撮像素子外部に設けているので、固体撮像素子の信号蓄積期間及び信号出力期間の発熱による性能悪化を抑制することができる（図３参照）。しかしながら、出力部であるソースフォロワ回路の定電流源となる負荷トランジスタＱｂ、Ｑｄがそれぞれソースフォロワ回路の駆動トランジスタＱａ、Ｑｃに常に電流を供給しているため、消費電流の低減を図ることができなかった。   In the solid-state imaging device described in Patent Document 2, the final stage of the output unit is a source follower circuit, and the constant current source unit (the load transistor Qd, the resistor Ra, and the constant voltage unit E is the final stage of the output unit. ) Is provided outside the solid-state image sensor, so that deterioration in performance due to heat generation in the signal accumulation period and signal output period of the solid-state image sensor can be suppressed (see FIG. 3). However, since the load transistors Qb and Qd, which are constant current sources of the source follower circuit as the output unit, always supply current to the drive transistors Qa and Qc of the source follower circuit, respectively, current consumption can be reduced. There wasn't.

本発明は、上記の状況に鑑み、発熱による性能悪化の抑制と消費電流の低減とを図ることができる固体撮像装置及びこれを備えた電子機器を提供することを目的とする。   In view of the above situation, an object of the present invention is to provide a solid-state imaging device capable of suppressing performance deterioration due to heat generation and reducing current consumption, and an electronic apparatus including the same.

上記目的を達成するために本発明に係る固体撮像装置は、出力部の最終段がソースフォロワ回路からなる固体撮像素子と、前記出力部の最終段であるソースフォロワ回路の負荷になる負荷部と、前記固体撮像素子の信号出力期間でない場合には前記負荷部に流れる電流を遮断又は低減するように前記負荷部を制御する制御回路とを備え、前記負荷部が前記固体撮像素子に対して外付けされており、
前記負荷部が定電流源部であり、前記制御回路が、前記固体撮像素子の信号出力期間でない場合には前記定電流源部に流れる定電流を遮断又は低減し、前記固体撮像素子の信号出力期間である場合には前記定電流源部が定電流を出力するように、前記定電流源部を制御し、
前記定電流源部が、負荷トランジスタと、前記負荷トランジスタの制御端子に定電圧を印加する定電圧回路とを備え、前記制御回路が、前記固体撮像素子の信号出力期間でない場合には前記定電圧回路が出力停止状態になり、前記固体撮像素子の信号出力期間である場合には前記定電圧回路が定電圧を出力するように、前記定電圧回路を制御し、
前記定電圧回路が、前記定電流源部本体に対して外付けされる外付け抵抗を備え、前記外付け抵抗の抵抗値に応じて前記定電圧回路が出力する定電圧の値が可変する構成とする。 In order to achieve the above object, a solid-state imaging device according to the present invention includes a solid-state imaging device in which the final stage of the output unit is a source follower circuit, and a load unit that is a load of the source follower circuit that is the final stage of the output unit. A control circuit for controlling the load unit so as to cut off or reduce a current flowing through the load unit when the signal output period of the solid-state image sensor is not, and the load unit is external to the solid-state image sensor. Attached ,
When the load unit is a constant current source unit and the control circuit is not in the signal output period of the solid-state image sensor, the constant current flowing through the constant current source unit is interrupted or reduced, and the signal output of the solid-state image sensor In the case of a period, the constant current source unit is controlled so that the constant current source unit outputs a constant current,
The constant current source unit includes a load transistor and a constant voltage circuit that applies a constant voltage to a control terminal of the load transistor, and the constant voltage is applied when the control circuit is not in a signal output period of the solid-state imaging device. When the circuit is in an output stop state and in the signal output period of the solid-state imaging device, the constant voltage circuit is controlled so that the constant voltage circuit outputs a constant voltage,
The constant voltage circuit includes an external resistor externally attached to the constant current source unit main body, and a constant voltage value output from the constant voltage circuit is variable according to a resistance value of the external resistor. And

このような構成によると、固体撮像素子の出力部の最終段であるソースフォロワ回路の負荷になる負荷部を固体撮像素子に対して外付けしているので、発熱による性能悪化の抑制を図ることができる。また、このような構成によると、固体撮像素子の信号出力期間でない場合には負荷部に流れる電流が遮断又は低減されるので、消費電流の低減を図ることができる。また、このような構成によると、前記固体撮像素子の設定が異なる場合でも前記定電流源部本体の共通化を図ることができる。 According to such a configuration, since the load unit that becomes the load of the source follower circuit, which is the final stage of the output unit of the solid-state imaging device, is externally attached to the solid-state imaging device, performance deterioration due to heat generation is suppressed. Can do. Further, according to such a configuration, the current flowing through the load unit is cut off or reduced when it is not the signal output period of the solid-state imaging device, so that the current consumption can be reduced. Further, according to such a configuration, the constant current source body can be shared even when the settings of the solid-state imaging device are different.

また、上記構成の固体撮像装置において、少なくとも前記負荷部と前記制御回路を１チップの集積回路に集積化し、少なくとも前記集積回路と前記固体撮像素子とを含むようにしてもよい。   In the solid-state imaging device having the above-described configuration, at least the load unit and the control circuit may be integrated into a one-chip integrated circuit, and at least the integrated circuit and the solid-state imaging element may be included.

また、上記各構成の固体撮像装置において、前記制御回路が、外部から供給される制御信号（例えば、前記固体撮像素子に各種駆動パルス信号を供給する駆動回路の出力信号）に応じて前記負荷部を制御するようにしてもよい。 Further, in the solid-state imaging device having the above-described configurations, the control circuit includes the load unit according to a control signal supplied from the outside (for example, an output signal of a driving circuit that supplies various driving pulse signals to the solid-state imaging device). May be controlled.

また、上記目的を達成するために本発明に係る電子機器は、上記各構成の固体撮像装置を備える構成とする。   In order to achieve the above object, an electronic apparatus according to the present invention includes a solid-state imaging device having the above-described configurations.

本発明によると、固体撮像装置において、固体撮像素子の出力部の最終段であるソースフォロワ回路の負荷になる負荷部を固体撮像素子に対して外付けし、固体撮像素子の信号出力期間でない場合には負荷部に流れる電流を遮断又は低減するので、発熱による性能悪化の抑制と消費電流の低減とを図ることができる固体撮像装置及びこれを備えた電子機器を実現することができる。   According to the present invention, in the solid-state imaging device, when the load unit that becomes the load of the source follower circuit, which is the final stage of the output unit of the solid-state imaging device, is externally attached to the solid-state imaging device and the signal output period is not in the solid-state imaging device Since the current flowing through the load section is cut off or reduced, it is possible to realize a solid-state imaging device capable of suppressing performance deterioration due to heat generation and reducing current consumption, and an electronic apparatus including the same.

本発明の実施形態について図面を参照して以下に説明する。本発明に係る固体撮像装置として、ここではＣＣＤイメージセンサを例に挙げて説明する。   Embodiments of the present invention will be described below with reference to the drawings. Here, a CCD image sensor will be described as an example of the solid-state imaging device according to the present invention.

本発明に係るＣＣＤイメージセンサの概略構成例を図１に示す。図１に示すＣＣＤイメージセンサは、出力部が２段ソースフォロワ回路である固体撮像素子を備えている。上記固体撮像素子は、各画素のフォトダイオード（不図示）と、垂直方向転送用ＣＣＤ（不図示）と、水平方向転送用ＣＣＤ（不図示）と、水平方向転送用ＣＣＤと出力部との間に設けられるフローティング・ディフュージョン（不図示）と、フローティング・ディフュージョンをリセットするためのリセット・トランジスタ（不図示）と、出力部の１段目駆動トランジスタＱａと、出力部の１段目負荷トランジスタＱｂと、出力部の２段目駆動トランジスタＱｃと、電源電圧ＶCCが印加される外部端子とグランドに接続される外部端子との間の電圧を分圧して得られる定電圧ＶGGを１段目負荷トランジスタＱｂのゲートに印加する分圧回路（不図示）とによって構成され、第１の半導体パッケージ１内の１チップの集積回路に集積化されている。上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源は第１の半導体パッケージ１に対して外付けされる。このように、図１に示すＣＣＤイメージセンサは、上記固体撮像素子の最終段ソースフォロワ回路の負荷になる定電流源部（上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源）が上記固体撮像素子に対して外付けされるので、発熱による性能悪化の抑制を図ることができる。 FIG. 1 shows a schematic configuration example of a CCD image sensor according to the present invention. The CCD image sensor shown in FIG. 1 includes a solid-state imaging device whose output unit is a two-stage source follower circuit. The solid-state imaging device includes a photodiode (not shown) of each pixel, a vertical transfer CCD (not shown), a horizontal transfer CCD (not shown), a horizontal transfer CCD, and an output unit. A floating diffusion (not shown), a reset transistor (not shown) for resetting the floating diffusion, a first-stage driving transistor Qa in the output section, and a first-stage load transistor Qb in the output section, The first stage load is a constant voltage V GG obtained by dividing the voltage between the second stage drive transistor Qc in the output section and the external terminal to which the power supply voltage V CC is applied and the external terminal connected to the ground. And a voltage dividing circuit (not shown) that is applied to the gate of the transistor Qb, and is integrated into a one-chip integrated circuit in the first semiconductor package 1. That. A constant current source serving as a load of the second-stage source follower circuit of the solid-state imaging device is externally attached to the first semiconductor package 1. As described above, the CCD image sensor shown in FIG. 1 has a constant current source unit that becomes a load of the last-stage source follower circuit of the solid-state imaging device (a constant-current source that becomes a load of the second-stage source follower circuit of the solid-state imaging device). ) Is externally attached to the solid-state imaging device, and performance deterioration due to heat generation can be suppressed.

上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源は、２段目負荷トランジスタであるＮＰＮトランジスタＱ４と、抵抗Ｒ５と、ＮＰＮトランジスタＱ４のベースに定電圧を供給する定電圧回路とによって構成される。ＮＰＮトランジスタＱ４のベースに定電圧を供給する定電圧回路は、抵抗Ｒ３及びＲ４と、ダイオードＤ１と、ＮＰＮトランジスタＱ２及びＱ３と、外付け抵抗Ｒ６とからなり、外付け抵抗Ｒ６を除く全ての構成部品が第２の半導体パッケージ２内の１チップの集積回路に集積化され、外付け抵抗Ｒ６が第２の半導体パッケージ２に対して外付けされる。   The constant current source serving as the load of the second-stage source follower circuit of the solid-state imaging device is a constant-voltage circuit that supplies a constant voltage to the base of the NPN transistor Q4, the resistor R5, and the NPN transistor Q4 as the second-stage load transistor. It is comprised by. The constant voltage circuit for supplying a constant voltage to the base of the NPN transistor Q4 is composed of resistors R3 and R4, a diode D1, NPN transistors Q2 and Q3, and an external resistor R6, and all components except the external resistor R6. The components are integrated in a one-chip integrated circuit in the second semiconductor package 2, and an external resistor R 6 is externally attached to the second semiconductor package 2.

図１に示すＣＣＤイメージセンサは、ＮＰＮトランジスタＱ４のベースに定電圧を供給する定電圧回路の出力ひいては上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源の出力を制御する制御回路も有している。当該制御回路は、抵抗Ｒ１及びＲ２と、ＮＰＮトランジスタＱ１とによって構成され、全ての構成部品が第２の半導体パッケージ２内の１チップの集積回路に集積化される。   The CCD image sensor shown in FIG. 1 controls the output of a constant voltage circuit that supplies a constant voltage to the base of an NPN transistor Q4, and thus the output of a constant current source that becomes the load of the second-stage source follower circuit of the solid-state imaging device. It also has a circuit. The control circuit is constituted by resistors R1 and R2 and an NPN transistor Q1, and all the components are integrated in a one-chip integrated circuit in the second semiconductor package 2.

また、図１に示すＣＣＤイメージセンサは、上記固体撮像素子の出力信号Ｖｏｕｔをインピーダンス変換するバッファ回路も有している。当該バッファ回路は、外付け抵抗Ｒ７とＮＰＮトランジスタＱ５とからなり、ＮＰＮトランジスタＱ５が第２の半導体パッケージ２内の１チップの集積回路に集積化され、外付け抵抗Ｒ７が第１の半導体パッケージ１及び第２の半導体パッケージ２に対して外付けされる。   The CCD image sensor shown in FIG. 1 also has a buffer circuit that performs impedance conversion on the output signal Vout of the solid-state imaging device. The buffer circuit includes an external resistor R7 and an NPN transistor Q5. The NPN transistor Q5 is integrated on a one-chip integrated circuit in the second semiconductor package 2, and the external resistor R7 is integrated in the first semiconductor package 1. And externally attached to the second semiconductor package 2.

次に、第２の半導体パッケージ２内の回路構成について説明する。ＮＰＮトランジスタＱ１のベースは、抵抗Ｒ１を介して外部端子Ｔ１に接続され、抵抗Ｒ２を介して外部端子端子Ｔ２に接続される。外部端子Ｔ１には制御信号ＳＴＢＹが供給され、外部端子Ｔ２はグランドに接続される。ＮＰＮトランジスタＱ１のエミッタは外部端子Ｔ２に接続され、ＮＰＮトランジスタＱ１のコレクタは外部端子Ｔ３、ＮＰＮトランジスタＱ２のコレクタ、及びＮＰＮトランジスタＱ３のベースに接続される。外部端子Ｔ３は外付け抵抗Ｒ６の一端に接続され、外付け抵抗Ｒ６の他端に電源電圧ＶCCが印加される。 Next, a circuit configuration in the second semiconductor package 2 will be described. The base of the NPN transistor Q1 is connected to the external terminal T1 through the resistor R1, and is connected to the external terminal terminal T2 through the resistor R2. A control signal STBY is supplied to the external terminal T1, and the external terminal T2 is connected to the ground. The emitter of the NPN transistor Q1 is connected to the external terminal T2, and the collector of the NPN transistor Q1 is connected to the external terminal T3, the collector of the NPN transistor Q2, and the base of the NPN transistor Q3. The external terminal T3 is connected to one end of the external resistor R6, and the power supply voltage V CC is applied to the other end of the external resistor R6.

ＮＰＮトランジスタＱ２のエミッタは抵抗Ｒ３を介して外部端子Ｔ２に接続され、ＮＰＮトランジスタＱ２のベースはＮＰＮトランジスタＱ３のエミッタ、ＮＰＮトランジスタＱ４のベース、及びダイオードＤ１のアノードに接続される。ダイオードＤ１のカソードは抵抗Ｒ４を介して外部端子Ｔ２に接続され、ＮＰＮトランジスタＱ４のエミッタは抵抗Ｒ５を介して外部端子Ｔ２に接続される。   The emitter of the NPN transistor Q2 is connected to the external terminal T2 via the resistor R3, and the base of the NPN transistor Q2 is connected to the emitter of the NPN transistor Q3, the base of the NPN transistor Q4, and the anode of the diode D1. The cathode of the diode D1 is connected to the external terminal T2 via the resistor R4, and the emitter of the NPN transistor Q4 is connected to the external terminal T2 via the resistor R5.

ＮＰＮトランジスタＱ４のコレクタは外部端子Ｔ４に接続される。ＮＰＮトランジスタＱ３のコレクタは外部端子Ｔ６及びＮＰＮトランジスタＱ５のコレクタに接続される。ＮＰＮトランジスタＱ５のベースは外部端子Ｔ５に接続され、ＮＰＮトランジスタＱ５のエミッタは外部端子端子Ｔ７に接続される。外部端子Ｔ４は、第１の半導体パッケージ１の２段目駆動トランジスタが接続されている外部端子と、外付け抵抗Ｔ７の一端とに接続される。外部端子Ｔ５は外付け抵抗Ｔ７の他端に接続され、外部端子Ｔ６には電源電圧ＶCCが印加される。外部端子Ｔ７は、サンプルホールド部やＡ／Ｄ変換部等を内蔵している後段の信号処理ＩＣの入力端子に接続される。 The collector of NPN transistor Q4 is connected to external terminal T4. The collector of NPN transistor Q3 is connected to external terminal T6 and the collector of NPN transistor Q5. The base of the NPN transistor Q5 is connected to the external terminal T5, and the emitter of the NPN transistor Q5 is connected to the external terminal terminal T7. The external terminal T4 is connected to an external terminal to which the second stage driving transistor of the first semiconductor package 1 is connected and one end of the external resistor T7. The external terminal T5 is connected to the other end of the external resistor T7, and the power supply voltage V CC is applied to the external terminal T6. The external terminal T7 is connected to an input terminal of a signal processing IC at a subsequent stage that incorporates a sample hold unit, an A / D conversion unit, and the like.

次に、上述した構成の上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源及び制御回路の動作について説明する。外部端子Ｔ１に供給される制御信号ＳＴＢＹは、上記固体撮像素子の信号出力期間でないときにＨｉｇｈレベルになり、上記固体撮像素子の信号出力期間中にＬｏｗレベルになる信号である。制御信号ＳＴＢＹは、上記固体撮像素子に各種駆動パルス信号を供給する駆動回路の出力信号（例えば垂直ＣＣＤ駆動パルス）を利用することができる。   Next, the operation of the constant current source and the control circuit that are the loads of the second-stage source follower circuit of the solid-state imaging device having the above-described configuration will be described. The control signal STBY supplied to the external terminal T1 is a signal that is at a high level when not in the signal output period of the solid-state image sensor and is at a low level during the signal output period of the solid-state image sensor. As the control signal STBY, an output signal (for example, a vertical CCD drive pulse) of a drive circuit that supplies various drive pulse signals to the solid-state imaging device can be used.

上記固体撮像素子の信号出力期間でないとき、外部端子Ｔ１に供給される制御信号ＳＴＢＹがＨｉｇｈレベルになりＮＰＮトランジスタＱ１がＯＮ状態になるので、ＮＰＮトランジスタＱ３のベースがグランド電位になりＮＰＮトランジスタＱ３がＯＦＦ状態となる。これにより、抵抗Ｒ３及びＲ４と、ダイオードＤ１と、ＮＰＮトランジスタＱ２及びＱ３と、外付け抵抗Ｒ６とからなる定電圧回路が出力停止状態になり、ＮＰＮトランジスタＱ４のベースに定電圧が供給されないので、上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源は出力停止状態になる。このように、図１に示すＣＣＤイメージセンサは、上記固体撮像素子の信号出力期間でないときに上記固体撮像素子の最終段ソースフォロワ回路の負荷になる定電流源（上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源）が出力停止状態になるので、消費電流の低減を図ることができる。   When it is not the signal output period of the solid-state imaging device, the control signal STBY supplied to the external terminal T1 becomes High level and the NPN transistor Q1 is turned on, so that the base of the NPN transistor Q3 becomes the ground potential and the NPN transistor Q3 It will be in the OFF state. As a result, the constant voltage circuit including the resistors R3 and R4, the diode D1, the NPN transistors Q2 and Q3, and the external resistor R6 is in an output stop state, and no constant voltage is supplied to the base of the NPN transistor Q4. The constant current source that becomes the load of the second-stage source follower circuit of the solid-state imaging device is in an output stopped state. As described above, the CCD image sensor shown in FIG. 1 has a constant current source (the second stage of the solid-state image sensor) that becomes a load of the final source follower circuit of the solid-state image sensor when the signal output period of the solid-state image sensor is not reached. Since the output of the constant current source that is the load of the source follower circuit is stopped, current consumption can be reduced.

一方、上記固体撮像素子の信号出力期間であるとき、外部端子Ｔ１に供給される制御信号ＳＴＢＹがＬｏｗレベルになりＮＰＮトランジスタＱ１がＯＦＦ状態になる。これにより、抵抗Ｒ３及びＲ４と、ダイオードＤ１と、ＮＰＮトランジスタＱ２及びＱ３と、外付け抵抗Ｒ６とからなる定電圧回路がＮＰＮトランジスタＱ４のベースに定電圧を供給するので、上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源は定電流を出力する。   On the other hand, during the signal output period of the solid-state imaging device, the control signal STBY supplied to the external terminal T1 becomes Low level, and the NPN transistor Q1 is turned off. As a result, a constant voltage circuit including the resistors R3 and R4, the diode D1, the NPN transistors Q2 and Q3, and the external resistor R6 supplies a constant voltage to the base of the NPN transistor Q4. A constant current source serving as a load of the stage source follower circuit outputs a constant current.

なお、図１に示すＣＣＤイメージセンサでは、外付け抵抗Ｒ６の抵抗値設定を変更することにより、抵抗Ｒ３及びＲ４と、ダイオードＤ１と、ＮＰＮトランジスタＱ２及びＱ３と、外付け抵抗Ｒ６とからなる定電圧回路がＮＰＮトランジスタＱ４のベースに供給する定電圧の値、ひいては上記固体撮像素子の２段目ソースフォロワ回路の負荷になる定電流源が出力する定電流の値を変更することができる。したがって、第１の半導体パッケージ１の仕様が異なる場合でも、外付け抵抗Ｒ６の抵抗値設定の変更のみで対応でき、第２の半導体パッケージ２の共通化を図ることができる。   In the CCD image sensor shown in FIG. 1, by changing the resistance value setting of the external resistor R6, a constant value composed of resistors R3 and R4, a diode D1, NPN transistors Q2 and Q3, and an external resistor R6. The value of the constant voltage supplied to the base of the NPN transistor Q4 by the voltage circuit, and hence the value of the constant current output from the constant current source that becomes the load of the second-stage source follower circuit of the solid-state image sensor can be changed. Therefore, even if the specifications of the first semiconductor package 1 are different, it can be dealt with only by changing the resistance value setting of the external resistor R6, and the second semiconductor package 2 can be shared.

また、本発明に係る電子機器の一構成例としては、図１に示すＣＣＤイメージセンサと、上記ＣＣＤイメージセンサの後段に設けられる信号処理ＩＣと、被写体からの像を前記ＣＣＤイメージセンサ上に結像させる光学レンズと、上記ＣＣＤイメージセンサに設けられる固体撮像素子に各種駆動パルス信号を供給する駆動回路とを備える構成が挙げられる。本発明に係る電子機器の例としては、カメラ付携帯電話、デジタルカメラ、監視カメラ等が挙げられる。   Further, as an example of the configuration of the electronic apparatus according to the present invention, a CCD image sensor shown in FIG. 1, a signal processing IC provided at the subsequent stage of the CCD image sensor, and an image from a subject are connected on the CCD image sensor. A configuration including an optical lens for imaging and a drive circuit for supplying various drive pulse signals to a solid-state imaging device provided in the CCD image sensor can be mentioned. Examples of the electronic apparatus according to the present invention include a camera-equipped mobile phone, a digital camera, and a surveillance camera.

は、本発明に係るＣＣＤイメージセンサの概略構成例を示す図である。These are figures which show the example of schematic structure of the CCD image sensor which concerns on this invention. は、従来の固体撮像素子の出力部の構成例を示す図である。These are figures which show the structural example of the output part of the conventional solid-state image sensor. は、従来の固体撮像素子の出力部の他の構成例を示す図である。These are figures which show the other structural example of the output part of the conventional solid-state image sensor.

符号の説明Explanation of symbols

１ 第１の半導体パッケージ
２ 第２の半導体パッケージ
Ｑ１〜Ｑ５ ＮＰＮトランジスタ
Ｑａ 出力部の１段目駆動トランジスタ
Ｑｂ 出力部の１段目負荷トランジスタ
Ｑｃ 出力部の２段目駆動トランジスタ
Ｒ１〜Ｒ５ 抵抗
Ｒ６、Ｒ７ 外付け抵抗 DESCRIPTION OF SYMBOLS 1 1st semiconductor package 2 2nd semiconductor package Q1-Q5 NPN transistor Qa The 1st stage drive transistor of an output part Qb The 1st stage load transistor of an output part Qc The 2nd stage drive transistor of an output part R1-R5 Resistor R6, R7 External resistor

Claims (4)

出力部の最終段がソースフォロワ回路からなる固体撮像素子と、前記出力部の最終段であるソースフォロワ回路の負荷になる負荷部と、前記固体撮像素子の信号出力期間でない場合には前記負荷部に流れる電流を遮断又は低減するように前記負荷部を制御する制御回路とを備え、前記負荷部が前記固体撮像素子に対して外付けされており、
前記負荷部が定電流源部であり、前記制御回路が、前記固体撮像素子の信号出力期間でない場合には前記定電流源部に流れる定電流を遮断又は低減し、前記固体撮像素子の信号出力期間である場合には前記定電流源部が定電流を出力するように、前記定電流源部を制御し、
前記定電流源部が、負荷トランジスタと、前記負荷トランジスタの制御端子に定電圧を印加する定電圧回路とを備え、前記制御回路が、前記固体撮像素子の信号出力期間でない場合には前記定電圧回路が出力停止状態になり、前記固体撮像素子の信号出力期間である場合には前記定電圧回路が定電圧を出力するように、前記定電圧回路を制御し、
前記定電圧回路が、前記定電流源部本体に対して外付けされる外付け抵抗を備え、前記外付け抵抗の抵抗値に応じて前記定電圧回路が出力する定電圧の値が可変することを特徴とする固体撮像装置。 A solid-state imaging device in which the final stage of the output unit is a source follower circuit, a load unit that is a load of the source follower circuit that is the final stage of the output unit, and the load unit if it is not a signal output period of the solid-state imaging device A control circuit that controls the load unit so as to cut off or reduce the current flowing through the load, the load unit is externally attached to the solid-state imaging device ,
When the load unit is a constant current source unit and the control circuit is not in the signal output period of the solid-state image sensor, the constant current flowing through the constant current source unit is interrupted or reduced, and the signal output of the solid-state image sensor In the case of a period, the constant current source unit is controlled so that the constant current source unit outputs a constant current,
The constant current source unit includes a load transistor and a constant voltage circuit that applies a constant voltage to a control terminal of the load transistor, and the constant voltage is applied when the control circuit is not in a signal output period of the solid-state imaging device. When the circuit is in an output stop state and in the signal output period of the solid-state imaging device, the constant voltage circuit is controlled so that the constant voltage circuit outputs a constant voltage,
The constant voltage circuit includes an external resistor externally attached to the constant current source unit body, and a constant voltage value output from the constant voltage circuit is variable according to a resistance value of the external resistor. A solid-state imaging device. 少なくとも前記負荷部と前記制御回路を１チップの集積回路に集積化し、少なくとも前記集積回路と前記固体撮像素子とを含む請求項１に記載の固体撮像装置。 2. The solid-state imaging device according to claim 1, wherein at least the load unit and the control circuit are integrated in a one-chip integrated circuit, and includes at least the integrated circuit and the solid-state imaging device. 前記制御回路が、外部から供給される制御信号に応じて前記負荷部を制御する請求項１又は請求項２に記載の固体撮像装置。 The solid-state imaging device according to claim 1 , wherein the control circuit controls the load unit according to a control signal supplied from the outside . 請求項１〜３のいずれかに記載の固体撮像装置を備えることを特徴とする電子機器。An electronic apparatus comprising the solid-state imaging device according to claim 1.
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