JP4311214B2 - Demodulator, disk drive device, and phase adjustment method - Google Patents

Description

  The present invention relates to a demodulator for an MSK (Minimum Shift Keying) modulated signal and an STW (Saw Tooth Wobble) modulated signal, a disk drive device equipped with the demodulator, and a method for adjusting the phase of an internal reference wave in the demodulator.

JP 2003-123249 A Japanese Patent No. 3343997 Japanese Patent No. 3233016

As a technique for recording / reproducing digital data, optical disks (including magneto-optical disks) such as CD (Compact Disk), MD (Mini-Disk), and DVD (Digital Versatile Disk) are used as recording media. There is data recording technology. An optical disk is a generic term for recording media that irradiate laser light onto a disk in which a thin metal plate is protected with plastic, and read signals by changes in reflected light.
The optical disc includes, for example, a read-only type as known as CD, CD-ROM, DVD-ROM, MD, CD-R, CD-RW, DVD-R, DVD-RW, DVD + RW, DVD -There is a type in which user data can be recorded as known in RAM and the like. In the recordable type, data can be recorded by utilizing a magneto-optical recording method, a phase change recording method, a dye film change recording method, or the like. The dye film change recording method is also called a write-once recording method, and can be recorded only once and cannot be rewritten. On the other hand, the magneto-optical recording method and the phase change recording method can rewrite data and are used for various purposes such as recording of various content data such as music, video, games, application programs and the like.
In recent years, a high-density optical disk called a Blu-ray Disc has been developed, and the capacity has been significantly increased.

In order to record data on a recordable disc such as a magneto-optical recording method, a dye film change recording method, a phase change recording method, etc., a guide means for tracking the data track is required. Grooves (grooves) are formed in advance as pregrooves, and the grooves or lands (cross-section plateau-like portions sandwiched between the grooves and the grooves) are used as data tracks.
Further, it is necessary to record address information so that data can be recorded at a predetermined position on the data track, but this address information may be recorded by wobbling (meandering) the groove.

That is, a track for recording data is formed in advance as a pregroup, for example, and the side wall of this pregroup is wobbled corresponding to the address information.
In this way, the address can be read from the wobbling information obtained as reflected light information at the time of recording or reproduction. For example, even if pit data indicating the address is not formed on the track in advance, the desired position can be read. Data can be recorded and reproduced.
By adding address information as a wobbling groove in this way, for example, it becomes unnecessary to provide an address area discretely on a track and record an address as, for example, pit data. Recording capacity can be increased.
The absolute time (address) information expressed by such a wobbling groove is called ATIP (Absolute Time In Pregroove) or ADIP (Adress In Pregroove).

In the case of the Blu-ray disc, the groove is wobbled based on a modulation waveform obtained by combining MSK modulation and STW modulation.
The MSK modulation and STW modulation and ADIP information formed by combining these will be described in detail later. The MSK modulation has a modulation index of 0.5 among FSK (Frequency Shift Keying) modulation in which phases are continuous. It is.
STW modulation is a modulation method that generates a modulation waveform such as a sawtooth waveform by adding or subtracting twice the harmonics to the wobble fundamental wave.
In a disk drive device corresponding to a Blu-ray disc, an MSK demodulator and an STW demodulator are mounted in order to reproduce such ADIP information.
In particular, techniques relating to demodulation of MSK / STW modulation signals and decoding of ADIP information are disclosed in Patent Documents 1, 2, and 3.

  FIG. 18 shows an example of a circuit that performs MSK demodulation / STW demodulation, which is necessary as a preceding process in order to decode ADIP information. This is a circuit that performs MSK demodulation / STW demodulation on the push-pull signal P / P as reflected light information by the wobbling groove of the disk and supplies the demodulated signal to the ADIP decoder at the subsequent stage. For explanation, FIG. 8 and FIG. 9 are also referred to.

The push-pull signal as shown in FIG. 8A obtained as a wobbling groove modulation signal is supplied to the A / D converter 111 and the comparator 112 in the MSK demodulator 110 in FIG.
The comparator 112 binarizes the push-pull signal P / P and supplies it to the PLL circuit 113. In the PLL circuit 113, as shown in FIG. 8B, a push-pull signal P / P, that is, a frequency (wobble frequency) of a modulation signal of a wobbling groove (hereinafter referred to as a modulation frequency signal) is generated based on the binarized signal. Generate.
The modulation frequency signal output from the PLL circuit 113 is supplied to the PLL circuit 114 and the edge detection circuit 115.
The PLL circuit 114 multiplies the modulation frequency signal and generates a clock CK. This clock CK is used as a sampling clock for the A / D converter 111, and is also used by the edge detection circuit 115, the delay circuit 116, and the counter 117.

The edge detection circuit 115 detects a rising edge of the modulation frequency signal and outputs a detection pulse of the rising edge. This detection pulse becomes information on the reference timing of the wobble frequency signal.
The detection pulse by the edge detection circuit 115 is supplied to the counter 117 after a predetermined delay time is given by the delay circuit 116 in units of the clock CK. The counter 117 performs an operation of counting the clock CK, but performs count reset at the timing when the detection pulse from the delay circuit 116 is supplied. That is, the counter 117 counts the clock CK from the reset timing by the detection pulse, and outputs the count value to the cos table 121.
The cos table 121 is a table that stores waveform data to be an internal reference wave, and each data is read according to the count value of the counter 117.
For example, it is assumed that the clock CK has a frequency at which one cycle of the wobble basic waveform is 23 clocks. Since the counter 117 is reset at intervals of one cycle of the wobble basic waveform, the count value of 0 to 22 is repeatedly generated.
In the cos table 121, data of TD0 to TD22 is stored as cos waveform data serving as an internal reference wave, and the data is sequentially read according to the count value. As a result, as shown in FIG. 8C, an internal reference wave having the same frequency as the wobble basic waveform is generated and supplied to the multiplier 118.

On the other hand, the input push-pull signal P / P is sampled by the A / D converter 111 with the clock CK, converted into digital data, and supplied to the multiplier 118.
Accordingly, the multiplier 118 multiplies the modulated signal data and the internal reference wave data. This multiplication value is, for example, as shown in FIG. The multiplied value is supplied to the adder 119 and integrated. The adder 119 is reset by the detection pulse from the delay circuit 116. That is, the adder 119 is reset at the same timing as the counter 117. Therefore, in the adder, multiplication values are integrated during one wobble basic waveform period. For example, the operation of integrating the multiplication results of 23 samples is repeated.
Then, the integrated value (added value after multiplication) changes as shown in FIG. The output of such an adder 119 is positive / negative determined by the positive / negative determination circuit 120, and the determination result becomes an MSK demodulated signal. For example, the demodulated signal is obtained by sampling / holding the output of the adder 119 at a predetermined timing and determining whether the hold value is positive or negative (binarization). That is, as shown in FIG. 8, the added value after multiplication changes in the positive direction in the wobble fundamental wave section in the input modulation signal. On the other hand, the added value after multiplication shifts in the negative direction in the section of the MSK mark. Therefore, a demodulated signal for discriminating between the MSK mark and the fundamental wave can be obtained by determining whether this is positive or negative.

  The STW demodulator 130 has a configuration substantially similar to that of the MSK demodulator 110 although a detailed description thereof is omitted here. That is, an STW demodulated signal is obtained by converting the push-pull signal P / P, which is a modulation signal, into digital data, multiplying it by an internal reference wave, and determining whether the integrated value of the multiplication result is positive or negative. However, in the case of the STW demodulator 130, the internal reference wave is a second harmonic signal of the wobble basic waveform. The integration is performed not in the period of one wobble basic waveform but in a plurality of wobble periods in which STW modulation is performed on the wobble signal (push-pull signal P / P).

Incidentally, the wobble signal waveform read from the disc fluctuates due to crosstalk from adjacent tracks, a difference between output amplitudes before and after recording, disc quality variations, and the like. When trying to demodulate the MSK signal and STW signal from a signal with a lot of noise components and a poor S / N, the sampling frequency becomes relatively low especially at a high transfer rate, so that the modulation signal waveform (wobble signal waveform) In some cases, the phase of the fundamental wave is greatly different, and the phase shift causes a demodulation error.
For example, FIG. 9 shows a case where the phase of the input modulation signal (FIG. 9A) and the internal reference wave (FIG. 9C) are greatly shifted. In this case, the multiplication value is as shown in FIG. 9D, and the post-multiplication addition value is as shown in FIG. This post-multiplication addition value is in a state where an error is likely to occur during positive / negative determination, as can be seen by comparison with the post-multiplication addition value of FIG.

In order to eliminate this phase shift, the delay amount in the delay circuit 116 is adjusted. For example, the CPU 100 in FIG. 18 is configured so that the delay amount in the delay circuit 116 can be variably set in units of clocks CK.
As described above, assuming that the clock CK has a frequency of 23 clocks in one wobble basic waveform period, the phase of the internal reference wave is changed in 1/23 period units by changing the delay amount in the delay circuit 116. You can adjust it. That is, when the clock CK becomes 23 clocks in the wobble basic waveform cycle of FIG. 19A, the reset timing of the counter 117 is varied in units of clock timing, and therefore the data TD0 to TD22 output from the cos table 121. Can be changed as shown in FIGS. 19C, 19D, 19E, and so on to change the phase of the internal reference wave.
In this way, if the modulation signal is adjusted so that the phase of the internal reference wave multiplied by the multiplier 118 is matched, a demodulation error due to a phase shift can be avoided.

However, in practice, for example, in the phase adjustment in units of 1/23 of one wobble basic waveform cycle, the adjustment width (phase difference) in one step is large, and the phase adjustment with a precision that can sufficiently avoid the demodulation error. I could not.
However, for this, it can be said that the frequency of the clock CK may be increased. If the frequency of the clock CK is increased, the amount of delay in the delay circuit 116 can be adjusted in such a fine step, whereby the phase of the internal reference wave can be adjusted precisely. In particular, Patent Document 3 discloses a method for increasing the sampling frequency to increase the phase resolution of the signal waveform.

  However, it is not easy to increase the sampling frequency (clock CK). In particular, at present, it is necessary to consider operation at a high transfer rate. In this case, increasing the sampling frequency significantly increases the operation load of the circuit, and in practice, it is difficult to increase the clock frequency. .

  In view of such a problem, an object of the present invention is to enable more precise phase adjustment without increasing the sampling frequency, thereby realizing a stable demodulation operation.

The demodulator of the present invention includes a signal generation means for generating a modulation frequency signal and a clock signal obtained by multiplying the modulation frequency signal based on the input modulation signal, and sampling the input modulation signal with the clock signal. A / D conversion means for outputting modulated signal data as digital data, and a reference timing for generating a reference timing signal based on the modulation frequency signal and delaying the reference timing signal in units of the clock signal Signal generating means; internal reference wave generating means capable of generating a plurality of internal reference waves having different phases within a range of one clock cycle of the clock signal with reference to the reference timing signal; and the internal reference wave generating means selection means for selecting one of a plurality of internal reference wave by, after being selected by the selection means A demodulator that multiplies the internal reference wave data by the modulation signal data output from the A / D converter and obtains a demodulated signal from a value obtained by integrating the multiplication results, and the reference timing signal generator described above. While obtaining the evaluation value of the demodulation operation while changing the delay time step by step, the optimum delay time is determined and the delay time is set, and further, the optimum delay time is set. The selection means determines the optimum internal reference wave by acquiring the evaluation value of the demodulating operation while sequentially selecting each of the plurality of internal reference waves by the internal reference wave generating means to optimize the selection means. Phase adjustment means for adjusting the phase of the internal reference wave by setting the selected state of the internal reference wave .
Further, in this case, the internal reference wave generating means is reset by the reference timing signal from the reference timing signal generating means, and a counter that counts at the clock signal timing, and each of the clock signals is one clock of the clock signal. The internal reference wave data having different phases within the period range is held, and each of the data is configured by a plurality of tables configured to output data specified by the count value from the counter, and The selection means is configured to select one of the plurality of tables.

The disk drive apparatus according to the present invention further includes a reading means for reading a modulation signal recorded as a wobbling groove on a disk recording medium, and the modulation signal read by the reading means is demodulated by the demodulating apparatus having the above-described configuration. . The demodulated demodulated signal is decoded by a decoding means to obtain information recorded as the wobbling groove.
In this case, the decoding means obtains address information on the disk recording medium as information recorded as the wobbling groove.

In the demodulating device or the disk drive device, the modulation signal is an MSK modulation signal, and the internal reference wave generating means outputs an internal reference wave having the same frequency as the reference wave of the MSK modulation signal.
The modulation signal is an STW modulation signal, and the internal reference wave generating means outputs an internal reference wave that is a second harmonic of the reference wave of the STW modulation signal.

  The phase adjustment method of the present invention is a phase adjustment method of the internal reference wave in the demodulator having the above configuration. Then, an evaluation value of the demodulation operation is obtained while changing the delay time in the reference timing signal generation means stepwise, and a delay time setting step for discriminating and setting an optimum delay time; and the optimum time While the delay time is set, the evaluation value of the demodulation operation is acquired while sequentially selecting each of the plurality of internal reference waves by the internal reference wave generating means, the optimum internal reference wave is determined, and the above selection is performed. And an internal reference wave selection step for setting the means to an optimal internal reference wave selection state.

  That is, according to the present invention, in a circuit that demodulates an input modulated signal wave by calculating an internal reference wave, the internal reference wave generating means is, for example, a numerical value whose phase is changed as an internal reference wave table (calculation numerical value table). Provide multiple tables. In addition, by adopting a configuration in which one of a plurality of tables can be selected, even when there is a difference in the phase of the clock that generates the internal reference wave and the input modulation signal, the internal reference is canceled so that the phase difference is eliminated. The phase of the wave is adjusted so that the operation for demodulation can be performed with the waveform having the same phase.

According to the present invention, in a circuit that demodulates an input modulated signal wave by calculating an internal reference wave, the internal reference wave generating means generates a plurality of internal reference waves having different phases within one clock cycle. To be able to. For example, a plurality of numerical tables with different phases are provided as internal reference wave tables (calculated numerical tables), and one of the plurality of tables can be selected. As a result, even if there is a difference between the phase of the clock that generates the internal reference wave and the input modulation signal, the phase of the internal reference wave is adjusted so that the phase difference is eliminated, and the waveform with the same phase is demodulated. Therefore, there is an effect that even a noisy input signal (modulated signal) can be correctly demodulated.
In particular, in the operation at a high transfer rate in the disk drive device, when the circuit operating frequency cannot be increased with the high-speed rotation of the disk, the sampling interval inevitably becomes relatively sparse, crosstalk from adjacent tracks, and after writing. Decrease in reflectivity Wobble signal deteriorates and MSK demodulated data and STW demodulated data tend not to be read correctly. However, according to the present invention, the resolution of phase adjustment can be increased without increasing the clock frequency. Can be demodulated sufficiently, and the address can be read correctly. Furthermore, this also has the advantage that the dead time until the address information is correctly read out is shortened, and that recording / reproducing can be performed stably even on recording / reproducing media having large variations.
In addition, since the wobble address demodulation capability can be maintained even with variations in characteristics of the pickup unit by appropriate phase adjustment, the yield of the pickup unit can be improved.

Hereinafter, embodiments of the present invention will be described in the following order.
1. MSK modulation, STW modulation, and ADIP
2. 2. Configuration of disk drive device 3. MSK demodulator 4. STW demodulator Effects and modifications of the embodiment

1. MSK modulation, STW modulation, and ADIP

As shown in FIG. 1A, the optical disk 1 corresponding to the embodiment of the present invention is formed with a groove GV serving as a recording track. The groove GV is formed in a spiral shape from the inner peripheral side to the outer peripheral side. Therefore, when the cut surface in the radial direction of the optical disc 1 is viewed, as shown in FIG. 1B, convex lands L and concave grooves GV are alternately formed. Note that the spiral direction in FIG. 1A is a state in which the optical disk 1 is viewed from the recording surface side. In the case of a disk having a plurality of recording layers, the spiral state may be different in each recording layer.

As shown in FIG. 1B, the groove GV of the optical disk 1 is meandered in the tangential direction. The meandering shape of the groove GV is a shape corresponding to the wobble signal. Therefore, in the optical disk drive, both edge positions of the groove GV are detected from the reflected light of the laser spot LS irradiated to the groove GV, and the positions of both edges when the laser spot LS is moved along the recording track are detected. By extracting the fluctuation component with respect to the disk radial direction, the wobble signal can be reproduced.
In this wobble signal, the address information (physical address and other additional information) of the recording track at the recording position is modulated. Therefore, the optical disk drive can perform address control and the like during data recording and reproduction by demodulating address information and the like from the wobble signal.

  In the embodiment of the present invention, an optical disk on which groove recording is performed will be described. However, the present invention is not limited to such an optical disk of groove recording, but is applied to an optical disk that performs land recording for recording data on a land. It is also possible to apply to a land-groove recording optical disk for recording data in the groove and land.

  Here, in the optical disc 1 of the present embodiment, the address information is modulated with respect to the wobble signal by using two modulation methods. One is an MSK (Minimum Shift Keying) modulation method. The other is an STW (Saw Tooth Wobble) that modulates by adding an even-order harmonic signal to a sine wave carrier signal and changing the polarity of the harmonic signal in accordance with the sign of the modulated data. Modulation method.

  In the optical disc 1 of the present embodiment, as shown in FIG. 3A, a block in which a reference carrier signal waveform of a sine wave of a predetermined frequency continues for a predetermined period is formed, and MSK-modulated address information is included in this block. Is generated, and an STW modulation unit in which STW-modulated address information is inserted is generated. That is, MSK-modulated address information and STW-modulated address information are inserted at different positions in the block. Further, one of the two sine wave carrier signals used in the MSK modulation and the STW modulation carrier signal are used as the reference carrier signal. Also, the MSK modulation unit and the STW modulation unit are arranged at different positions in the block, respectively, and a reference carrier signal of one cycle or more is arranged between the MSK modulation unit and the STW modulation unit. Yes.

  A portion where no data is modulated and only the frequency component of the reference carrier signal appears is hereinafter referred to as monotone wobble. In the following, it is assumed that the sine wave signal used as the reference carrier signal is Cos (ωt). One period of the reference carrier signal is referred to as one wobble period. The frequency of the reference carrier signal is constant from the inner periphery to the outer periphery of the optical disc 1 and is determined according to the relationship with the linear velocity when the laser spot moves along the recording track.

Hereinafter, modulation methods of MSK modulation and STW modulation will be described in more detail. First, the address information modulation method using the MSK modulation method will be described.
The MSK modulation has a modulation index of 0.5 among FSK (Frequency Shift Keying) modulation in which phases are continuous. FSK modulation is a method of modulating two carrier signals of frequency f1 and frequency f2 by associating “0” and “1” of the code of modulated data with each other. In other words, if the modulated data is “0”, a sine wave waveform of frequency f1 is output, and if the modulated data is “1”, a sine wave waveform of frequency f1 is output. Further, in the case of FSK modulation with continuous phases, the phases of the two carrier signals are continuous at the timing of switching the code of the modulated data.
In this FSK modulation, a modulation index m is defined. This modulation index m is
m = | f1-f2 | T
Defined by Here, T is the transmission rate of modulated data (1 / the time of the shortest code length). The phase continuous FSK modulation when m is 0.5 is referred to as MSK modulation.

The MSK modulation waveform is shown in FIG. FIG. 2A shows a state in which MSK modulation waveforms (MM1, MM2, MM3) are present in a region of three wobble periods sandwiched between monotone wobbles MW.
If the monotone wobble is expressed as Cos (ωt) as described above, one of the two frequencies used for MSK modulation is the same frequency as the reference carrier signal and the other is 1.5 times the frequency of the reference carrier signal. Therefore, one of the signal waveforms used for MSK modulation is Cos (ωt) or -Cos (ωt), and the other is Cos (1.5ωt) or -Cos (1.5ωt).
2A shows two monotone wobbles, an MSK modulation region, and two monotone wobbles. In this case, the signal waveform of the MSK stream is Cos (wt) for each wobble period. , Cos (wt), Cos (1.5wt), -Cos (wt), -Cos (1.5wt), Cos (wt). In the drawing, monotone wobble Cos (ωt) = cos {2π · (fwob) · t} is shown (fwob is a reference carrier frequency). Therefore, the three wobble period as the MSK modulation region is MM1 = cos { 2π · (1.5 · fwob) · t}, MM2 = −cos {2π · (fwob) · t}, and MM3 = −cos {2π · (1.5 · fwob) · t}.
Thus, the first wobble cycle period (MM1) has a frequency 1.5 times that of the monotone wobble, the second (MM2) has the same frequency as the monotone wobble, and the third (MM3) has a frequency of 1.5 of the monotone wobble. The frequency is doubled, and the phase returns in this three wobble period. That is, the phase is continuous with the preceding and following monotone wobbles, and the second wobble (MM2) has a polarity reversed with respect to the monotone wobble.

In the optical disc 1, address information is modulated into the wobble signal by making the wobble signal into the MSK stream as described above, and this MSK modulated signal can be synchronously detected for the following reason.
When the modulated data is inserted into the wobble signal of the optical disc 1 by the MSK modulation method, first, the data stream of the modulated data is differentially encoded in units of clocks corresponding to the wobble period. That is, the difference calculation is performed on the modulated data stream and the delayed data delayed by one period of the reference carrier signal. The data that has been subjected to the differential encoding processing is referred to as pre-coded data. Subsequently, the precoded data is MSK modulated to generate the MSK stream as described above.

  In the differentially encoded data (precode data), a bit is set at the sign change point of the modulated data (becomes “1”). Since the code length of the modulated data is at least twice the wobble period, the reference carrier signal (Cos (ωt)) or its inverted signal (−Cos (ωt) is always included in the latter half of the code length of the modulated data. )) Will be inserted. When the bit of the precode data is “1”, a waveform having a frequency 1.5 times that of the reference carrier signal is inserted, and the waveform is connected in phase at the sign switching point. Therefore, the signal waveform inserted in the latter half of the code length of the modulated data is always the reference carrier signal waveform (Cos (ωt)) if the modulated data is “0”, and the modulated data is “1”. If so, the inverted signal waveform (-Cos (ωt)) is always obtained. The synchronous detection output has a positive value if the phase is in phase with the carrier signal, and a negative value if the phase is inverted. Therefore, the above MSK modulated signal is used as the reference carrier. If synchronous detection is performed using a signal, the modulated data can be demodulated.

Next, STW modulation will be described.
In STW modulation, as described above, an even-order harmonic signal is added to a sinusoidal carrier signal, and the polarity of the harmonic signal is changed in accordance with the code of the modulated data to modulate the digital code. Modulation method.
In the optical disc 1, the STW modulated carrier signal is a signal having the same frequency and phase as the reference carrier signal (Cos (ωt)), which is the MSK modulated carrier signal. The even-order harmonic signals to be added are Sin (2ωt) and −Sin (2ωt), which are the second-order harmonics of the reference carrier signal (Cos (ωt)), and the amplitude thereof is relative to the amplitude of the reference carrier signal. The amplitude is −12 dB. The minimum code length of the modulated data is set to twice the wobble period (period of the reference carrier signal).
When the code of the modulated data is “1”, Sin (2ωt) is added to the carrier signal, and when it is “0”, modulation is performed by adding −Sin (2ωt) to the carrier signal.

FIG. 2B shows a signal waveform when the wobble signal is modulated by the above method. FIG. 2B shows the signal waveform of the monotone wobble MW of the reference carrier signal (Cos (ωt)) in the central wobble period. In the previous two wobble periods, a signal waveform in which Sin (2ωt) is added to the reference carrier signal (Cos (ωt)), that is, a signal waveform when the modulated data is “1” is shown. Yes. Further, in the 2 wobble period after the monotone wobble MW, a signal waveform in which −Sin (2ωt) is added to the reference carrier signal (Cos (ωt)), that is, a signal waveform when the modulated data is “0”. Is shown.
In the drawing, monotone wobble Cos (ωt) = cos {2π · (fwob) · t} is shown. Therefore, when the modulated data is “1”, the STW modulated signal is cos {2π · (fwob). ) · T} + a · sin {2π · (2 · fwob) · t}, and when the modulated data is “0”, cos {2π · (fwob) · t} −a · sin {2π · (2 · fwob) · t}.
As can be seen from the figure, this STW signal waveform rises steeply on the outer periphery of the disk and gently returns to the inner periphery, and conversely, rises with a gentle slope on the outer periphery of the disk and returns sharply. Values of “1” and “0” are expressed. In either case, the waveform has a common zero cross point with the monotone wobble MW indicated by a broken line. Therefore, in extracting the clock from the fundamental wave component common to the MSK monotone wobble MW portion, the phase is not affected.

Then, when positive and negative even harmonic signals are added to the reference carrier signal in this way, from the characteristics of the generated waveform, synchronous detection is performed using this harmonic signal, and the code data of the modulated data is It is possible to demodulate the modulated data by integrating the synchronous detection output.
In the optical disc 1, the harmonic signal added to the carrier signal is a second harmonic, but not limited to the second harmonic, any signal may be added as long as it is an even harmonic. Further, in the optical disc 1, only the second harmonic is added, but a plurality of harmonic signals may be added simultaneously such that both the second harmonic and the fourth harmonic are added simultaneously.

An ADIP structure including MSK modulation and STW modulation as described above will be described. One unit (ADIP unit) as ADIP information is composed of 56 wobbles.
FIG. 3B shows eight types of ADIP units. The eight types are a monotone unit, a reference unit, a sync 0 unit, a sync 1 unit, a sync 2 unit, a sync 3 unit, a data 1 unit, and a data 0 unit.
In all eight types of ADIP units, the leading wobble numbers 0, 1, and 2 are MSK marks.
In the monotone unit, the wobble numbers 3 to 55 following the MSK mark are all composed of monotone wobbles.
The reference unit is an STW modulation wobble in which wobble numbers 18 to 54 indicate a zero value.
Each of the sync 0 unit, the sync 1 unit, the sync 2 unit, and the sync 3 unit is an ADIP unit for sync information, and an MSK mark is arranged at a predetermined wobble number position as illustrated.
The data 1 unit represents the value “1”, and the data 0 unit represents the value “0”. In the case of 1 data unit, the MSK mark is arranged in the wobble numbers 12 to 14, and the wobble numbers 18 to 54 are STW modulated wobbles having the value “1”. In the case of data 0 unit, the MSK mark is arranged in the wobble numbers 14 to 16, and the wobble numbers 18 to 54 are STW modulation wobbles having the value “0”.

By collecting 83 such ADIP units, one piece of ADIP information (address information) is formed.
That is, as shown in FIG. 4, one unit of ADIP information is formed by ADIP units 0-82. ADIP unit numbers 0 to 7 are a monotone unit, a sync 0 unit, a monotone unit, a sync 1 unit, a monotone unit, a sync 2 unit, a monotone unit, and a sync 3 unit.
After the ADIP unit number 8, five units as a reference unit and a 4-bit data unit are repeatedly arranged. Each data unit (for example, data [0], data [1], data [2], data [3]... Data [59]) is either one of the data 1 unit or data 0 unit. , A 60-bit value as ADIP information is shown. These 60 bits include an address value, additional information, ECC parity, and the like.

2. Configuration of disk drive device

Next, a disk drive device capable of recording / reproducing corresponding to the disk 1 as described above will be described. FIG. 5 shows the configuration of the disk drive device.
The disk 1 is loaded on a turntable (not shown) and is driven to rotate at a constant linear velocity (CLV) by a spindle motor 52 during a recording / reproducing operation.
Then, ADIP information embedded as wobbling of the groove track on the disk 1 is read by the optical pickup (optical head) 51.
On the disk 1, for example, physical information of the disk is recorded as reproduction-only management information by embossed pits or wobbling grooves. Reading of these information is also performed by the pickup 51.
When data is recorded, user data is recorded on the track as a phase change mark by the optical pickup, and at the time of reproduction, the mark recorded by the optical pickup is read.

  In the pickup 51, a laser diode serving as a laser light source, a photodetector for detecting reflected light, an objective lens serving as an output end of the laser light, and a laser recording light are irradiated onto the disk recording surface via the objective lens. An optical system (not shown) for guiding the reflected light to the photodetector is formed. The laser diode outputs, for example, a so-called blue laser having a wavelength of 405 nm. The NA by the optical system is 0.85.

The objective lens is held in the pickup 51 so as to be movable in the tracking direction and the focus direction by a biaxial mechanism.
The entire pickup 51 can be moved in the radial direction of the disk by a thread mechanism 53.
The laser diode in the pickup 51 is driven to emit laser light by a drive signal (drive current) from the laser driver 63.

Reflected light information from the disk 1 is detected by a photo detector, converted into an electric signal corresponding to the amount of received light, and supplied to the matrix circuit 54.
The matrix circuit 54 includes a current-voltage conversion circuit, a matrix calculation / amplification circuit, and the like corresponding to output currents from a plurality of light receiving elements as photodetectors, and generates necessary signals by matrix calculation processing.
For example, a high frequency signal (reproduction data signal) corresponding to reproduction data, a focus error signal for servo control, a tracking error signal, and the like are generated.
Further, a push-pull signal is generated as a signal related to groove wobbling, that is, a signal for detecting wobbling.
The reproduction data signal output from the matrix circuit 54 is supplied to the reader / writer circuit 55, the focus error signal and tracking error signal are supplied to the servo circuit 61, and the push-pull signal is supplied to the wobble circuit 58.

The reader / writer circuit 55 performs binarization processing, reproduction clock generation processing by PLL, and the like on the reproduction data signal, reproduces data read out as a phase change mark, for example, and supplies the data to the modulation / demodulation circuit 56.
The modem circuit 56 includes a functional part as a decoder at the time of reproduction and a functional part as an encoder at the time of recording.
At the time of reproduction, as a decoding process, a run-length limited code is demodulated based on the reproduction clock.
The ECC encoder / decoder 57 performs ECC encoding processing for adding an error correction code during recording, and ECC decoding processing for performing error correction during reproduction.
At the time of reproduction, the data demodulated by the modulation / demodulation circuit 56 is taken into an internal memory, and error detection / correction processing and deinterleaving processing are performed to obtain reproduction data.
Data decoded up to reproduction data by the ECC encoder / decoder 57 is read based on an instruction from the system controller 60 and transferred to an AV (Audio-Visual) system 120.

The push-pull signal output from the matrix circuit 54 as a signal related to groove wobbling is processed in the wobble circuit 58. The push-pull signal as ADIP information is MSK demodulated and STW demodulated in the wobble circuit 58, demodulated into a data stream constituting an ADIP address, and supplied to the address decoder 59.
The address decoder 59 decodes the supplied data, obtains an address value, and supplies it to the system controller 60.
The address decoder 59 generates a clock by PLL processing using the wobble signal supplied from the wobble circuit 58, and supplies the clock to each unit, for example, as an encode clock during recording.
A configuration for performing MSK demodulation and STW demodulation in the wobble circuit 58 will be described later.

At the time of recording, recording data is transferred from the AV system 120. The recording data is sent to a memory in the ECC encoder / decoder 57 and buffered.
In this case, the ECC encoder / decoder 57 performs error correction code addition, interleaving, subcode addition, and the like as encoding processing of the buffered recording data.
The ECC-encoded data is modulated in the RLL (1-7) PP system (RLL: Run Length Limited, PP: Parity preserve / Prohibit rmtr (repeated minimum transition runlength)) in the modulation / demodulation circuit 56, and the reader / writer This is supplied to the circuit 55.
As described above, the clock generated from the wobble signal is used as the reference clock for the encoding process during recording.

The recording data generated by the encoding process is subjected to a recording compensation process by the reader / writer circuit 55, and fine adjustment of the optimum recording power and adjustment of the laser drive pulse waveform with respect to the recording layer characteristics, laser beam spot shape, recording linear velocity, etc. Etc. are sent to the laser driver 63 as a laser drive pulse.
The laser driver 63 applies the supplied laser drive pulse to the laser diode in the pickup 51 to perform laser emission driving. As a result, pits (phase change marks) corresponding to the recording data are formed on the disc 1.

  The laser driver 63 includes a so-called APC circuit (Auto Power Control), and the laser output is not dependent on the temperature or the like while monitoring the laser output power by the output of the laser power monitoring detector provided in the pickup 51. Control to be constant. The target value of the laser output at the time of recording and reproduction is given from the system controller 60, and the laser output level is controlled to be the target value at the time of recording and reproduction.

The servo circuit 61 generates various servo drive signals for focus, tracking, and thread from the focus error signal and tracking error signal from the matrix circuit 54, and executes the servo operation.
That is, a focus drive signal and a tracking drive signal are generated according to the focus error signal and tracking error signal, and the focus coil and tracking coil of the biaxial mechanism in the pickup 51 are driven. Thus, a pickup 51, a matrix circuit 54, a servo circuit 61, a tracking servo loop and a focus servo loop by a biaxial mechanism are formed.
The servo circuit 61 turns off the tracking servo loop and outputs a jump drive signal in response to a track jump command from the system controller 60, thereby executing a track jump operation.
The servo circuit 61 generates a thread drive signal based on a thread error signal obtained as a low frequency component of the tracking error signal, access execution control from the system controller 60, and the like, and drives the thread mechanism 53. Although not shown, the sled mechanism 53 has a mechanism including a main shaft that holds the pickup 51, a sled motor, a transmission gear, and the like, and by driving the sled motor according to a sled drive signal, a required slide of the pick-up 51 is obtained. Movement is performed.

The spindle servo circuit 62 controls the spindle motor 52 to perform CLV rotation.
The spindle servo circuit 62 obtains the clock generated by the PLL processing for the wobble signal as the current rotational speed information of the spindle motor 52 and compares it with predetermined CLV reference speed information to generate a spindle error signal. .
At the time of data reproduction, the reproduction clock (clock serving as a reference for decoding processing) generated by the PLL in the reader / writer circuit 55 becomes the current rotational speed information of the spindle motor 52, and this is used as a predetermined CLV. A spindle error signal can also be generated by comparing with the reference speed information.
The spindle servo circuit 62 outputs a spindle drive signal generated according to the spindle error signal, and causes the spindle motor 62 to perform CLV rotation.
The spindle servo circuit 62 generates a spindle drive signal in response to a spindle kick / brake control signal from the system controller 60, and executes operations such as starting, stopping, acceleration, and deceleration of the spindle motor 52 .

Various operations of the servo system and the recording / reproducing system as described above are controlled by a system controller 60 formed by a microcomputer.
The system controller 60 executes various processes according to commands from the AV system 120.
For example, when a write command (write command) is issued from the AV system 120, the system controller 60 first moves the pickup 51 to the address to be written. Then, the ECC encoder / decoder 57 and the modulation / demodulation circuit 56 execute the encoding process as described above on the data transferred from the AV system 120 (for example, video data of various systems such as MPEG2 or audio data). Then, recording is executed by supplying the laser drive pulse from the reader / writer circuit 55 to the laser driver 63 as described above.

For example, when a read command for requesting transfer of certain data (such as MPEG2 video data) recorded on the disc 1 is supplied from the AV system 120, seek operation control is first performed for the instructed address. That is, a command is issued to the servo circuit 61 to cause the pickup 51 to access the address specified by the seek command.
Thereafter, operation control necessary for transferring the data in the designated data section to the AV system 120 is performed. That is, data reading from the disk 1 is performed, decoding / buffering and the like in the reader / writer circuit 55, the modem circuit 56, and the ECC encoder / decoder 57 are executed, and the requested data is transferred.

  When recording / reproducing data using these phase change marks, the system controller 60 controls access and recording / reproducing operations using the ADIP addresses detected by the wobble circuit 58 and the address decoder 59.

Incidentally, although the example of FIG. 5 is a disk drive device connected to the AV system 120, the disk drive device of the present invention may be connected to, for example, a personal computer.
Furthermore, there may be a form that is not connected to other devices. In that case, an operation unit and a display unit are provided, and the configuration of the interface part for data input / output is different from that in FIG. That is, it is only necessary that recording and reproduction are performed in accordance with a user operation and a terminal unit for inputting / outputting various data is formed.
Of course, there are various other configuration examples. For example, examples of a recording-only device and a reproduction-only device are also possible.

FIG. 6 shows only a circuit system for demodulating a wobble signal and obtaining ADIP information in the configuration of FIG. As described above, the push-pull signal P / P from the matrix circuit 54 is supplied to the wobble circuit 58. The wobble circuit 58 is provided with an MSK demodulator 10 and an STW demodulator 30. The MSK demodulator 10 demodulates the wobble signal as the push-pull signal P / P and outputs an MSK demodulated signal. The STW demodulator 30 demodulates the wobble signal as the push-pull signal P / P and outputs an STW demodulated signal. The MSK demodulated signal and STW demodulated signal are supplied to the address decoder 59. Then, the ADIP information is decoded by the address decoder 59 and supplied to the system controller 60.

3. MSK demodulator

The configuration of the MSK demodulator 10 shown in FIG. 6 is shown in FIG. This will be described with reference to FIGS.

The push-pull signal P / P as shown in FIG. 8A obtained from the matrix circuit 54 as a wobbling groove modulation signal (wobble signal) is sent to the A / D converter 11 and the comparator 12 in the MSK demodulator 10. Supplied.
The comparator 12 includes an operational amplifier and a comparator amplifier, and binarizes the push-pull signal P / P. Then, the binarized push-pull signal P / P is supplied to the PLL circuit 13.
The PLL circuit 13 generates a push-pull signal P / P based on the binarized signal, that is, a clock (hereinafter referred to as a modulation frequency signal) of the frequency (wobble frequency) of the modulation signal of the wobbling groove, as shown in FIG. Generate. The PLL circuit 13 may be a digital circuit.

The modulation frequency signal output from the PLL circuit 13 is supplied to the PLL circuit 14 and the edge detection circuit 15.
The PLL circuit 14 multiplies the modulation frequency signal to generate a clock CK. This clock CK is used as a sampling clock for the A / D converter 11 and is used by the edge detection circuit 15, the delay circuit 16, and the counter 17. The PLL circuit 14 may also be configured with either an analog circuit or a digital circuit.

The edge detection circuit 15 detects a rising edge of the modulation frequency signal and outputs a detection pulse of the rising edge. This detection pulse becomes information on the reference timing of the wobble frequency signal.
The edge detection circuit 15 may have any configuration as long as it detects a rising edge. For example, the edge detection circuit 15 may include a flip-flop, a resistor, a capacitor, an AND circuit, and the like. A falling edge circuit may be used.

The detection pulse from the edge detection circuit 15 is given a predetermined delay time in units of clock CK by the delay circuit 16. The delay circuit 16 can be constituted by, for example, a shift register and a selector. Of course, other configurations are possible.
The detection pulse via the delay circuit 16 is supplied to the counter 17.
The counter 17 performs an operation of counting the clock CK, but performs count reset at the timing when the detection pulse from the delay circuit 16 is supplied. That is, the counter 17 counts the clock CK from the reset timing by the detection pulse, and outputs the count value to the table group 21 as a table address.
For example, it is assumed that the clock CK has a frequency at which one cycle of the wobble basic waveform is 23 clocks. Since the counter 17 is reset at intervals of one cycle of the wobble basic waveform, the count value of 0 to 22 is repeatedly generated.

The table group 21 has a plurality of (for example, eight in this example) tables as the tables TB0 to TBn. Each of the tables TB0 to TBn is a table (ROM) storing waveform data serving as an internal reference wave, and each data is read according to the count value of the counter 17.
As waveform data of each table TB0 to TBn, for example, 23 data of TD0 to TD22 are stored. As this is sequentially read out according to the count values of 0 to 22, an internal reference wave having the same frequency as the wobble basic waveform is generated as shown in FIG.
However, the waveforms of the internal reference waves stored in the tables TB0 to TBn are waveforms whose phases are shifted little by little. That is, the data TD0 to TD22 of each table TB0 to TBn is data indicating a waveform of one wobble period with the phase shifted. The phase difference between the tables TB0 to TBn will be described later.

  The selection circuit 22 selects one of the tables TB0 to TBn. The selection circuit 22 selects one table based on a control signal from the system controller 60. In each of the tables TB0 to TBn, waveform data serving as an internal reference wave is sequentially output according to the count value from the counter 17, but the internal reference wave from the table TBx selected by the selection circuit 22 is supplied to the multiplier 18. Will be.

The table group 21 generates an internal reference wave. However, as long as it outputs waveform data, the table group 21 may have a configuration other than the table group, may be configured by a combinational circuit, or may sequentially form a data string. An output shift register may be employed.
The counter 17, the table group 21, and the selection circuit 22 are one example of a configuration that generates an internal reference wave in various phase states as will be described later. However, the configuration is limited if the same operation is performed. Alternatively, for example, a configuration in which the counter 17 is operated not by increasing / decreasing 1 but by increasing / decreasing n by setting from the system controller 60, for example, and combining the n tables into one table is conceivable.

On the other hand, the input push-pull signal P / P is sampled by the A / D converter 11 with the clock CK, converted into digital data, and supplied to the multiplier 18.
In the multiplier 18, the modulation signal data from the A / D converter 11 and the internal reference wave data from the table TBx selected by the selection circuit 22 are multiplied. This multiplication value is, for example, as shown in FIG. The multiplied value is supplied to the adder 19 and integrated. The adder 19 is reset by the detection pulse from the delay circuit 16. That is, the adder 19 is reset at the same timing as the counter 17. Therefore, in the adder, multiplication values are integrated during one wobble basic waveform period. For example, the operation of integrating the multiplication results of 23 samples is repeated.
Then, the integrated value (added value after multiplication) changes as shown in FIG. The output of such an adder 19 is positive / negative determined by a positive / negative determination circuit 20, and the determination result becomes an MSK demodulated signal.
When the adder 19 outputs an integrated value in 2's complement expression, the positive / negative determination circuit 20 may be configured to output the most significant bit. Of course, as long as it can determine the positive / negative of a numerical value, other things may be used, and a comparator circuit may be used for positive / negative determination.

As can be seen from FIG. 8, the added value after multiplication shifts in the positive direction in the wobble fundamental wave section of the input modulation signal. On the other hand, the added value after multiplication shifts in the negative direction in the section of the MSK mark. Therefore, a demodulated signal for discriminating between the MSK mark and the fundamental wave can be obtained by determining whether this is positive or negative.
FIG. 8 shows a state in which the push-pull signal P / P supplied to the multiplier 18 is in phase with the internal reference wave. That is, the best demodulation result is obtained when the phases match. On the other hand, FIG. 9 shows a case where the phases of the push-pull signal P / P and the internal reference wave are shifted, but as described above, in this case, the demodulation accuracy deteriorates.

Therefore, in this example, in addition to the phase adjustment by the delay circuit 16, the table TB0 to TBn is selected for the internal reference wave, so that a finer phase adjustment can be performed.
As described above with reference to FIG. 19, the phase adjustment performed by changing the delay time of the delay circuit 16 and changing the reset timing of the counter 17 in a state where a certain table TBx is selected is 1 clock. Adjustment is in units. When one wobble period is 23 clock periods, the phase of the internal reference wave can be adjusted in units of 1/23 period. For example, FIG. 12 shows a state in which the phase can be adjusted in 1/23 period units by adjusting the delay time as an internal reference wave output from a certain table TBx.
If the phase of the input push-pull signal P / P is a waveform that always crosses zero at the position of the clock CK, there is no problem with the phase adjustment by the delay circuit 16, but depending on the internal operation clock sampling timing due to the delay of the circuit operation, etc. The phase may shift. When the operating frequency is lowered, the sampling interval is increased and the phase difference is increased. Therefore, it is necessary to perform a finer phase adjustment than the clock unit.

In order to perform phase adjustment finer than the clock unit in this way, the tables TB0 to TBn are internally shifted in phase in units of 1/8 period of one clock period by eight tables TB0 to TB7, for example, TBn = TB7. A reference waveform is prepared.
FIG. 10 shows an example of waveform data stored in each table TB0 to TB7. As shown in the figure, the data stored in each of the tables TB0 to TB7 is data whose phase is shifted by 1/8 clock period. In particular, the portion of broken line S in FIG. 10 is enlarged and shown in FIG. 11, but as clearly shown in FIG. 11, each table TB0-TBn has a phase shifted within the sampling interval by the clock CK. Data TD is set.

  That is, by selecting one table in the table group 21 by the selection circuit 22, finer phase adjustment is possible. In other words, when eight tables TB0 to TB7 are provided, the phase adjustment can be realized with the same accuracy as when the sampling frequency is increased by 8 times without increasing the sampling frequency.

The number of tables can be calculated as follows.
Number of tables = (1/2) · 2 ^ADB × Sin (2π / S)
However, ADB is the number of bits of the A / D converter 11, and S is the number of samples in one cycle of the input signal.
For example, when the number of bits of the A / D converter 11 is 6 bits and the number of samples in one cycle of the input signal is 23 as described above, the number of tables according to the above formula is 8.6, and the number of tables is 8 to 8. Nine can be said to be appropriate.

The phase adjustment is performed by the system controller 60 controlling the delay amount of the delay circuit 16 and the selection operation of the selection circuit 22.
For example, the control signal for phase adjustment is output as an 8-bit value. The delay circuit 16 is given a control value of upper 5 bits in order to adjust the delay time between 23 clocks. Also for the selection circuit 22 to indicate one of the eight tables, providing a control value of the lower 3 bits.

The process of actually adjusting the internal reference wave to the optimum phase state is performed as shown in FIG. 13, for example.
In step F101, the delay amount of the delay circuit 16 is set to an initial value. In step F102, the ADIP reproduction operation is executed in that state, the demodulation error rate is acquired from the address decoder 59, and stored in correspondence with the current delay amount setting value.
For example, the processing of steps F101 and F102 is repeated while returning from step F103 to F101. That is, 23 delay amounts are sequentially set, and an error rate is obtained for each. When the error rate can be stored corresponding to each of the 23 delay amounts, the process proceeds from step F103 to step F104 to determine the optimum delay amount. That is, the best delay amount as the error rate is determined, and the delay amount of the delay circuit 16 is determined.

Subsequently, in a state where the delay amount is set to the optimum value, the process proceeds to processing for sequentially selecting the tables TB0 to TBn. That is, one of the tables 21 is selected in step F105, and in that state, an ADIP reproduction operation is executed in step F106, the demodulation error rate is acquired from the address decoder 59, and stored in correspondence with the current table. . This process is repeated while returning from step F107 to F105. That is, the error rate is acquired while selecting each of the eight tables TB0 to TB7.
When the error rates can be stored for all the tables TB0 to TB7, the process proceeds to step F108, and an optimum table is set. That is, the table with the best error rate is determined.

By setting the delay amount and the table in this manner, the internal reference wave supplied to the multiplier 18 is adjusted to the optimum phase state with respect to the modulation signal supplied to the multiplier 18, that is, the most in phase. Will be.
That is, according to this example, the phase of the internal reference wave can be accurately adjusted without increasing the sampling frequency, thereby improving the MSK demodulation accuracy.
Normally, once such adjustment is performed at the manufacturing stage of the disk drive device, the adjustment state may be fixed thereafter. This is because, in particular, the phase shift of the input signal with respect to the clock timing is due to the characteristics of the elements of the circuit, and therefore the phase shift amount to be adjusted in the tables TB0 to TBn is almost fixed.
However, of course, the demodulation performance may be deteriorated due to phase shift due to various circumstances, and in order to cope with this, it is possible to appropriately adjust as shown in FIG.

4). STW demodulator

Next, the STW demodulator 30 shown in FIG. 6 will be described. The STW demodulator 30 basically performs STW demodulation with substantially the same configuration as the MSK demodulator 10. FIG. 14 shows the configuration of the STW demodulator 30. This will be described with reference to FIGS.

The push-pull signal P / P as shown in FIG. 15A obtained from the matrix circuit 54 described above as the STW modulation signal of the wobbling groove is supplied to the A / D converter 31 and the comparator 32 in the STW demodulator 30. .
The comparator 32 binarizes the push-pull signal P / P and supplies it to the PLL circuit 33.
The PLL circuit 33 generates a wobble frequency clock (modulation frequency signal) based on the binarized signal as shown in FIG.

The modulation frequency signal output from the PLL circuit 33 is supplied to the PLL circuit 34 and the edge detection circuit 35.
The PLL circuit 34 multiplies the modulation frequency signal to generate a clock CK. This clock CK is used as a sampling clock for the A / D converter 31 and is used by the edge detection circuit 35, the delay circuit 36, and the counter 37.
The edge detection circuit 35 detects the rising edge of the modulation frequency signal and outputs a detection pulse of the rising edge. This detection pulse becomes information on the reference timing of the wobble frequency signal.

A detection pulse from the edge detection circuit 35 is given a predetermined delay time in units of clock CK by the delay circuit 36.
The detection pulse via the delay circuit 36 is supplied to the counter 37.
The counter 37 performs an operation of counting the clock CK, but performs count reset at the timing when the detection pulse from the delay circuit 36 is supplied. That is, the counter 37 counts the clock CK from the reset timing by the detection pulse, and outputs the count value to the table group 41 as a table address.
For example, it is assumed that the clock CK has a frequency at which one cycle of the wobble basic waveform is 23 clocks. Since the counter 37 is reset at intervals of one cycle of the wobble basic waveform, the count value of 0 to 22 is repeatedly generated.

The table group 41 includes a plurality of (for example, 16 in this example) tables as the tables TB0 to TBn. Each of the tables TB0 to TBn is a table (ROM) storing waveform data serving as an internal reference wave, and each data is read according to the count value of the counter 37.
As waveform data of each table TB0 to TBn, for example, 23 data of TD0 to TD22 are stored. As this is sequentially read according to the count values of 0 to 22, an internal reference wave that is the second harmonic of the wobble basic waveform is generated as shown in FIG.
However, the waveforms of the internal reference waves stored in the tables TB0 to TBn are waveforms whose phases are shifted little by little. That is, the data TD0 to TD22 of each table TB0 to TBn is data indicating a waveform of one wobble period with the phase shifted.

  The selection circuit 42 selects one of the tables TB0 to TBn. The selection circuit 42 selects one table based on a control signal from the system controller 60. Each table TB0 to TBn sequentially outputs waveform data as an internal reference wave according to the count value from the counter 37, but the internal reference wave from the table TBx selected by the selection circuit 42 is supplied to the multiplier 38. Will be.

On the other hand, the input push-pull signal P / P is sampled by the A / D converter 31 with the clock CK, converted into digital data, and supplied to the multiplier 38.
The multiplier 38 multiplies the modulation signal data from the A / D converter 31 and the internal reference wave data from the table TBx selected by the selection circuit 42. This multiplication value is, for example, as shown in FIG. The multiplication value is supplied to the adder 39 and integrated. The adder 39 is controlled to the enable state by the STW area signal from the subsequent address decoder 59. Further, the edge of the STW area signal is detected by the edge detection circuit 43 and cleared by the edge detection signal.
In other words, in this case, the adder 39 is controlled so as to accumulate the multiplication values within the range of the STW modulation signal of the ADIP unit shown in FIG. 3B, for example, and is reset for each ADIP unit. For example, integration is performed in the section of wobble numbers 18 to 54.
Then, the integrated value (added value after multiplication) changes as shown in FIG. The output of such an adder 19 is positive / negative determined by the positive / negative determination circuit 40, and the determination result becomes an STW demodulated signal.

As can be seen from FIG. 15, the added value after multiplication changes in the positive direction in the STW modulated wave section of “1” value in the input modulation signal. On the other hand, the post-multiplication addition value shifts in the negative direction in the STW modulated wave section of “0” value. In the monotone wobble section, it moves at almost zero level. Therefore, an STW demodulated signal can be obtained by determining whether this is positive or negative.
FIG. 15 shows a state in which the push-pull signal P / P supplied to the multiplier 38 and the phase of the internal reference wave (second harmonic) match. That is, the best demodulation result is obtained when the phases match. On the other hand, FIG. 16 shows a similar waveform. FIG. 16 shows a case where the phases of the push-pull signal P / P and the internal reference wave are shifted. In this case, as can be seen from FIG. 16 (e), the transition of the addition value after multiplication becomes ambiguous, and accurate positive / negative determination becomes difficult, and demodulation accuracy deteriorates.

Therefore, in this example, in addition to the phase adjustment by the delay circuit 36, the table TB0 to TBn is selected for the internal reference wave so that a finer phase adjustment can be performed.
Since it is basically the same as the case of the MSK demodulator 10, detailed description is omitted. In this case, 16 tables (TB0 to TB15) are prepared as the tables TB0 to TBn.
The tables TB0 to TB15 prepare an internal reference wave system as a second harmonic whose phase is shifted in units of 1/16 period of one clock period.
FIG. 17 shows the state of the phase-shifted waveforms of the tables TB0 to TB15 in the vicinity of the zero cross as in FIG. That is, in each table TB0 to TB15, the respective data TD is set so that the phase is shifted within the sampling interval by the clock CK.

In this case, the number of tables is
Number of tables = (1/2) · 2 ^ADB × Sin (4π / S)
It can be calculated with Also in this case, ADB is the number of bits of the A / D converter 31, and S is the number of samples in one cycle of the input signal. Then, for example, when the number of bits of the A / D converter 31 is 6 bits and the number of samples in one cycle of the input signal is 23 as described above, about 16 tables are appropriate.
In the case of the MSK demodulator 10, the selection circuit 42 selects one of the tables 41 in the table group 41, so that in addition to the phase adjustment in the delay circuit 36, finer phase adjustment is possible. It is the same. That is, also in this case, high-accuracy phase adjustment can be realized without increasing the sampling frequency, and thus STW demodulation performance can be improved.
The phase adjustment is performed by the system controller 60 controlling the delay amount of the delay circuit 36 and the selection operation of the selection circuit 42. In this case as well, the phase adjustment may be performed according to the procedure shown in FIG.
The configuration of the STW demodulator 30 and the phase adjustment operation timing can be variously considered as in the case of the MSK demodulator 10.

5. Effects and modifications of the embodiment

As can be seen from the above description, in this embodiment, in the MSK demodulator 10 and the STW demodulator 30 that perform demodulation by calculating the internal reference wave on the input modulated signal wave, 1 is used as the table TB of the internal reference wave. A plurality of tables (numerical tables) whose phases are changed within a clock cycle are provided, and one of the tables TB0 to TBn can be selected. As a result, even if there is a difference between the phase of the clock that generates the internal reference wave and the input modulation signal, the phase of the internal reference wave is adjusted so that the phase difference is eliminated, and the waveform with the same phase is demodulated. Therefore, there is an effect that even a noisy input signal (modulated signal) can be correctly demodulated.
In particular, in the operation at a high transfer rate in the disk drive device, when the circuit operating frequency cannot be increased with the high-speed rotation of the disk, the sampling interval inevitably becomes relatively sparse, crosstalk from adjacent tracks, Decrease in reflectivity Wobble signal deteriorates and MSK demodulated data and STW demodulated data tend not to be read correctly. However, according to this example, the resolution of phase adjustment can be increased without increasing the clock frequency. Can be demodulated sufficiently, and the address can be read correctly. Furthermore, this also has the advantage that the dead time until the address information is correctly read out is shortened, and that recording / reproducing can be performed stably even on recording / reproducing media having large variations.
Further, the wobble address demodulation capability can be maintained even when the characteristics of the pickup 51 are varied by appropriate phase adjustment, so that the yield of the pickup 51 can be improved.

Various modifications may be considered for the circuit configurations of the MSK demodulator 10 and the STW demodulator 30, the phase adjustment method procedure, and the like.
For example, in the MSK demodulator 10 of FIG. 7 and the STW demodulator 30 of FIG. 14, both the A / D converter (11, 31), the comparator (12, 32), the PLL circuit (13, 33), the PLL circuit (14, 34). However, these are not necessarily provided separately in both the MSK demodulator 10 and the STW demodulator 30, and may be a circuit system shared by both demodulators.
Further, the table TB in the table groups 21 and 41 may store either data of the cosine waveform or the sin waveform.
Further, the phase adjustment procedure is not limited to the example of FIG. For example, ADIP reproduction may be performed with all combinations of delay time adjustment and table selection, and the combination that optimizes the error rate may be determined.
Also, in the above example, an example of an information demodulating device using a wobbling groove of a phase change recording disk is given. However, the present invention is not limited to a wobbling groove of a disk of another recording system such as a dye film changing system or a magneto-optical recording system. It can also be applied to demodulation.
In addition, the phase adjustment method shown in this example can be applied to various devices because it can obtain a resolution higher than the clock frequency. That is, it can be applied not only to the wobble address demodulation of an optical disc as described above, but also to a signal transmission demodulator using MSK modulation or STW modulation.

It is explanatory drawing of the wobbling groove of a disk. It is explanatory drawing of the MSK modulation wave and STW modulation wave of a wobble signal. It is explanatory drawing of an ADIP unit. It is explanatory drawing of ADIP information formed from an ADIP unit. 1 is a block diagram of a disk drive device according to an embodiment. It is a block diagram of a wobble demodulation system of the disk drive device of the embodiment. It is a block diagram of the MSK demodulator of an embodiment. It is explanatory drawing of a MSK demodulation waveform. It is explanatory drawing of the MSK demodulation waveform in the case of a phase shift. It is explanatory drawing of the phase adjustment by the table selection of embodiment. It is explanatory drawing of the phase of each table of embodiment. It is explanatory drawing of the phase adjustment by the delay time of embodiment. It is a flowchart of the phase adjustment process of embodiment. It is a block diagram of the STW demodulator of the embodiment. It is explanatory drawing of a STW demodulation waveform. It is explanatory drawing of the STW demodulation waveform in the case of a phase shift. It is explanatory drawing of the phase of each table of embodiment. It is a block diagram of the conventional demodulation circuit. It is explanatory drawing of the phase adjustment by delay time.

Explanation of symbols

  1 disk, 10 MSK demodulator, 11, 31 A / D converter, 12, 32 comparator, 13, 33, 14, 34 PLL circuit, 15, 35, 43 edge detection circuit, 16, 36 delay circuit, 17, 37 Counter, 18, 38 Multiplier, 19, 39 Adder, 20, 40 Positive / negative judgment circuit, 21, 41 Table group, 22, 42 selection circuit, 30 STW demodulator, 51 Pickup, 52 Spindle motor, 53 Thread mechanism, 54 Matrix circuit, 55 reader / writer circuit, 56 modulation / demodulation circuit, 57 ECC encoder / decoder, 58 wobble circuit, 59 address decoder, 60 system controller, 61 servo circuit, 62 spindle servo circuit, 63 laser driver, 120 AV system

Claims (10)

A signal generating means for generating a modulation frequency signal and a clock signal obtained by multiplying the modulation frequency signal based on the input modulation signal;
A / D conversion means for sampling the input modulation signal with the clock signal and outputting modulation signal data as digital data;
A reference timing signal generating means for generating a reference timing signal based on the modulation frequency signal, and delaying the reference timing signal in units of the clock signal;
An internal reference wave generating means capable of generating a plurality of internal reference waves having different phases within a range of one clock cycle of the clock signal with reference to the reference timing signal;
Selecting means for selecting one of a plurality of internal reference waves by the internal reference wave generating means;
Demodulating means for multiplying the data of the internal reference wave selected by the selecting means and the modulated signal data output from the A / D converting means, and obtaining a demodulated signal from a value obtained by integrating the multiplication results;
The optimal delay time is determined by acquiring the evaluation value of the demodulation operation while gradually changing the delay time in the reference timing signal generation means, and the delay time is set. With the delay time set, an optimum internal reference wave is obtained by acquiring an evaluation value of the demodulation operation while sequentially selecting each of a plurality of internal reference waves by the internal reference wave generating means by the selecting means. By determining and setting the selection means to the optimal internal reference wave selection state, the phase adjustment means for adjusting the phase of the internal reference wave,
A demodulating device comprising: The internal reference wave generating means is
A counter that is reset by the reference timing signal from the reference timing signal generation means and counts at the clock signal timing;
A plurality of tables each holding data of an internal reference wave having a different phase within the range of one clock cycle of the clock signal, and each outputting data specified by a count value from the counter; ,
And consisting of
2. The demodulator according to claim 1, wherein the selecting means is configured to select one of the plurality of tables. The modulation signal is an MSK modulation signal,
2. The demodulator according to claim 1, wherein the internal reference wave generating means outputs an internal reference wave having the same frequency as the reference wave of the MSK modulation signal. The modulation signal is an STW modulation signal,
2. The demodulator according to claim 1, wherein the internal reference wave generating means outputs an internal reference wave that is a second harmonic of the reference wave of the STW modulation signal. Reading means for reading the modulation signal recorded as a wobbling groove on the disk recording medium;
A signal generating means for generating a modulation frequency signal and a clock signal obtained by multiplying the modulation frequency signal based on the modulation signal read by the reading means;
A / D conversion means for sampling the modulation signal read by the reading means with the clock signal and outputting modulation signal data as digital data;
A reference timing signal generating means for generating a reference timing signal based on the modulation frequency signal, and delaying the reference timing signal in units of the clock signal;
An internal reference wave generating means capable of generating a plurality of internal reference waves having different phases within a range of one clock cycle of the clock signal with reference to the reference timing signal;
Selecting means for selecting one of a plurality of internal reference waves by the internal reference wave generating means;
Demodulating means for multiplying the data of the internal reference wave selected by the selecting means and the modulated signal data output from the A / D converting means, and obtaining a demodulated signal from a value obtained by integrating the multiplication results;
The optimal delay time is determined by acquiring the evaluation value of the demodulation operation while gradually changing the delay time in the reference timing signal generation means, and the delay time is set. With the delay time set, an optimum internal reference wave is obtained by acquiring an evaluation value of the demodulation operation while sequentially selecting each of a plurality of internal reference waves by the internal reference wave generating means by the selecting means. By determining and setting the selection means to an optimal internal reference wave selection state, phase adjustment means for adjusting the phase of the internal reference wave; and
Decoding the demodulated signal demodulated by the demodulating means to obtain information recorded as the wobbling groove;
A disk drive device comprising:   6. The disk drive device according to claim 5, wherein the decoding means obtains address information on the disk recording medium as information recorded as the wobbling groove. The internal reference wave generating means is
A counter that is reset by the reference timing signal from the reference timing signal generation means and counts at the clock signal timing;
A plurality of tables each holding data of an internal reference wave having a different phase within the range of one clock cycle of the clock signal, and each outputting data specified by a count value from the counter; ,
And consisting of
6. The disk drive device according to claim 5, wherein the selection means is configured to select one of the plurality of tables. The modulation signal read by the reading means is an MSK modulation signal,
6. The disk drive apparatus according to claim 5, wherein the internal reference wave generating means outputs an internal reference wave having the same frequency as the reference wave of the MSK modulation signal. The modulation signal read by the reading means is an STW modulation signal,
6. The disk drive device according to claim 5, wherein the internal reference wave generating means outputs an internal reference wave that is a second harmonic of the reference wave of the STW modulation signal. A signal generating means for generating a modulation frequency signal and a clock signal obtained by multiplying the modulation frequency signal based on the input modulation signal;
A / D conversion means for sampling the input modulation signal with the clock signal and outputting modulation signal data as digital data;
A reference timing signal generating means for generating a reference timing signal based on the modulation frequency signal, and delaying the reference timing signal in units of the clock signal;
An internal reference wave generating means capable of generating a plurality of internal reference waves having different phases within a range of one clock cycle of the clock signal with reference to the reference timing signal;
Selecting means for selecting one of a plurality of internal reference waves by the internal reference wave generating means;
Demodulating means for multiplying the data of the internal reference wave selected by the selecting means and the modulated signal data output from the A / D converting means, and obtaining a demodulated signal from a value obtained by integrating the multiplication results;
As a method for adjusting the phase of the internal reference wave in the demodulator provided with
A delay time setting step of acquiring an evaluation value of a demodulation operation while changing the delay time in the reference timing signal generation means stepwise, and determining and setting an optimal delay time;
While the optimum delay time is set, the evaluation value of the demodulation operation is obtained while sequentially selecting each of the plurality of internal reference waves by the internal reference wave generating means, and the optimum internal reference wave is determined. , An internal reference wave selection step for setting the selection means to an optimal internal reference wave selection state;
A phase adjustment method comprising:

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