JP2010049746A - Demodulating apparatus, demodulating method, information reproducing apparatus, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a demodulating apparatus which performs sufficient demodulation even when phase fluctuation occurs due to crosstalk from an adjacent track, and reduces an address error rate. <P>SOLUTION: The demodulating apparatus has a carrier generation circuit that generates and outputs a carrier with respect to a predetermined modulation signal included in an input signal, a multiplier that multiplies the input signal by the carrier and outputs the result, an adder that adds the output of the multiplier for a predetermined period and outputs the result, a slice level adjusting section that adds or subtracts a predetermined offset value to or from the output of the adder and outputs the result, and a positive and negative determination circuit that determines positive or negative of the output of the slice level adjusting section and outputs the determination result. The slice level adjusting section determines the predetermined offset value using at least a minimum value of the output of the adder. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a demodulation device, a demodulation method, an information reproducing device, and a computer program.

  As a technique for recording / reproducing digital data, for example, data using an optical disk (including a magneto-optical disk) such as a CD (Compact Disk), an MD (Mini Disk), and a DVD (Digital Versatile Disk) as a recording medium. There is a recording technology. In recent years, the density and capacity of such optical discs are increasing, and they are widely used for recording / reproducing high-definition video data.

  In order to record data on such an optical disc, guidance means for tracking the data track is required. As such guiding means, a method is used in which a groove is formed in advance as a pre-groove, and the groove or land (a section plate-like portion sandwiched between the groove and the groove) is used as a data track. It is also necessary to record address information so that data can be recorded at a predetermined position on the data track. Such address information is recorded by wobbling (meandering) the groove.

  A track for recording data is formed in advance as a pregroove, for example, and the side wall of the formed pregroove is wobbled corresponding to the address information. In this way, an address can be read from wobbling information obtained as reflected light information at the time of recording or reproduction. For example, even if pit data indicating the address is not formed on the track in advance, the address can be read. The data can be recorded and reproduced at the position.

  By adding address information as a wobbling groove in this way, for example, it becomes unnecessary to provide an address area discretely on a track and record an address as, for example, pit data. Recording capacity can be increased. The absolute time (address) information expressed by such a wobbled groove is called ATIP (Absolute Time In Pregroove) or ADIP (Address In Pregroove).

  Among optical disks, there is an optical disk in which a groove is wobbled based on a modulation waveform obtained by combining MSK modulation and STW modulation. The MSK modulation has a modulation index of 0.5 among FSK modulations in which phases are continuous. STW modulation is a modulation method that generates a modulation waveform such as a sawtooth waveform by adding or subtracting twice the harmonics to the wobble fundamental wave. In a disk drive device that reproduces information recorded on such an optical disk, an MSK demodulator and an STW demodulator are mounted to reproduce such ADIP information.

  By the way, the wobble signal fluctuates due to crosstalk from adjacent tracks, a difference in output amplitude before and after recording, disc quality variations, and the like. As a method for avoiding the amplitude change of the wobble, an AGC circuit method and a method for limiting the amplitude of the wobble signal (for example, see Patent Document 1 and Patent Document 2) are considered.

JP-A-11-306686 JP 2002-74660 A

  The wobble signal waveform is affected not only by the amplitude but also by the time axis (phase) direction. In the second wobble (STW) as a method for avoiding this phase disturbance, a reference signal is provided for the purpose of adjusting the phase of the detection basic signal of the demodulator, and phase adjustment is performed. Although a method of adding the STW phase value to the MSK phase adjustment has been devised, there is a problem that the circuit scale becomes large.

  Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to sufficiently demodulate even if the MSK demodulated signal is reduced due to phase fluctuation due to crosstalk from adjacent tracks. Another object of the present invention is to provide a new and improved demodulation device, demodulation method, information reproducing device, and computer program capable of reducing the address error rate.

  In order to solve the above-described problem, according to one aspect of the present invention, a carrier wave generation circuit that generates and outputs a carrier wave for a predetermined modulation signal included in an input signal, and a multiplier that multiplies the input signal by the carrier wave and outputs the result. An adder that adds and outputs the output of the multiplier for a predetermined period, a slice level adjustment unit that adds and subtracts a predetermined offset value to the output of the adder, and a sign of the output of the slice level adjustment unit And a positive / negative determination circuit that determines the above and outputs a determination result, and a slice level adjusting unit determines a predetermined offset value using at least the minimum value of the output of the adder.

  According to such a configuration, the carrier wave generation circuit generates and outputs a carrier wave for a predetermined modulation signal included in the input signal, the multiplier multiplies the input signal by the carrier wave, and the adder outputs the output of the multiplier. The period is added and output. The slice level adjustment unit adds or subtracts a predetermined offset value to the output of the adder and outputs the result. The positive / negative determination circuit determines whether the output of the slice level adjustment unit is positive or negative and outputs a determination result. Then, the slice level adjustment unit determines a predetermined offset value using at least the minimum value of the output of the adder. As a result, by determining the predetermined offset value using at least the minimum value of the output from the adder, even if the MSK demodulated signal is reduced, it can be demodulated sufficiently and the address error rate can be reduced.

  The slice level adjusting unit may use an average value of the maximum value and the minimum value of the output of the adder as a predetermined offset value. In this case, when the average value of the maximum value and the minimum value of the adder is far from the center value of the demodulated wave, the slice level adjustment unit may set a predetermined offset value in the away direction. Good.

  The slice level adjustment unit may use a value obtained by adding a predetermined amount in consideration of the demodulation error rate to the minimum value of the adder output as the predetermined offset value.

  In order to solve the above problems, according to another aspect of the present invention, a carrier wave generating step for generating and outputting a carrier wave for a predetermined modulation signal included in an input signal, and multiplying the input signal by the carrier wave for output An addition step for adding the output of the multiplication step for a predetermined period and outputting the result, a slice level adjustment step for adding or subtracting a predetermined offset value to the output of the addition step, and a slice level adjustment step. And a positive / negative determination step that determines whether the output is positive or negative and outputs a determination result, and the slice level adjustment step provides a demodulation method that determines a predetermined offset value using at least the minimum value of the output of the addition step. The

  In order to solve the above problems, according to another aspect of the present invention, a carrier wave generation circuit that generates and outputs a carrier wave for a predetermined modulation signal included in an input signal obtained by reading information from a recording medium, and A multiplier that multiplies the input signal by the carrier wave and outputs, an adder that adds and outputs the output of the multiplier for a predetermined period, and a slice level that outputs by adding or subtracting a predetermined offset value to the output of the adder An adjustment unit, and a positive / negative determination circuit that determines whether the output of the slice level adjustment unit is positive or negative and outputs a determination result. The slice level adjustment unit uses at least a minimum value of the output of the adder to determine a predetermined offset value An information reproducing apparatus is provided for determining

  In order to solve the above problems, according to another aspect of the present invention, a carrier wave generating step for generating and outputting a carrier wave for a predetermined modulation signal included in an input signal, and multiplying the input signal by the carrier wave for output An addition step for adding the output of the multiplication step for a predetermined period and outputting the result, a slice level adjustment step for adding or subtracting a predetermined offset value to the output of the addition step, and a slice level adjustment step. A computer program for causing a computer to execute a positive / negative determination step for determining whether the output is positive or negative and outputting a determination result, wherein the slice level adjustment step determines a predetermined offset value using at least the minimum value of the output of the addition step Is provided.

  As described above, according to the present invention, it is possible to sufficiently demodulate even if the MSK demodulated signal is reduced due to phase fluctuations due to crosstalk from adjacent tracks, and to improve the address error rate. Demodulated apparatus, demodulated method, information reproducing apparatus, and computer program can be provided.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

Further, preferred embodiments of the present invention will be described in detail according to the following order.
[1] First embodiment of the present invention [2] Second embodiment of the present invention [3] Third embodiment of the present invention [4] Fourth embodiment of the present invention

[1] First Embodiment of the Present Invention <Configuration of Optical Disc Device>
First, an optical disk device according to a first embodiment of the present invention will be described. FIG. 1 is an explanatory diagram for explaining the configuration of an optical disc apparatus 100 according to the first embodiment of the present invention. Hereinafter, the configuration of the optical disc apparatus 100 according to the first embodiment of the present invention will be described with reference to FIG.

  The optical disc apparatus 100 shown in FIG. 1 records information on the recording surface of the optical disc 1 and reads information recorded on the recording surface of the optical disc 1 from the recording surface of the optical disc 1 and reproduces it. is there. Examples of the optical disc 1 include DVD-R, Blu-ray Disc (registered trademark), and other optical discs that can be recorded / reproduced.

  As shown in FIG. 1, the optical disc apparatus 100 according to the first embodiment of the present invention includes a spindle servo circuit 102, a spindle driver 104, a spindle motor 106, an optical block servo circuit 108, and a thread driver 110. , Thread mechanism 112, biaxial driver 114, optical block 116, laser power control unit 118, recording pulse conversion circuit 120, ECC encoder / decoder 122, matrix circuit 124, PLL circuit 126, and data demodulation The circuit 128, the ADIP demodulation circuit 130, the address decoder 132, and the CPU 134 are configured.

  The disk 1 is loaded on a turntable (not shown), and is driven to rotate at a constant linear velocity (CLV) or constant rotation (CAV) by a spindle motor 106 during a recording / reproducing operation. The ADIP information embedded as wobbling of the groove track on the disk 1 is read by the optical block 116. On the disc 1, for example, physical information of the disc is recorded as reproduction-only management information by embossed pits or wobbling grooves, and the information is also read by the optical block 116.

  At the time of data recording on the optical disc 1, user data is recorded on the track as a phase change mark by the optical block 116, and at the time of data reproduction from the optical disc 1, the mark recorded by the optical block 116 is read.

  The optical block 116 is irradiated with laser light on the recording surface of the optical disc 1 through a laser diode serving as a laser light source, a photodetector for detecting reflected light, an objective lens serving as an output end of the laser light, and an objective lens. In addition, an optical system (not shown) for guiding the reflected light to the photodetector is formed. The laser diode outputs, for example, a so-called blue laser having a wavelength of 405 nm. The NA (Numerical Aperture) by the optical system is 0.85.

  The objective lens is held in the optical block 116 so as to be movable in the tracking direction and the focus direction by a biaxial mechanism. The entire optical block 116 can be moved in the disk radial direction by the sled mechanism 112. The laser diode in the optical block 116 is driven to emit laser light by a drive signal (drive current) from the laser power control unit 118.

  Reflected light information from the optical disk 1 is detected by a photodetector inside the optical block 116, converted into an electrical signal corresponding to the amount of received light, and supplied to the matrix circuit 124. The matrix circuit 124 includes a current-voltage conversion circuit, a matrix calculation / amplification circuit, and the like corresponding to output currents from a plurality of light receiving elements as photodetectors, and generates necessary signals by matrix calculation processing.

  For example, the matrix circuit 124 generates a high frequency signal (reproduction data signal) corresponding to reproduction data, a focus error signal for servo control, a tracking error signal, and the like. Further, a push-pull signal is generated as a signal related to groove wobbling, that is, a signal for detecting wobbling. Data signals output from the matrix circuit 124 are supplied to the data demodulation circuit 128, the ADIP demodulation circuit 130, and the PLL circuit 126, respectively.

  The data demodulation circuit 128 performs a run-length limited code demodulation process based on the reproduction clock as a decoding process during reproduction. The demodulated data is supplied to the ECC encoder / decoder 122.

  The ECC encoder / decoder 122 performs an ECC encoding process for adding an error correction code during data recording and an ECC decoding process for performing error correction during data reproduction. At the time of data reproduction, the data demodulated by the data demodulation circuit 128 is taken into an internal memory, and error detection / correction processing, deinterleaving processing, and the like are performed to obtain reproduced data. The data decoded up to the reproduction data by the ECC encoder / decoder 122 is read based on an instruction from the CPU 134 and transferred to a subsequent system (not shown).

  The push-pull signal output from the matrix circuit 124 as a signal related to the wobbling of the groove is digitized to become wobble data. The wobble data is MSK demodulated and STW demodulated by the ADIP demodulating circuit 130, and a data stream constituting an ADIP address. And is supplied to the address decoder 132. The address decoder 132 decodes the supplied data, obtains an address value, and supplies the address value to the CPU 134.

  When data is recorded on the optical disk 1, the recording data is transferred from a system (not shown). The recording data is sent to a memory in the ECC encoder / decoder 122 and buffered. In this case, the ECC encoder / decoder 122 performs error correction code addition, interleaving, subcode addition, and the like as encoding processing of the buffered recording data. Further, the data encoded by the ECC encoder / decoder 122 is subjected to RLL (1-7) PP method (RLL: Run Length Limited, PP: Parity Preserve / Prohibit trmtr (repeated minimum transition run length)) modulation in the recording pulse conversion circuit 120. Is done. Note that a clock generated from a wobble signal is used as an encode clock serving as a reference clock for the encoding process during data recording.

  The recording data generated by the encoding process in the recording pulse conversion circuit 120 is subjected to a recording compensation process by the laser power control unit 118 as a recording compensation process. The optimum recording power for the recording layer characteristics, laser beam spot shape, recording linear velocity, etc. Adjustment and adjustment of the laser drive pulse waveform are performed. Then, the laser power control unit 118 gives the laser drive pulse subjected to the recording compensation process to the laser diode in the optical block 116 to execute the laser emission drive. As a result, pits (phase change marks) corresponding to the recording data are formed on the optical disc 1.

  The laser power control unit 118 includes a so-called APC circuit (Auto Power Control), and the laser output power is monitored while the laser output power is monitored by the output of the laser power monitoring detector provided in the optical block 116. Control so that it is constant regardless of. The target value of the laser output at the time of recording and reproduction is given from the CPU 134, and the laser output level is controlled to be the target value at the time of recording and reproduction, respectively.

  The optical block servo circuit 108 generates various servo drive signals for focus, tracking, and thread from the focus error signal and tracking error signal from the matrix circuit 124 and executes the servo operation. That is, the optical block servo circuit 108 generates a focus drive signal and a tracking drive signal according to the focus error signal and the tracking error signal, and drives the focus coil and tracking coil of the biaxial mechanism in the optical block 116 by the biaxial driver 114. Will do. By this driving, an optical block 116, a matrix circuit 124, an optical block servo circuit 108, a biaxial driver 114, a tracking servo loop and a focus servo loop by a biaxial mechanism are formed.

  The optical block servo circuit 108 turns off the tracking servo loop and outputs a jump drive signal in accordance with a track jump command from the CPU 134, thereby executing a track jump operation.

  The optical block servo circuit 108 generates a thread drive signal based on a thread error signal obtained as a low frequency component of the tracking error signal or access execution control from the CPU 134, and drives the thread mechanism 112 by the thread driver 110. Let Although not shown, the sled mechanism 112 has a mechanism including a main shaft that holds the optical block 116, a sled motor, a transmission gear, and the like. The sled mechanism 112 is driven by a sled drive signal according to a sled drive signal. The slide movement is performed.

  The spindle servo circuit 102 controls the spindle motor 106 to perform CLV rotation (Constant Linear Velocity) and CAV rotation (Constant Angular Velocity). The spindle servo circuit 102 obtains the clock generated by the PLL processing for the wobble signal as the current rotational speed information of the spindle motor 106, and compares the rotational speed information with predetermined CLV reference speed information, thereby obtaining a spindle error. Generate a signal.

  At the time of data reproduction, the reproduction clock generated by the PLL circuit 126 (delay processing reference clock) becomes the current rotation speed information of the spindle motor 106, and is compared with predetermined CLV reference speed information. Thus, a spindle error signal can also be generated.

  Then, the spindle servo circuit 102 outputs a spindle drive signal generated according to the spindle error signal, and causes the spindle driver 104 to perform CLV rotation of the spindle motor 106. Further, the spindle servo circuit 102 generates a spindle drive signal in response to a spindle kick / brake control signal from the CPU 134, and executes operations such as starting, stopping, acceleration, and deceleration of the spindle motor 106.

  Various operations of the servo system and the recording / reproducing system as described above are controlled by the CPU 134. The CPU 134 executes various processes according to commands from a system (not shown). For example, when a write command (write command) is sent from the system, the CPU 134 first moves the optical block 116 to an address to be written. Then, the ECC encoder / decoder 122 and the recording pulse conversion circuit 120 cause the encoding process to be performed on the data transferred from the system (for example, video data by MPEG2 or other methods, audio data, etc.) as described above. Then, the laser power control unit 118 controls the laser light emission drive from the optical block 116 according to the encoded data as described above, whereby recording on the optical disc 1 is executed.

  Also, for example, when a read command requesting transfer of data recorded on the optical disk 1 from the system (for example, MPEG2 or other types of video data, audio data, etc.) is sent to the CPU 134, the designated address is first set as the target address. Perform seek operation control as an address. That is, a command is issued to the optical block servo circuit 108, and the access operation of the optical block 116 is executed with the address designated by the seek command as a target. Thereafter, operation control necessary for transferring the data in the designated data section to the system is performed. That is, data reading from the optical disc 1 is performed, decoding / buffering in the matrix circuit 124, the data demodulating circuit 128, and the ECC encoder / decoder 122 is executed, and the requested data is transferred.

  At the time of data recording / reproducing by these phase change marks, the CPU 134 controls access and recording / reproducing operations using the ADIP address detected by the ADIP demodulating circuit 130 and the address decoder 132.

  The configuration of the optical disc apparatus 100 according to the first embodiment of the present invention has been described above with reference to FIG. Next, the configuration of the ADIP demodulator circuit 130 of the optical disc apparatus 100 according to the first embodiment of the present invention will be described. Before entering the description, the MSK used in the Blu-ray Disc (registered trademark) is used. The wobble structure of the optical disc on which the modulation signal and the STW modulation signal are superimposed, and the signal waveforms of the MSK modulation wave and the STW modulation wave will be described.

<Wobble structure of optical disc>
FIG. 2 is an explanatory diagram for explaining the wobble structure of the optical disc 1 on which the MSK modulation signal and the STW modulation signal are superimposed. As shown in FIG. 2, the wobble structure of the optical disc has a structure in which convex lands and concave grooves are alternately formed, and the wobble structure of the optical disc is meandered in the tangential direction. Yes. The meandering shape of the groove is a shape corresponding to the wobble signal. Therefore, in the optical disk apparatus, both edge positions of the groove are detected from the reflected light of the laser spot 2 irradiated to the groove and the laser spot is moved along the recording track in the disk radial direction. The wobble signal can be reproduced by extracting the fluctuation component for.

  In this wobble signal, the address information (physical address and other additional information) of the recording track at the recording position is modulated. Therefore, in the optical disk drive, address control or the like at the time of data recording or reproduction can be performed by demodulating address information or the like from the wobble signal.

<MSK modulation wave waveform>
FIG. 3 is an explanatory diagram for explaining the waveform of the MSK modulated wave. FIG. 3 shows a state in which MSK modulation waveforms (MM1, MM2, MM3) exist in a region of three wobble periods sandwiched between monotone wobbles MW. In FIG. 3, the upper side of the vertical axis corresponds to the inner side of the disc (inner side of disc), and the lower side corresponds to the outer side of the disc (outer side of disc). A non-modulated portion where no data is modulated and only the frequency component of the reference carrier signal appears is referred to as monotone wobble.

  If the monotone wobble is expressed as Cos (ωt) as shown in FIG. 3, one of the two frequencies used for MSK modulation is the same frequency as the reference carrier signal, and the other is 1.5 times the frequency of the reference carrier signal. Therefore, one of the signal waveforms used for MSK modulation is Cos (ωt) or -Cos (ωt), and the other is Cos (1.5ωt) or -Cos (1.5ωt).

  The waveform of the MSK modulation wave shown in FIG. 3 shows two monotone wobbles, an MSK modulation region, and two monotone wobbles. In this case, the signal waveform of the MSK stream is Cos every wobble period. The waveforms are (ωt), Cos (ωt), Cos (1.5ωt), -Cos (ωt), -Cos (1.5ωt), and Cos (ωt). In FIG. 3, monotone wobble Cos (ωt) = cos {2π · (fwob) · t} is shown (fwob is a reference carrier frequency). Therefore, three wobble periods as the MSK modulation region are represented by MM1 = cos {2π · (1.5 · fwob) · t}, MM2 = −cos {2π · (fwob) · t}, MM3 = −cos {2π · (1.5 · fwob · t)}.

  Thus, the first wobble cycle period (MM1) has a frequency 1.5 times that of the monotone wobble, the second (MM2) has the same frequency as the monotone wobble, and the third (MM3) has a frequency of 1.5 of the monotone wobble. The frequency is doubled, and the phase returns in this three wobble period. That is, the phase is continuous with the preceding and following monotone wobbles, and the second wobble (MM2) has a polarity reversed with respect to the monotone wobble.

  In the optical disc 1, address information is modulated into the wobble signal by making the wobble signal into the MSK stream as described above, and this MSK modulated signal can be synchronously detected for the following reason. That is, when the modulated data is inserted into the wobble signal of the optical disc 1 by the MSK modulation method, first, the data stream of the modulated data is differentially encoded in units of clocks corresponding to the wobble period. That is, the difference calculation is performed on the modulated data stream and the delayed data delayed by one period of the reference carrier signal. The data that has been subjected to the differential encoding processing is referred to as pre-coded data. Subsequently, the precoded data is MSK modulated to generate the MSK stream as described above.

  In the differentially encoded data (precode data), a bit is set at the sign change point of the modulated data (becomes “1”). Since the code length of the modulated data is at least twice the wobble period, the reference carrier signal (Cos (ωt)) or its inverted signal (−Cos (ωt) is always included in the latter half of the code length of the modulated data. )) Will be inserted. When the bit of the precode data is “1”, a waveform having a frequency 1.5 times that of the reference carrier signal is inserted, and the waveform is connected in phase at the sign switching point. Therefore, the signal waveform inserted in the latter half of the code length of the modulated data is always the reference carrier signal waveform (Cos (ωt)) if the modulated data is “0”, and the modulated data is “1”. If so, the inverted signal waveform (-Cos (ωt)) is always obtained. The synchronous detection output has a positive value if the phase is in phase with the carrier signal, and a negative value if the phase is inverted. Therefore, the MSK modulated signal as described above is used as the reference carrier. If synchronous detection is performed using a signal, the modulated data can be demodulated.

<Waveform of STW modulation wave>
FIG. 4 is an explanatory diagram showing the waveform of the STW modulated wave. STW modulation is a modulation method that modulates a digital code by adding an even-order harmonic signal to a sine wave carrier signal and changing the polarity of the harmonic signal according to the code of the modulated data. . Also in FIG. 4, the upper side of the vertical axis corresponds to the inner side of the disc (inner side of disc), and the lower side corresponds to the outer side of the disc (outer side of disc). In the optical disc 1, the carrier signal of STW modulation is a signal having the same frequency and phase as the reference carrier signal (Cos (ωt)), which is the carrier signal of MSK modulation. The even-order harmonic signals to be added are Sin (2ωt) and −Sin (2ωt), which are the second-order harmonics of the reference carrier signal (Cos (ωt)), and the amplitude thereof is relative to the amplitude of the reference carrier signal. The amplitude is −12 dB. The minimum code length of the modulated data is set to twice the wobble period (period of the reference carrier signal). Then, when the code of the modulated data is “1”, Sin (2ωt) is added to the carrier signal, and when it is “0”, modulation is performed by adding −Sin (2ωt) to the carrier signal. The waveform when the wobble signal is modulated in this way is the waveform shown in FIG.

  The signal waveform of the monotone wobble MW of the reference carrier signal (Cos (ωt)) is shown in the center wobble period. In the previous two wobble periods, a signal waveform in which Sin (2ωt) is added to the reference carrier signal (Cos (ωt)), that is, a signal waveform when the modulated data is “1” is shown. Yes. Further, in the two wobble period after the monotone wobble MW, a signal waveform in which −Sin (2ωt) is added to the reference carrier signal (Cos (ωt)), that is, a signal waveform when the modulated data is “0”. Is shown.

  In the drawing, the monotone wobble Cos (ωt) = cos {2π · (fwob) · t} is shown. Therefore, when the modulated data is “1”, the STW modulated signal is cos {2π · (fwob). ) · T} + a · sin {2π · (2 · fwob) · t}, and when the modulated data is “0”, cos {2π · (fwob) · t} −a · sin {2π · (2 · fwo) · t}.

  As can be seen from FIG. 4, this STW signal waveform rises steeply toward the outer periphery of the disk and gently returns toward the inner periphery, and conversely, rises with a gentle slope toward the outer periphery of the disk and returns sharply. The values “1” and “0” are expressed by. In either case, the waveform has a common zero cross point with the monotone wobble MW indicated by a broken line. Therefore, in extracting the clock from the fundamental wave component common to the MSK monotone wobble MW portion, the phase is not affected.

Then, when positive and negative even harmonic signals are added to the reference carrier signal in this way, from the characteristics of the generated waveform, synchronous detection is performed using this harmonic signal, and the code data of the modulated data is It is possible to demodulate the modulated data by integrating the synchronous detection output.

  The Blu-ray Disc (registered trademark) recording / reproducing apparatus reads an address recorded by two methods of MSK modulation and STW modulation indicating the position on the wobble on the recording surface of the disc, and picks up the disc or disc at the target location. Is moving. A wobble signal including MSK modulation and STW modulation is binarized by a demodulator and further converted into a meaningful bit string by an address decoder. The converted bit string is subjected to ECC correction processing and determined as an address by the CPU. Thereafter, in order to move to the target address, the CPU sends an instruction to the servo control circuit, and the optical block moves the optical pickup to the designated position. After the optical pickup reaches the target address, data can be read from the optical disk, or data can be recorded on the optical disk by modulating the laser emitted from the pickup unit.

  The wobble structure of the optical disc on which the MSK modulation signal and the STW modulation signal are superimposed and the signal waveforms of the MSK modulation wave and the STW modulation wave have been described above. Next, an example of the configuration of an MSK demodulating circuit for demodulating an MSK modulated signal provided in a conventional optical disc apparatus will be described.

<Example of Configuration of Conventional MSK Demodulator Circuit>
FIG. 5 is an explanatory diagram illustrating an example of the configuration of a conventional MSK demodulation circuit. As shown in FIG. 5, the conventional MSK demodulation circuit 10 includes an A / D converter 11, a PLL circuit 12, a delay unit 13, a carrier wave generation circuit 14, a multiplier 15, an adder 16, And a positive / negative determination circuit 17.

  The A / D converter 11 converts the analog wobble signal input to the MSK demodulation circuit 10 into a digital signal and outputs the digital signal. The PLL circuit 12 includes an oscillator that oscillates at the same phase and the same frequency as the wobble signal input to the MSK demodulation circuit 10. The master clock that oscillates at such a phase and frequency is sent from the PLL circuit 12 to the A / D converter 11, the carrier wave generation circuit 14, and the adder 16 as a wobble cycle. The delay unit 13 delays the master clock (wobble clock signal) generated by the PLL circuit 12 so that the phase of the demodulation fundamental wave matches the input wobble.

  The carrier wave generation circuit 14 generates a signal waveform of a sine wave according to a master clock sent from the PLL circuit 12 using the signal from the delay unit 13 as a start pulse. The multiplier 15 multiplies the output of the A / D converter 11 and the Sin wave generated by the carrier wave generation circuit 14 and outputs the result. The adder 16 integrates the data obtained by the multiplier 15 in the section of the delayed wobble clock.

  The positive / negative determination circuit 17 determines whether the data output from the adder 16 is positive or negative. When the phase adjustment delay in the delay unit 13 is appropriately selected, the data output from the adder 16 becomes a negative value in the portion including the MSK wave. For this reason, the positive / negative determination circuit 17 outputs the MSB (Most Significant Bit) of the adder 16.

  The example of the configuration of the conventional MSK demodulation circuit has been described above. Such an MSK demodulator circuit has a problem that it cannot be demodulated sufficiently if the MSK demodulated signal is reduced due to phase fluctuation due to crosstalk from adjacent tracks. As a result, the address error rate has increased, and there has been a problem that stable recording / reproduction cannot be performed on recording / reproducing media having large variations. Next, the configuration of the ADIP demodulation circuit 130 of the optical disc apparatus 100 according to the first embodiment of the present invention that solves such a problem will be described.

<Configuration of ADIP demodulation circuit>
FIG. 6 is an explanatory diagram illustrating the configuration of the ADIP demodulation circuit 130 according to the first embodiment of the present invention. The configuration of the ADIP demodulation circuit 130 according to the first embodiment of the present invention will be described below using FIG.

  As shown in FIG. 6, the ADIP demodulating circuit 130 according to the first embodiment of the present invention includes an A / D converter 141, a delay unit 143, a carrier wave generating circuit 144, a multiplier 145, and an adder. 146, a positive / negative determination circuit 147, and a slice level adjustment unit 148.

  The A / D converter 141 operates according to the clock transmitted from the PLL circuit 142, converts the analog wobble signal input to the ADIP demodulation circuit 130 into a digital signal, and outputs the digital signal. The digital wobble signal converted by the A / D converter 141 is sent to the PLL circuit 142 and the multiplier 145.

  The PLL circuit 142 is a PLL circuit included in the PLL circuit 126 shown in FIG. 1 and oscillates at the same phase and the same frequency as the wobble signal input to the ADIP demodulating circuit 130. Although not shown, the PLL circuit 142 may include an oscillator for oscillating at the same phase and the same frequency as the wobble signal input to the ADIP demodulating circuit 130. The master clock output from the PLL circuit 142 is sent to the A / D converter 141, the carrier wave generation circuit 144, and the adder 146 as a wobble cycle.

  The delay unit 143 is for delaying the master clock (wobble clock signal) generated by the PLL circuit 142 so that the phase of the fundamental wave for demodulation coincides with the wobble signal input to the ADIP demodulation circuit 130. is there. Note that the delay unit 143 may include a flip-flop and a selector, and may use a digital counter. The delay unit 143 may be an analog circuit using a capacitor and a resistor, or may be a delay circuit using a buffer and a selector.

  The carrier wave generation circuit 144 generates a signal waveform of a sine wave according to a master clock (wobble clock signal) sent from the PLL circuit 142 using the signal from the delay unit 143 as a start pulse. As the carrier wave generation circuit 144, a ROM table circuit may be used as long as it generates a sine wave signal, it may be set by a CPU using a RAM, or an analog circuit using an oscillator. May be. Further, the signal generated by the carrier wave generation circuit 144 may be a signal other than the Sin wave as long as it generates a reference signal for demodulation. For example, it may be a Cos wave or a rectangular wave. Good.

  The multiplier 145 multiplies the output of the A / D converter 141 and the Sin wave generated by the carrier wave generation circuit 144 and outputs the result. The multiplication result in multiplier 145 is sent to adder 146. The adder 146 integrates the data obtained by the multiplier 145 during the wobble clock period delayed by the delay unit 143. As the adder 146, a digital circuit or an analog circuit may be used as long as it is an integrating circuit.

  The slice level adjustment unit 148 adds an offset to the output of the adder 146 and outputs the result. The slice level adjustment unit 148 includes an MPU (Micro Processing Unit) 151, an AND circuit 152, and an adder 153.

  In the adder 153, the MPU 151 sets a value (slice level) to be added to the value output from the adder 146. The value added to the adder 146 can be either positive or negative.

  The AND circuit 152 is a circuit to which the output from the MPU 151 and the Bit Sync LOCK signal sent from the address decoder 132 are input, and adds the output from the MPU 151 when the Bit Sync LOCK signal is in the HIGH state. To the container 153. The address decoder 132 detects the Sync Unit and Data Unit according to the format from the bit string (MSK Mark Bit) sent from the positive / negative determination circuit 147. Once the address decoder 132 finds the Sync Mark, it has a function of predicting the position of the next Mark and ignoring it even if a Mark is received at a position other than the Mark position. A signal indicating that the neglected function has been activated is referred to as a Bit Sync LOCK signal.

  In the present embodiment, the output from the MPU 151 is supplied to the adder 153 when the Bit Sync LOCK signal is in the HIGH state. However, it goes without saying that the present invention is not limited to this example. It is also possible to configure so that the output from is supplied to the adder 153.

  The positive / negative determination circuit 147 determines whether the data output from the adder 146 and offset by the slice level adjustment unit 148 is added. When the phase adjustment delay in the delay unit 143 is appropriately selected, the data output from the adder 146 becomes a negative value in the portion including the MSK wave. Therefore, the positive / negative determination circuit 147 outputs the MSB (Most Significant Bit) of the adder 16. Note that the positive / negative determination circuit 147 may determine positive / negative by using a positive value in a portion including the MSK wave by a combination of the phase delay value and the polarity of the input wobble.

  The configuration of the ADIP demodulation circuit 130 according to the first embodiment of the present invention has been described above. Next, the operation of the ADIP demodulation circuit 130 according to the first embodiment of the present invention will be described.

<Operation of ADIP Demodulation Circuit 130>
Due to the relationship between the track pitch and the wobble period, the wobble signal may change due to the influence of beats from adjacent tracks. 7 and 8 are explanatory diagrams showing a wobble signal when a beat is added from an adjacent track. The graphs shown in FIGS. 7A to 7C show that the wobble signal has changed as if the amplitude was modulated by the beat from the adjacent track, and FIGS. The graph shown in (2) shows that the wobble signal changed as if the phase was modulated by the beat from the adjacent track.

  For example, in the case of the DVD + RW format, the beat affects the amplitude. In the case of the Blu-ray (registered trademark) format, the beat has a relationship affecting the phase. In other words, in the case of the Blu-ray (registered trademark) format, the PLL (wobble PLL) that generates a clock synchronized with the wobble signal is synchronized with the waveform that follows the beat. The phase of the carrier wave of the multiplication circuit that performs the detection is different, or the amplitude of the Mark portion is reduced.

The beat frequency based on the wobble signal from the adjacent track is calculated as follows.
Fbeat: Beat frequency
Fwbl: wobble frequency
Tp: Track pitch
r: When the radius is set,
Fbeat ≒ Tp / r × Fwbl

The beat cycle around a radius of 25 mm in various disks at that time is as follows.
CD 1.6 / 25 × 22.05 = 1.4 [Hz]
DVD- 0.74 / 25 x 140.6 = 4.1 [Hz]
DVD + 0.74 / 25 x 818 = 24.2 [Hz]
BD 0.32 / 25 × 957 = 12.2 [Hz]

  FIG. 9 is an explanatory diagram showing an example of a demodulated waveform in the ADIP demodulating circuit 130 when the wobble signal input to the ADIP demodulating circuit 130 is not affected by the beat from the adjacent track. If there is no influence of the beat from the adjacent track, as shown in FIG. 9, the integration of the adder 146 in the inversion section (the section shown by (1) in FIG. 9) of the wobble signal input to the ADIP demodulation circuit 130. The result shows a negative value, and it can be recognized that the inversion section is the Mark section.

  However, when the wobble signal input to the ADIP demodulator circuit 130 is affected by the beat from the adjacent track, it may not be possible to recognize that the inversion section is the Mark section unless any countermeasure is taken. . FIG. 10 is an explanatory diagram showing an example of a demodulated waveform in the ADIP demodulator circuit 130 when the wobble signal input to the ADIP demodulator circuit 130 is affected by the beat from the adjacent track. FIG. 10 shows a demodulated waveform in the ADIP demodulating circuit 130 when the amplitude of the wobble signal input to the ADIP demodulating circuit 130 is decreased and the phase is shifted due to the influence of the beat from the adjacent track. .

  As shown in FIG. 10, in the inversion section of the wobble signal input to the ADIP demodulation circuit 130 (section shown by (1) in FIG. 10), if there is an influence of a beat from an adjacent track, the demodulation of the Mark section is performed. In some cases, the value decreases and the reversal section cannot be recognized as the Mark section.

  Therefore, the present embodiment is characterized in that the ADIP demodulation circuit 130 is provided with a slice level adjustment unit 148 as a mechanism for changing the slice level in order to easily detect the Mark unit.

  In the ADIP demodulation circuit 130 according to the first embodiment of the present invention, the slice level is set by the MPU 151 as described above. The set slice level is added (or subtracted) to the output of the adder 146 in the adder 153 via the AND circuit 152. In this way, by performing addition (or subtraction) processing on the output of the adder 146 in the slice level adjustment unit 148, detection of the Mark unit is facilitated in the ADIP demodulation circuit 130.

  The operation of the ADIP demodulation circuit 130 according to the first embodiment of the present invention has been described above. If the detection of the Mark part is facilitated, a place other than the Mark part may be erroneously detected as the Mark part due to the influence of noise. Therefore, in order to avoid erroneous detection, the slice level adjustment unit 148 may change the slice level only while the Bit Sync LOCK signal from the address decoder 132 is valid. When the Bit Sync LOCK signal is valid, the address decoder 132 detects the Mark signal only at the position where the Mark portion should be, thereby reducing the loss of the Mark.

[2] Second Embodiment of the Present Invention Next, the configuration of an ADIP demodulator circuit according to a second embodiment of the present invention will be described. In the first embodiment of the present invention, the slice level is set by the MPU 151. However, in the second embodiment of the present invention, ADIP demodulation in which the slice level is set using the center between the maximum and minimum demodulation amplitudes. The circuit will be described.

  FIG. 11 is an explanatory diagram illustrating the configuration of the ADIP demodulation circuit 230 according to the second embodiment of the present invention. The ADIP demodulator circuit 230 according to the second embodiment of the present invention shown in FIG. 11 is replaced with the ADIP demodulator circuit 130 according to the first embodiment of the present invention, and the ADIP demodulator circuit 130 according to the present invention shown in FIG. The configuration of the slice level adjustment unit 248 is different from that of the ADIP demodulation circuit 130 according to the first embodiment. The slice level adjustment unit 248 in the ADIP demodulation circuit 230 illustrated in FIG. 11 includes an MPU 251, an update interval adjustment unit 252, a peak detection unit 253, a bottom detection unit 254, an adder 255, an averaging unit 256, An AND circuit 257 and a subtracter 258 are included.

  The MPU 251 sends information on the data update intervals in the peak detection unit 253 and the bottom detection unit 254 to the update interval adjustment unit 252. When the update interval adjustment unit 252 receives the update interval information from the MPU 251, the peak detection and the bottom of the integration result in the adder 246 are detected at the update interval received from the MPU 251 based on the clock from the PLL circuit. The unit 253 and the bottom detection unit 254 detect.

  The peak detector 253 detects the peak of the integration result in the adder 246 at a predetermined update interval. The bottom detection unit 254 detects the bottom of the integration result in the adder 246 at a predetermined update interval. The detection results in the peak detection unit 253 and the bottom detection unit 254 are sent to the adder 255 and added, and the addition result is averaged by the averaging unit 256. The result obtained by averaging by the averaging unit 256 is subtracted from the integration result of the adder 246 in the subtractor 258, so that the slice level can be adjusted.

  The update interval in this embodiment may be, for example, about 1/20 second (20 Hz). In this embodiment, the slice level is adjusted by hardware. However, the slice level may be adjusted not only by hardware processing but also by software processing. For example, the peak value and the bottom value may be detected by the peak detection unit 253 and the bottom detection unit 254, the detected values may be passed to the MPU 251, and calculated by the MPU 251, and then the slice level may be controlled.

[3] Third Embodiment of the Present Invention Next, the configuration of an ADIP demodulator circuit according to a third embodiment of the present invention will be described. In the second embodiment of the present invention, the ADIP demodulation circuit that sets the slice level using the center between the maximum and minimum of the demodulation amplitude has been described. However, in the third embodiment of the present invention, the maximum of the demodulation amplitude is described. An ADIP demodulating circuit that adjusts the slice level in the direction in which the center is shifted from the minimum will be described.

  FIG. 12 is an explanatory diagram illustrating the configuration of the ADIP demodulation circuit 330 according to the third embodiment of the present invention. The ADIP demodulator circuit 330 according to the third embodiment of the present invention shown in FIG. 12 is the ADIP demodulator circuit 130 according to the first embodiment of the present invention or the ADIP demodulator circuit 230 according to the second embodiment of the present invention. Compared with the ADIP demodulating circuit 230 according to the second embodiment of the present invention shown in FIG. 11, the configuration after the adder 255 is different. The slice level adjustment unit 348 in the ADIP demodulation circuit 330 illustrated in FIG. 12 includes an MPU 351, an update interval adjustment unit 352, a peak detection unit 353, a bottom detection unit 354, an adder 355, an operational amplifier 356, and a slice level. The setting unit 357 includes a flip-flop circuit 358, an AND circuit 359, and a subtracter 360.

  In the ADIP demodulator circuit 330 according to the third embodiment of the present invention shown in FIG. 12, the peak detector 353 and the bottom detector 354 detect the peak value and the bottom value of the integration result of the adder 346. Then, the operational amplifier 356, the slice level setting unit 357, and the flip-flop circuit 358 are used to detect whether or not there is a difference between the peak value and the bottom value detected by the peak detection unit 353 and the bottom detection unit 354.

  If there is a difference between the peak value detected by the peak detection unit 353 and the bottom detection unit 354 and the bottom value, the slice level is set to +1 (or -1 in the direction shifted by the slice level setting unit 357). ) Change. By adjusting the slice level little by little by the slice level setting unit 357, the response speed can be made slow and smooth.

  The update interval in this embodiment may be, for example, about 1/20 second (20 Hz). In this embodiment, the slice level is adjusted by hardware. However, the slice level may be adjusted not only by hardware processing but also by software processing. For example, the peak detection unit 353 and the bottom detection unit 354 detect the peak value and the bottom value of the integration result of the adder 346, pass the detected values to the MPU 351, perform calculation processing by the MPU 351, and then change the slice level. You may control.

  As described above, according to the ADIP demodulating circuit 330 according to the third embodiment of the present invention, the peak value and the bottom value of the integration result of the adder 346 are detected by the peak detection unit 353 and the bottom detection unit 354. . Then, the operational amplifier 356, the slice level setting unit 357, and the flip-flop circuit 358 detect whether or not there is a difference between the detected peak value and the bottom value. When the difference occurs, the slice level setting unit 357 By changing the level, the Mark portion can be easily detected.

[4] Fourth Embodiment of the Present Invention Next, the configuration of an ADIP demodulator circuit according to a fourth embodiment of the present invention will be described. In the second embodiment of the present invention, the ADIP demodulation circuit that sets the slice level using the center of the maximum and minimum of the demodulation amplitude has been described, but in the fourth embodiment of the present invention, only the bottom of the demodulation amplitude is described. An ADIP demodulating circuit that detects a signal and sets a slice level will be described.

  FIG. 13 is an explanatory diagram illustrating the configuration of the ADIP demodulation circuit 430 according to the fourth embodiment of the present invention. The ADIP demodulation circuit 430 according to the fourth embodiment of the present invention shown in FIG. 13 includes an ADIP demodulation circuit 130 according to the first embodiment of the present invention and an ADIP demodulation circuit 230 according to the second embodiment of the present invention. Alternatively, the ADIP demodulator circuit 330 according to the third embodiment of the present invention is replaced, and compared with the ADIP demodulator circuit 230 according to the second embodiment of the present invention shown in FIG. The difference is that only the bottom value of the integration result is detected. The slice level adjustment unit 448 in the ADIP demodulation circuit 430 illustrated in FIG. 13 includes an MPU 451, an update interval adjustment unit 452, a bottom detection unit 453, an adder 454, an AND circuit 455, and a subtracter 456. Consists of.

  In the ADIP demodulation circuit 430 shown in FIG. 13, a fixed value is sent from the MPU 451 to the bottom value of the integration result of the adder 446 detected by the bottom detection unit 453 in consideration of the MSK error rate. Both are added and output. The ADIP demodulating circuit 430 according to the fourth embodiment of the present invention can set the slice level by detecting only the bottom of the demodulated amplitude and adding a fixed value considering the MSK error rate.

  As described above, according to the ADIP demodulating circuit 430 according to the fourth embodiment of the present invention, the bottom value of the integration result of the adder 446 detected by the bottom detection unit 453 is taken into account for the MPU 451 in consideration of the MSK error rate. The fixed value is sent out from the signal, and the adder 454 adds both of them and outputs them, so that the Mark portion can be easily detected.

  As described above, according to each of the above embodiments, a mechanism for adjusting the slice level is provided in the ADIP demodulator circuit, and the slice level is adjusted using the output value of the adder, thereby detecting the Mark portion. Easy to do. As a result, even if the MSK demodulated signal is reduced due to phase fluctuations due to crosstalk from adjacent tracks, it can be demodulated sufficiently and the address error rate can be reduced.

  According to the second to fourth embodiments, the slice level is adjusted using at least the minimum value among the output values of the adder. At least, by using the minimum value of the output value of the adder, the detection of the Mark part can be facilitated, and the address error rate can be reduced.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention is applicable to a demodulation device, a demodulation method, an information reproducing device, and a computer program.

It is explanatory drawing explaining the structure of the optical disk apparatus 100 concerning the 1st Embodiment of this invention. It is explanatory drawing explaining the wobble structure of the optical disk with which the MSK modulation signal and the STW modulation signal were superimposed. It is explanatory drawing explaining the waveform of a MSK modulation wave. It is explanatory drawing shown about the waveform of STW modulation wave. It is explanatory drawing explaining an example of a structure of the conventional MSK demodulation circuit. It is explanatory drawing explaining the structure of the ADIP demodulation circuit 130 concerning the 1st Embodiment of this invention. It is explanatory drawing which shows a wobble signal when a beat is added from an adjacent track. It is explanatory drawing which shows a wobble signal when a beat is added from an adjacent track. It is explanatory drawing which shows an example of the demodulation waveform in ADIP demodulation circuit 130. FIG. It is explanatory drawing which shows an example of the demodulation waveform in ADIP demodulation circuit 130. FIG. It is explanatory drawing explaining the structure of the ADIP demodulation circuit 230 concerning the 2nd Embodiment of this invention. It is explanatory drawing explaining the structure of the ADIP demodulation circuit 330 concerning the 3rd Embodiment of this invention. It is explanatory drawing explaining the structure of the ADIP demodulation circuit 430 concerning the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Optical disk apparatus 102 Spindle servo circuit 104 Spindle driver 106 Spindle motor 108 Optical block servo circuit 110 Thread driver 112 Thread mechanism 114 Two axis driver 116 Optical block 118 Laser power control part 120 Recording pulse conversion circuit 122 ECC encoder / decoder 124 Matrix circuit 126 PLL circuit 128 Data demodulating circuit 130 ADIP demodulating circuit 132 Address decoder 134 CPU
141 A / D converter 142 PLL circuit 143 Delay unit 144 Carrier wave generation circuit 145 Multiplier 146 Adder 147 Positive / negative determination circuit 148 Slice level adjustment unit 151 MPU
152 AND circuit 153 Adder 230, 330, 430 ADIP demodulation circuit

Claims (7)

A carrier generation circuit for generating and outputting a carrier for a predetermined modulation signal included in the input signal;
A multiplier that multiplies an input signal by the carrier wave and outputs;
An adder for adding and outputting the output of the multiplier for a predetermined period;
A slice level adjusting unit that outputs by adding or subtracting a predetermined offset value to the output of the adder; and
A positive / negative determination circuit that determines the positive / negative of the output of the slice level adjustment unit and outputs a determination result;
Including
The demodulating apparatus, wherein the slice level adjusting unit determines the predetermined offset value using at least a minimum value of the output of the adder.   2. The demodulator according to claim 1, wherein the slice level adjustment unit uses an average value of a maximum value and a minimum value of the output of the adder as the predetermined offset value.   The slice level adjustment unit sets the predetermined offset value in a direction away from an average value of the maximum value and the minimum value of the adder when the average value is away from a center value of a demodulated wave. 2. The demodulator according to 2.   2. The demodulator according to claim 1, wherein the slice level adjustment unit sets a value obtained by adding a predetermined amount in consideration of a demodulation error rate to a minimum value of the output of the adder as the predetermined offset value. A carrier wave generating step of generating and outputting a carrier wave for a predetermined modulation signal included in an input signal obtained by reading information from a recording medium;
A multiplication step of multiplying the input signal by the carrier and outputting;
An addition step of adding and outputting the output of the multiplication step for a predetermined period;
A slice level adjustment step of adding or subtracting a predetermined offset value to the output of the addition step, and outputting,
A positive / negative determination step of determining the positive / negative of the output of the slice level adjustment step and outputting a determination result;
Including
The slice level adjustment step determines the predetermined offset value using at least the minimum value of the output of the addition step. A carrier generation circuit for generating and outputting a carrier for a predetermined modulation signal included in the input signal;
A multiplier that multiplies an input signal by the carrier wave and outputs;
An adder for adding and outputting the output of the multiplier for a predetermined period;
A slice level adjusting unit that outputs by adding or subtracting a predetermined offset value to the output of the adder; and
A positive / negative determination circuit that determines the positive / negative of the output of the slice level adjustment unit and outputs a determination result;
Including
The slice level adjustment unit determines the predetermined offset value using at least the minimum value of the output of the adder. A carrier generation step for generating and outputting a carrier for a predetermined modulation signal included in the input signal;
A multiplication step of multiplying the input signal by the carrier and outputting;
An addition step of adding and outputting the output of the multiplication step for a predetermined period;
A slice level adjustment step of adding or subtracting a predetermined offset value to the output of the addition step, and outputting,
A positive / negative determination step of determining the positive / negative of the output of the slice level adjustment step and outputting a determination result;
To the computer,
The slice level adjustment step determines the predetermined offset value by using at least the minimum value of the output of the addition step.

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