JP4305286B2 - Computer system - Google Patents

Description

  The present invention relates to a memory system in a computer system such as a personal computer, a workstation, an office computer, and more particularly to a large capacity memory system.

  In response to the recent rapid increase in performance of processors, the memory subsystem is required to have a larger data width and higher speed operation in order to satisfy the high bandwidth required by the processor. In addition, there is also a demand to increase the memory capacity as much as possible.

  FIG. 2 shows an example of a computer system configuration. In the following, numbers in the figure that have a lowercase suffix such as 201a and 201b indicate one element of multiple elements, and all elements are described without a suffix And Also, in the case of the data buses A, B, and C with the element names, a number written immediately after, such as the data buses C0 and C1, indicates one element among a plurality of items, and is written without including a number Indicates all elements.

  This computer system includes a memory controller (202) connected to the processor (201) via the data bus A (205), and a plurality of data buses C (207) connecting the memory controller and the memory array (204). Composed. In the figure, the bus width of the processor and the memory array is the same M (bytes), but the data rate is L (bps) for the processor, whereas the memory array can only operate at half that L / 2 (bps). Therefore, by preparing two data buses C0 and C1, the data bus A and the data bus C have the same bandwidth.

  FIG. 3 shows a configuration when a memory array that can operate at a data rate of L (bps) appears. The difference from FIG. 2 is that the data rate of the data bus C has doubled L (bps), and the number of memory arrays connectable to the data bus C has decreased. Since the data width and the data rate of the data bus A and the data bus C are equal, the bandwidth of this computer system is equal only with one data bus C. However, the number of loads is limited due to the electrical characteristics of the interface of the data bus C that has become high-speed, and the number of memory arrays that can be connected to the data bus C is reduced. Compared to the configuration of If the memory controllers of FIGS. 2 and 3 are the same LSI package, there is room to add another data bus C, and two data buses C are prepared to increase the memory capacity. At this time, the memory array side has twice the bandwidth of the processor side, but since the bandwidth on the processor side has not changed, the data bus A becomes a bottleneck, affecting the maximum throughput of the entire system. Absent. However, the effective throughput and average access time may be improved depending on the access pattern to the memory.

  FIG. 4 shows a configuration in which the required bandwidth on the processor side is double that of FIG. The difference from FIG. 3 is that the data bus A1 is connected to the memory controller. In this state, the data bus A and the data bus C have the same data width, data rate, and number of buses, so the bandwidth is balanced between the processor side and the memory side. However, since the number of memory arrays that can be connected is limited by the number of data buses C, it is difficult to increase the memory capacity with respect to the throughput of the processor, which is not suitable for applications that require a large capacity memory. With respect to this configuration diagram, the techniques that have been performed to further secure the memory capacity can be classified into the following three types.

  The first is to increase the number of data buses that can be connected to the memory array side by using an LSI package having a large number of pins for the memory controller. However, the problem is that multi-pin type LSI packages are more expensive than mainstream LSI packages, and the number of multi-pin type LSI packages is limited. As of 1998, the number of signal pins is around 400, and if the ratio of the number of signal pins to the number of power supply pins is about 2: 1, the 600 pin class is used for the package. There are 1000 pin class packages, but they are still expensive.

  The second is to increase the number of memory arrays connected to the data bus C. For this purpose, the SSTL interface disclosed in Japanese Patent Laid-Open No. 7-202947 (Applicant: Hitachi) is used for the interface of the data bus C, and the data transfer method is Japanese Patent Laid-Open No. 10-293635 ( (Applicant: Hitachi, Ltd.) using the source synchronous transfer method. The configuration is shown in FIG. The difference from FIG. 4 is that the connection form of the memory sub-controller and the memory array is ring-shaped and connected via a 1: 2 multiplexer (208) (hereinafter referred to as MUX). As shown in Japanese Patent Application No. 8-145431, the effect of MUX is to change the transfer direction by memory access write and read operations, and halve the number of pins required for the memory sub-controller. It is to reduce. The SSTL interface is an interface that suppresses reflection to the bus line by inserting a series resistor in the stub of the load connected to the bus. The source synchronous transfer method transmits the source clock signal along with the data signal from the data transfer source. The data transfer method latches the received data signal using the source clock signal on the receiving side. Unlike the conventional synchronous transfer method that transfers data using the system clock signal, the source synchronous transfer method runs in parallel because the data signal to be transferred and the source clock signal run in parallel, and the setup hold time Since the propagation delay time due to the bus wiring length can be almost ignored at the time of timing design, etc., high-speed data transfer is facilitated. Combining the above two enables high-speed data transfer on a multi-load connection bus, and the memory capacity can be increased while operating at high speed. Even in this case, the memory capacity is determined by the number of data buses C that can be connected to the memory controller. Therefore, if the memory capacity is further increased, the number of pins of the LSI package of the memory controller must be increased.

  The third is to make it appear that the number of data buses C has increased. The configuration is shown in FIG. The difference from FIG. 4 is that a 1: N MUX (209) is connected between the memory controller and the memory array to increase the number of apparent buses. Therefore, the memory capacity is N times before using MUX. However, although the number of buses connected to the memory array and the memory capacity have increased, the number of buses connected to the memory controller has not changed, so the bandwidth of the data bus C does not change. . In addition, since a 1: N MUX is inserted in the middle, there is a problem that the time required for switching the MUX becomes an overhead and the effective throughput is lowered. In addition, since the memory array is spatially widened, high-speed data transfer between the memory controller and the memory array becomes difficult, and it is necessary to install a data buffer between the memory controller and the MUX or between the MUX and the memory array.

On the other hand, by using the source synchronous transfer method for data transfer, high-speed data transfer can be realized and the bandwidth can be improved. In the source synchronous transfer method, as long as the propagation delay time of the data signal between the data transfer devices and the source clock signal is equal, the transmission delay time in the transmission path between the data transfer devices, that is, the high speed is not affected by the distance between the data transfer devices. Data transfer is possible. Data transfer is not limited to 1-cycle transfer, and multi-cycle transfer is possible. However, when performing N cycle transfer, the data propagation delay time Td is
It is necessary to ensure that (N-1) × (1 machine cycle time) <Td <N × (1 machine cycle time), and the interface circuit matched to the data propagation delay time between data transfer devices It is created in the transfer device to realize N cycle transfer. The interface circuit in the data transfer apparatus is the only one created in accordance with the external transmission path, and in many cases, the change of the external transmission path cannot be compliantly followed.

JP-A-7-202947 JP-A-10-293635

The conventional computer system configuration has the following problems as described above.
(1) Increasing the number of pins of the memory controller to increase the number of data buses C increases the cost of the memory controller.
(2) Although it is possible to increase the memory capacity by apparently increasing the number of data buses C, the bandwidth is not improved.
(3) In (2), when the apparent data bus C is connected by MUX, the switching time of MUX becomes overhead and the effective throughput is lowered.
(4) In the source synchronous transfer method, the number of transfer cycles is determined according to the propagation delay time of data, and an interface circuit corresponding to the number of cycles needs to be created in the data transfer apparatus.

The purpose of the present invention is to
(1) Memory subsystem with improved bandwidth by adopting source synchronous transfer method capable of high-speed data transfer to multiple data transfer devices
(2) Memory subsystem with increased memory capacity and improved bandwidth without increasing costs
(3) Data that uses a source synchronous transfer method for data transfer, has a buffer that guarantees the minimum transfer cycle of data transfer, and realizes multi-cycle data transfer regardless of the minimum propagation delay time by the data transmission path It is to provide a transfer device.

  In order to achieve the above object, one or more memory sub-controllers are provided between the memory controller and the memory array, and the memory controller and the memory sub-controller are connected by a first data bus. The controller and the memory array are connected by one or more second data buses, and high-speed data transfer is performed by the source synchronous transfer method using the first data bus and the second data bus. Build a memory subsystem with improved bandwidth.

  The first data bus and the second data bus perform data transfer by the source synchronous transfer method, and further, the data interface conversion unit and the data width conversion unit are provided in the bus interface unit of the memory sub-controller and the memory controller. Either one or both were provided.

  The data rate of the first data bus connected to one memory sub-controller is increased so that the bandwidth of the first data bus is equal to the bandwidth of the second data bus connected to the memory sub-controller. By changing to be equal to the sum, a high-throughput and large-capacity memory subsystem is constructed without increasing costs.

  Further, the data width of the first data bus connected to the memory controller is reduced, the data rate is increased, and the bandwidth of the first data bus is connected to that of the third data bus connected to the memory controller. By changing to be equal to the bandwidth, the cost for the LSI package of the memory controller is reduced, and a large-capacity memory subsystem having the required bandwidth of the processor is constructed.

  Further, by providing N stages of buffers in the data transfer I / F section of the memory controller and the memory sub-controller that perform source synchronous transfer, the minimum transfer cycle of data transfer is guaranteed, and the first data bus and the second data A memory subsystem that implements N-cycle data transfer on the bus is constructed.

  The present invention provides a computer system comprising a memory controller and a memory array connected to a plurality of processors via a data bus A, and one or more memory sub-controllers are provided between the memory controller and the memory array. One memory sub-controller and a memory controller are connected by a data bus B, and the memory sub-controller and the memory array are connected by one or more data buses C. The data bus B and the data bus C are sources. The data bus interface unit of the memory sub-controller and the memory controller is provided with one or both of a data rate conversion circuit and a data width conversion circuit so that the data width of the data bus B is not increased. Increase the rate, By determining the data width and data rate of the data bus B so that the bandwidth of the bus B becomes equal to the sum of the bandwidths of the data bus C, the capacity of the memory is increased and the cost is increased without decreasing the maximum throughput. It is possible to improve the bandwidth without incurring the problem.

  An embodiment of the present invention will be described with reference to FIGS. 1 and 7 to 12. In FIG. 1, a memory sub-controller (103), a memory sub-memory that exists between a memory controller (102) and a memory array (104) connected to a plurality of processors (101) via a data bus A (105). A data bus B (106) connecting the controller and the memory controller and a plurality of data buses C (107) connecting the memory sub-controller and the memory array are included. The memory controller has two data buses on the memory array side, and is connected to one memory sub-controller (103a-b) via a data bus B (106a-b), respectively. Are connected to the memory array via the data bus C. Here, the configuration from the memory sub-controller 103a to the memory array 104a and the memory array 104b is exactly the same as the configuration from the memory sub-controller 103b to the memory array 104c and the memory array 104d. Therefore, in this embodiment, one memory sub-controller will be described, but the same can be said for the other memory sub-controller.

  Since the data buses C0 and C1 have the same data rate L (bps) and the same data width M (bytes), the bandwidth of each bus of the data buses C0 and C1 is (L × M). The data rate of the data bus B0 is 2L (bps), which is twice that of the data bus C. However, since the data width is M (bytes) equal to the data buses C0 and C1, the bandwidth of the data bus B0 is (2 × L × M). A method of doubling the bandwidth of the data bus B by doubling the data rate without changing the data width of the data bus B will be described.

  FIG. 7 is a block diagram of the memory sub-controller (103) of FIG. Reference numerals 301 to 315 denote elements and signal lines constituting the memory sub-controller. 401 to 406 are interface signals with the memory controller, and control signals for the memory array are transmitted using these signal lines. Reference numerals 501 to 505 denote interface signals with the memory controller, and data signals are transmitted and received using these signal lines. 601 to 605 are data bus C0 interface signals, and 701 to 705 are data bus C1 interface signals. 601 to 605 and 701 to 705 have the same signal line types, meanings, and timings, except that the connection destination buses are different.

  The memory sub-controller in the figure is composed of an edge trigger type flip-flop (301), an input buffer (302), an output buffer (303), a 2: 1 selector (304), and a select signal (305) to the 2: 1 selector. Is done. The trigger clock signal of the edge trigger type flip-flop is a system clock signal (T0) or a source clock signal for source synchronous transfer received from the bus. T14, T24, and T34 in the figure are signals delayed by 1/4 phase, 2/4 phase, and 3/4 phase, respectively, from the system clock signal (T0), and are used as source clock signals for source synchronous transfer.

  The interface with the memory controller includes an address signal (401) transmitted from the memory controller to the memory sub-controller, a control command signal (404), a source clock signal for the address signal (402 and 403), a source clock signal for the control command signal ( 405 and 406), a bidirectional data signal (503), a source clock signal for reception data (501 and 502), and a source clock signal for transmission data (504 and 505). The reason why there are two source clocks will be described later.

  The interface with the memory array includes an address signal (602), a control command signal (603), a bidirectional data signal (604), an address signal, a control command signal, and a transmission data signal transmitted to the memory array via the data bus C0. Source clock signal (601) and received data source clock signal (605).

  The configuration of the elements 701 to 705 in FIG. 7 is the same as that of the elements 601 to 605 as described above.

  In this embodiment, the access procedure to the memory array is the same as the access procedure to SDRAM (Synchronous DRAM).

(1) Write operation: A row address signal is transmitted to the address signal line, and a row address strobe (RAS) signal is transmitted to the control command signal line.
After three cycles, this time, a column address signal is transmitted to the address signal line, a column address strobe (CAS) signal is transmitted to the control command signal line, and a data signal to be written to the data signal line is transmitted.

(2) Read operation: A row address signal is transmitted to the address signal line, and a row address strobe signal is transmitted to the control command signal line.
After 3 cycles, this time, send a column address signal to the address signal line and a column address strobe signal to the control command signal line.
• Data is output to the bus after 3 cycles.
The memory array can perform burst transfer, and four write or read operations with respect to consecutive addresses can be performed by one write or read operation. Further, the address procedure (401: B-ADR) on the memory controller side and the address signals (602: C0-ADR and 702: C1-ADR) on the memory array side have the same access procedure except for the timing. The same applies not only to the address signal but also to other control command signals and data signals.

  In this embodiment, in order to double the data rate without changing the data width of the data bus, the data bus B is time-divided at the rise and fall of the system clock, and the system clock is "H". In other words, the data transfer related to the data bus C0 is performed in the first half of the clock cycle, and the data transfer related to the data bus C1 is performed in the second half of the clock cycle. Therefore, two source clocks for source synchronous transfer are required, one that latches the signal in the first half of the clock cycle and the other that latches the signal in the second half of the clock cycle. Of the source clock signals (402 and 403) relating to the address signal, 402 is a source clock signal for data processing on the data bus C0, and 403 is for data processing on the data bus C1. Similarly, 405, 501 and 504 are source clock signals for data processing on the data bus C0, and 406, 502 and 505 are source clock signals for data processing on the data bus C1.

  FIG. 8 shows an operation timing chart of data transfer from the memory controller to the memory array in the block diagram of FIG. Data transfer from the memory controller to the memory array is a write operation to the memory array. Since the address signal and the control command signal are transmitted at the same timing, the two are written together here. FIG. 8 is a timing chart in which write operations are performed on the data buses C0 and C1 at the same timing.

  The memory controller sends a row address signal (401: B-ADR) and a row address strobe signal (for the data bus C0 in the first half of the clock cycle and for the data bus C1 in the second half of the clock cycle to the memory sub-controller at the timing of CK0. 404: B-CMD). Further, in synchronization with the address signal and the control command signal, the source clock signal (402 and 405) for the data bus C0 and the source clock signal (403 and 406) for the data bus C1 are transmitted. The signals used for the source clock signal are T14 and T34, respectively. The memory sub-controller latches the address signal (405) and the control command signal (404) using the rising edge of the received source clock signal (402 and 405: T14 timing signal in the memory controller). The address signal latched by the source clock signals (402 and 405) is 306 (C0-ADRbuff), and the control command signal is 308 (C0-CMDbuff). These are signals for the data bus C0. The memory controller switches the address signal and the control command signal to the signal for the data bus C1 when ½ clock cycle has passed from the start of the cycle of CK0. The address signal (401) and the control command signal (404) are latched using the rising edge of the source clock signal (403 and 406: T34 timing in the memory controller) delayed by 1/2 cycle from the above-mentioned source clock signal. The address signal latched by the source clock signals (403 and 406) is 307 (C1-ADRbuff), and the control command signal is 309 (C1-CMDbuff). These are signals for the data bus C1. In the memory sub-controller, the signals (306 to 309) latched with the source clock signal are latched with the system clock (T0), the phases of all signals to be transferred are matched, and then transmitted to the data buses C0 and C1. The source clock signals transmitted to the data buses C0 and C1 are 601 and 701, and the clock timing to be used is both T24. The memory controller transmits a data signal (0a or 1a) to be written simultaneously with the column address signal and the column address strobe signal for the row address signal at the timing of CK3 three cycles after the transmission of the row address signal. In synchronization with this data transmission, the memory controller transmits a source clock signal (501) for the data bus C0 and a source clock signal (502) for the data bus C1. The timing related to the column address signal and the column address strobe signal is the same as that of the row address signal and the row address strobe signal. The same applies to the data signal.The received data signal (503) is latched by the received source clock signal (501: T14 timing signal in the memory controller) and source clock signal (502: T34 timing signal in the memory controller). To do. The data signals latched by the source clock signals (501 and 502) are 310 (C0-Dbuff) and 311 (C1-Dbuff), respectively, which are a data signal for the data bus C0 and a data signal for the data bus C1, respectively. Similarly to the address signal and control command signal described above, the data signal is also latched by the system clock (T0), and the phase of all signals to be transferred is adjusted. The system clock signal (T0) is used for the transmission timing to the data bus C. This timing is set to T0 if all of the address signal, control command signal, data signal and source clock signal can be transmitted to the data bus C at the same timing. Anything can be used. The signal used for the source clock signal is not limited to T24 as long as it satisfies the setup / hold time of the memory array, and any signal may be used. Since burst transfer is possible, the memory controller transmits data signals (three of 0b, 0c, and 0d, and three of 1b, 1c, and 1d) at the timing of CK4, CK5, and CK6 following the timing of CK3.

  As described above, by preparing two source clock signals and two edge trigger type flip-flops for the data signal of the data bus B having a double data rate, the two edge trigger type flip-flops are prepared. Functions as a data rate conversion circuit, and when transmitting to the data bus C, the data rate is ½ times that of the data bus B and equal to the data rate of the data bus C.

FIG. 9 shows an operation timing chart of data transfer from the memory array side to the memory controller side in the block diagram of FIG. Data transfer from the memory array to the memory controller is a read operation for the memory array. In FIG. 9, the address signal and the control command signal are already transmitted, and the timing is shown when data is output from the memory array. Since the memory array is capable of burst transfer, it outputs data signals for four cycles (C0a, C0b, C0c, C0d, and C1a, C1b, C1c, C1d). FIG. 9 is a timing chart in which the data transfer on the data bus C1 is delayed by one cycle with respect to the data transfer from the data bus C0. In general, a synchronous memory device has an access time and an output hold time during a read operation. The access time is the time from the input of the trigger clock signal until the data signal is output. The output hold time is the time from the input of the trigger clock signal until the data signal that was output in the previous cycle is not output. It is. Therefore, the window width of the output data signal is
(Memory array output data window width) = (1 cycle) + (output hold time) − (access time). Since the memory array of this embodiment has an access time of 1/2 cycle and an output hold time of 1/2 cycle, the output data signal has a window width of 1 cycle.

  In the memory sub-controller, the source clock signal received from the memory array in the cycle of CK0 in the interface section of the data bus C0, or sent from the memory sub-controller to the memory array and received by the memory sub-controller itself through the memory array ( 605) is used to latch the data signal (604). The latched data signal is 313 (C0-Din). On the other hand, the data signal (704) from the memory array is received in the interface section of the data bus C1 in the cycle CK1, and is latched using the rising edge of the received source clock signal (705). The latched data signal is 315 (C1-Din). Since the data rate is doubled in the data bus B, a data rate conversion circuit is necessary, but it uses a 2: 1 selector (304), and a system clock is used as the select signal (305). . The data signals from the data bus C0 and the data bus C1 may be input to the two inputs of the 2: 1 selector, respectively, but the phase of the select signal and the two input data must be matched, and the select signal (ie It is necessary to latch the received data signals (313 and 314) from the data buses C0 and C1 using the rising edge of the system clock signal T0). The data signals latched by the system clock signal (T0) are 312 (C0-Drt) and 314 (C1-Drt), respectively. When the select signal is “H”, that is, in the first half of the clock cycle, the data signal from the data bus C0 is transmitted to the data bus B, and when the select signal is “L”, that is, in the second half of the clock cycle, the data bus C1. The data signal from is transmitted to the data bus B. Source clock signals (504 and 505) are transmitted in synchronization with the data signal transmitted to the data bus B.

  As described above, by inserting a 2: 1 selector in the middle of the data bus C to the data bus B and switching the two input data in phase with the select signal according to the select signal, the data rate in the data bus B is changed to the data rate. The bus C can be doubled.

  When one data bus B and two data buses C are connected to the memory sub-controller, the data width of the data bus B and the data width can be increased by doubling the data rate without changing the data width of the data bus B. The sum of the bandwidths of bus C is equal.

  FIG. 1 shows a method of doubling the data rate while keeping the data width of the data bus B and making the sum of the bandwidth of the data bus B and the bandwidth of the data bus C equal. Next, a method is shown in which the data width of the data bus B is halved, the data rate is quadrupled, and the sum of the bandwidth of the data bus B and the bandwidth of the data bus C is made equal.

  FIG. 10 is a block diagram of the memory sub-controller (103) of FIG. The difference from FIG. 7 is that the data rate of the data signal has increased from 2 to 4 on the data bus B side, so the source clock signal used for data transfer has been changed from 2 to 4 (506 to 509), This is because the 2: 1 selector is changed to the 4: 1 selector (316) in order to convert the data rate and the data width when the data signals are transferred from the data buses C0 and C1 to the data bus B.

As shown in FIG. 10, when the number of data buses C connected to the memory sub-controller is two, the address signal and control command signal from the memory controller can be transmitted simultaneously even if the data rate is quadrupled. Since there are only two buses C0 and C1, the data rate is doubled and transferred. There are four source clock signals T18, T38, T58, and T78 for source synchronous transfer related to data signals, which are 1/8 phase, 3/8 phase, 5/8 phase, and 7/8 phase delayed from the system clock T0, respectively. FIG. 11 shows an operation timing chart of data transfer from the memory controller to the memory array in the block diagram of FIG. As in FIG. 8, the memory controller performs the write operation at the same timing on the data buses C0 and C1 at the timing of CK0. Since the data signal on the data bus B has a data width which is half that of the data signal on the data bus C and is four times the data rate, data transfer is performed at a quarter clock cycle pitch. The memory controller sends to the memory sub-controller at the timing of CK0 the upper byte data signal of the data bus C0 in a quarter part of the clock cycle, the lower byte data signal of the data bus C0 in the quarter part of the clock cycle, The upper byte data signal of the data bus C1 is transmitted in the 3/4 portion, and the lower byte data signal of the data bus C1 is transmitted in the 4/4 portion of the clock cycle. Further, in synchronization with the data signal, the source clock signal (506 and 507) for data processing on the data bus C0 and the source clock signal (508 and 509) for data processing on the data bus C1 are transmitted. The address signal and control command signal transfer method is the same as in FIG.

  The memory sub-controller latches the data signal 503 using the rising edge of the received source clock signal (506, 507, 508, 509). The upper byte data signal of the data bus C0 latched by the source clock signal 506 is 318 (C0-DUbuff), the lower byte data signal of the data bus C0 latched by the source clock signal 507 is 319 (C0-DLbuff), The upper byte data signal of the data bus C1 latched by the source clock signal 508 is 320 (C1-DUbuff), and the lower byte data signal of the data bus C1 latched by the source clock signal 509 is 321 (C1-DLbuff). In the memory sub-controller, the data signals divided by the memory controller into upper / lower bytes for transferring on the data bus B are combined into one, latched by the system clock (T0), and the phases of all signals to be transferred are Then, the data is transmitted to the data buses C0 and C1. The operations of the data buses C0 and C1 are the same as those in FIG.

  As described above, four data source clock signals and four edge trigger type flip-flops are prepared for the data signal of the data bus B having a data width of 1/2 and a data rate of 4 times. The edge trigger type flip-flop on the surface functions as a data rate conversion circuit and a bus width conversion circuit. When data is transmitted to the data bus C, the data rate is 1/4 times that of the data bus B and the data width is doubled. It becomes equal to the data rate and data width of the bus C.

  FIG. 12 shows an operation timing chart of data transfer from the memory array side to the memory controller side in the block diagram of FIG. The operation timing on the memory array side is the same as the above method. A 4: 1 selector (316) is used to achieve a quadruple data rate. For the select signal (317) of the 4: 1 selector (316), the system clock T0 and T14 delayed by 1/4 phase from the system clock are used. At the four inputs of the 4: 1 selector, the data signals (313 and 315) of the data buses C0 and C1, which are latched by the system clock (T0) and are in phase with the select signal, are divided into upper and lower bytes. Enter. There are four states depending on the values of the two select signals (T0 and T14), and when TO is "H" and T14 is "L", that is, the upper byte of the data bus C0 in the ¼ portion of the clock cycle. Data is transmitted to the data bus B, and when T0 is "H" and T14 is "H", that is, the lower byte data of the data bus C0 is transmitted to the data bus B in the 2/4 portion of the clock cycle. When L "and T142 are" H ", that is, the upper byte data of the data bus C1 is transmitted to the data bus B in 3/4 part of the clock cycle, when T0 is" L "and T14 is" L ", The lower byte data of the data bus C1 is transmitted to the data bus B in the 4/4 portion of the clock cycle. Source clock signals (510 to 513) are transmitted in synchronization with the data signal transmitted to the data bus B.

  As described above, a 4: 1 selector is inserted in the middle of the data bus C to the data bus B, and the four input data whose phase is matched with the select signal and the data width is halved are switched by the select signal. In the bus B, the data rate can be four times that of the data bus C and the data width can be ½ that of the data bus C.

  In the above description, the upper / lower bytes are used as the dividing method when the data width of the data bus B is halved, but there are many other methods such as dividing even / odd bytes. Also, the transfer order of the divided units is arbitrary.

  When one data bus B and two data buses C are connected to the memory sub-controller, the data bus B bandwidth is reduced by halving the data width of the data bus B and quadrupling the data rate. The sum of the bandwidths of the data bus C is equal.

  Another embodiment of the present invention is shown in FIG. The difference from FIG. 1 is that the data width of the data bus B is halved and the data rate is quadrupled, and the bandwidth of the data bus B connected to one memory sub-controller is set in the memory sub-controller. In other words, the sum of the bandwidths of the connected data bus C is made equal. The components and the operation timing are described in the “method of doubling the data rate by halving the data width” of the present invention. Since the data width of the data bus B is halved, the number of pins required for the memory controller and the memory sub-controller is reduced, and an LSI package smaller than the LSI package of FIG. 1 can be used, thereby reducing costs.

  Another embodiment of the present invention is shown in FIG. The difference from FIG. 1 is that the data width of the data bus B is ½, the data rate is quadrupled, and the bandwidth of the data bus B connected to one memory sub-controller is set to the memory sub-controller. In other words, the sum of the bandwidths of the connected data bus C is made equal. The difference from FIG. 13 is that the number of data buses C connected to the memory controller is doubled without reducing the number of pins of the memory controller. The components and the operation timing are described in the “method of doubling the data rate by halving the data width” of the present invention. Since the data width of the data bus B is halved, the number of data buses B that can be connected to the memory controller is doubled, and the data bus B doubles the memory capacity while ensuring the total bandwidth of the data bus C. It becomes possible.

  Another embodiment of the present invention is shown in FIG. The difference from FIG. 1 is that the data width of the data bus B is halved and the data rate is doubled. In all of the above-described embodiments, the data bus B secures the bandwidth corresponding to the number of data buses C connected to the memory array in the memory sub-controller. However, it is also possible to halve the data width of the data bus B and double the data rate so as to achieve a system configuration that balances the bandwidth of the data bus A and the data bus B. In this case, the bandwidth of the data bus B is not changed, but the data width of the data bus B is halved, so that the number of pins necessary for the memory controller and the memory sub-controller can be reduced. That is, the cost for the LSI package of the memory controller and the memory sub-controller can be reduced. The block diagram and timing chart of the memory sub-controller are the same as the block diagrams of FIG. 7, FIG. 8 and FIG. 9 except that the width of the data bus is different.

  Another embodiment of the present invention will be described with reference to FIGS. FIG. 16 is a block diagram of the memory sub-controller. Reference numerals 302 to 303, 810 to 812, and 820 to 822 denote elements and signal lines constituting the memory sub-controller (103). Reference numerals 800 to 803 are interface signals with the memory controller, and control signals for the memory array are received and data signals are transmitted and received using these signal lines. 804 to 807 are interface signals of the data bus C, and control signals for the memory array are transmitted and data signals are transmitted and received using these signal lines.

  The memory sub-controller in FIG. 16 includes an input buffer (302), an output buffer (303), an N-depth buffer (810), a retiming circuit (811), and a synchronization signal generation circuit (812).

  The interface with the memory controller consists of a data signal (802) transmitted and received between the memory controller and the memory sub-controller, a source clock signal (801) for received data, a source clock signal (803) for transmitted data, and a synchronization signal from the memory controller. (800). The address signal and control signal transmitted from the memory controller are considered as part of the data signal (802). The interface with the memory array consists of the data signal (806) transmitted and received between the memory sub-controller and the memory array, the source clock signal (805) for the transmission data, the source clock signal (807) for the reception data, and the synchronization signal to the memory array (804). The address signal and control signal transmitted to the memory array are considered as part of the data signal.

  16 is a block diagram of the 2-depth buffer (N = 2) shown in FIG. 16, a block diagram of a retiming circuit, and data transfer from the memory controller to the memory array when the memory controller and the memory sub-controller are in 2-cycle source synchronous transfer. The operation timing charts are shown in FIGS. 17, 18 and 19, respectively. As shown in FIG. 16, a synchronization signal generating circuit is mounted on the master side of the source synchronous transfer. 16 to 20, the memory controller is the master for data transfer between the memory controller and the memory sub-controller, and the memory sub-controller is the master for data transfer between the memory sub-controller and the memory array.

  The 2-depth buffer in FIG. 17 includes two edge trigger type flip-flops (907), one edge trigger type flip-flop (908) with a reset condition, and several AND / NOT gates.

  The retiming circuit of FIG. 18 selects one edge trigger type flip-flop (907), three edge trigger type flip-flops (908) with reset conditions, a plurality of delay gates (911), and each delay gate passing signal. It consists of M: 1 selector (912) and several AND / NOT gates. The delay signal (911) and the select signal (909) can be adjusted so that the synchronization signal (910) is surely performed in two cycles.

  Next, operations of the 2-depth buffer and the retiming circuit at the time of two-cycle source synchronous transfer from the memory controller to the memory sub-controller will be described with reference to FIG. First, the synchronization signal is asserted in the cycle CK0 from the transmission side (memory controller). In FIG. 16, this signal is output from the synchronization signal generation circuit (812). However, a reset signal of the memory controller and a signal obtained by latching the reset signal with a clock signal may be used. The synchronization signal is transferred to the inside and outside of the memory controller, and internally, the source clock signal (801, 902) is output to the memory sub-controller after 2 cycles when the synchronization signal is asserted based on the synchronization signal. The source clock signal uses T24 which is the opposite phase of the system clock T0 so that the clock edge comes to the center of the data window to be transmitted. The synchronization signal directly output to the outside is input to the memory sub-controller (800, 910). The receiving side (memory sub-controller) adjusts so that the transfer cycle is always 2 cycles. In the memory sub-controller, the assertion of the input synchronization signal is triggered to output the source clock signal (803, 916) to the memory controller, and at the same time, the select signal (913) at the time of retiming operates. In the CK3 cycle, the source clock signal output from the memory controller arrives at the memory sub-controller, and the source clock signal (902) is the trigger and the 2-depth buffer select signal (903) and the trigger clock signal to the 2-depth buffer (903,904) operates. In order to alternately take received data (901) into the 2-depth buffer, the source clock signal (902) is masked with the select signal (903).

  When the memory controller transmits four consecutive data signals at the timing of CK11, the data signal output from the memory controller is input to the memory sub-controller at almost the same timing as the above-mentioned synchronization signal (901). Here, a case where the propagation delay time is 1 cycle or more is shown, and a case where the propagation delay time is 1 cycle or less will be described later. Inside the memory sub-controller, the select signal of the 2-depth buffer that is already operating becomes a mask, and the input data (901) is converted to the 2-depth buffer using the trigger clock signal (903,904) that masks the source clock signal with the select signal. Alternately. As shown in the timing chart of FIG. 19, the data (905, 906) taken into the 2-depth buffer is selected when the select signal (913) is “H”, and the select signal (913) is “ When L ", the data signal (905) is selected. The data signal (914) selected by the select signal is latched by the system clock T0 in order to synchronize with the output timing of the next source synchronous transfer on the memory array side. The latched data signal (915) is sent to the memory array together with its source clock signal.

  The above is data transfer from the memory controller to the memory array, but the reverse is also true for data transfer from the memory array to the memory controller. In FIG. 17, the AND of the source clock signal (902) and the 2-depth buffer select signal (903) is taken, and the 907 flip-flop is used as a clock conditional edge trigger flip-flop, and the source clock signal (902 ) Can be directly connected to the clock terminal of the flip-flop, and the 2-depth buffer select signal (903) can be directly connected to the clock condition terminal of the flip-flop or via a NOT gate.

  FIG. 20 shows a timing chart in which the propagation delay time of signals between the memory controller and the memory sub-controller is within 1 cycle. The basic operation is not different from the case where the propagation delay time in FIG. 19 is 1 cycle or more. However, the synchronization signal is adjusted using the delay gate (911) so that it is always 2 cycle transfer. The difference from FIG. 19 is that the source clock signal transmitted by the memory controller at the timing of CK2 reaches the memory sub-controller within the clock cycle. The data signal transmitted from the memory controller at the timing of CK11 arrives at the memory sub-controller at the same timing as the source clock signal. Since the trigger clock signal (903,904) of the 2-depth buffer is only a mask of the source clock signal (902), the relative time relationship between the data signal (901) and the source clock signal (902) does not change. As in FIG. 19, they are alternately taken into the 2-depth buffer. The trigger clock signal (903,904) of the 2-depth buffer has a period twice that of the source clock signal (902), so the window width of the 2-depth buffer exists for 2 cycles and the propagation delay time is within 1 cycle. However, the data signal can be held until the next cycle. Since the data signal (905, 906) taken into the 2-depth buffer uses the select signal (913) having the same timing as that in the case where the propagation delay time in FIG. 19 is 1 cycle or more, the data transfer cycle does not change to 2 cycles.

  In the above embodiment, the source synchronous transfer of 2 cycles has been described, but the source synchronous transfer of 3 cycles or more can be similarly realized. Also, the present embodiment can be adopted for the embodiments described with reference to FIGS. 1 to 15 to realize multi-cycle source synchronous transfer.

  In the above embodiment, the rising edge of the clock signal is used as the trigger clock signal of the edge trigger type flip-flop. However, the falling edge or both rising and falling edges can be used.

  In addition, clock signals with timings of T14, T24, T34, T18, T38, T58, and T78 are used for source synchronous transfer, but if this clock signal timing can also capture the window of data to be transmitted, Other timings may be used.

  In the above embodiment, the same memory access procedure as that for the SDRAM is shown, but this is an example applied to the synchronous RAM, and the memory array is not limited to the memory module using SDRAM and SDRAM. Absent.

  In the above embodiment, the number of data buses C connected to the memory sub-controller is two. However, this is one example, and the number of data buses C connected to the memory controller is one. Or two or more may be sufficient.

  In all the above embodiments, the processor and the memory array are described, but the I / O bus is not mentioned. However, since the data bus can be classified into the memory array side and the other two with the memory controller in between, the I / O bus is considered to be included in the processor side.

The figure explaining the Example of this invention A diagram for explaining a conventional memory subsystem A diagram for explaining a conventional memory subsystem A diagram for explaining a conventional memory subsystem The figure explaining the method of increasing memory capacity in the conventional memory subsystem The figure explaining the method of increasing memory capacity in the conventional memory subsystem 1 is a block diagram of the memory sub-controller of FIG. 1 when the data rate is doubled without changing the data width in the present invention. Timing chart of the memory sub-controller in FIG. Timing chart of the memory sub-controller in FIG. 1 is a block diagram of the memory sub-controller of FIG. 1 when the data width is ½ and the data rate is quadrupled in the present invention. Timing chart of the memory sub-controller in FIG. Timing chart of the memory sub-controller in FIG. A diagram in which the number of pins of the memory controller is reduced by halving the data width and quadrupling the data rate in the present invention. A diagram in which the data width is halved and the data rate is quadrupled in the present invention to double the number of buses connected to the memory controller. A diagram in which the number of pins of the memory controller is reduced by halving the data width and doubling the data rate in the present invention. Block diagram of memory sub-controller that realizes multi-cycle source synchronous transfer with guaranteed minimum propagation delay Block diagram of the N-depth buffer shown in FIG. Block diagram of the retiming circuit shown in FIG. Timing chart of memory sub-controller realizing 2cycle source synchronous transfer Timing chart of memory sub-controller realizing 2cycle source synchronous transfer

Explanation of symbols

101, 201 ・ Processor
102, 202 ・ ・ Memory controller
103 ・ ・ Memory sub-controller
104, 204 ... Memory array
105, 205 ・ ・ Data bus A
106,206 ・ ・ Data bus B
107, 207 ・ ・ Data bus C

Claims (3)

In a computer system comprising a plurality of processors, a memory controller, and a plurality of memory arrays,
The computer system is provided with a plurality of data transfer paths connecting means between the memory controller and memory array, the first data transfer channel for each data transfer channel connecting means between the memory controller and each of said data transfer path connecting means in connecting, further, the between the data transfer path connecting means said memory array connected by the second data transfer channel for each memory array for each of the data transfer path connecting means, between said memory array and the memory controller Configured to transfer data to each other,
The processor is connected to the memory controller by a plurality of third data transfer paths, and a plurality of the data transfer path connection means are connected to the memory controller,
The first data transfer path and the second data transfer path have the data to be transferred and the clock information of the data transfer different between the first data transfer path and the second data transfer path, and the source synchronous transfer And
The first data transfer path has a smaller data transfer path width and a higher transfer frequency than the second data transfer path,
The computer system according to claim 1, wherein a data transfer bandwidth of the first data transfer path is equal to a sum of data transfer bandwidths of the second data transfer path. The data transfer path connecting means has a control means for transferring transfer data taken in from the data transfer clock information from one of the first data transfer path or the second data transfer path to the other data transfer path. And
  The computer system according to claim 1, wherein data is transferred between the first data transfer path and the second data transfer path. In a computer system comprising a processor, a memory controller and a plurality of memory arrays,
  The computer system includes a plurality of data transfer path connection means between the memory controller and the memory array,
  A first data transfer path is connected between the memory controller and the data transfer path connection means for each data transfer path connection means, and further, the data transfer path connection means and the plurality of data transfer paths are connected for each data transfer path connection means. The memory arrays are connected to each other by a second data transfer path for each memory array, and configured to perform source synchronous data transfer between the memory controller and the memory array,
  The memory controller and the processor are configured to be connected by a third data transfer path,
The data transfer bandwidth of the first data transfer path is equal to the data transfer bandwidth of the third data transfer path, and
  The computer system according to claim 1, wherein a data transfer path width of the first data transfer path is smaller than a data transfer path width of the second data transfer path.

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