JP2008217379A - Serial transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate high-speed transfer even when there is a transfer delay difference between a clock signal line and a data signal line, and to carry out efficient transfer even when transfer requests are made simultaneously. <P>SOLUTION: A serial bus configuration, in which a master module 1 and respective slave modules 2<SB>1</SB>to2<SB>3</SB>are connected by one-to-one connection, is constructed. A parallel-serial converter P/S for write access data and a serial-parallel converter S/P for read access data are arranged, and data transfer is carried out through respective data lines for the respective slave modules. When clock signals ϕ1toϕ3 with different frequencies are selected for each slave module by a multiplexer MUX, data transfer meeting the respective transfer speeds of the slave modules is carried out. In clock selection, a variable configuration by a register REG in the master module or a semifixed configuration by a digital switch DSW is set. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a serial transfer system in which a master module and a plurality of slave modules are coupled by a clock synchronous serial bus to transfer data.

FIG. 3 shows the bus connection of the clock synchronous serial transfer system, and the operation timing in this system is shown in FIG. A clock signal CLK for synchronization is output by the master module 1 and controls the transfer timing of the entire system. Write access outputs a data signal DAT master module 1 is in synchronization with the falling edge of the clock CLK, the slave module 2 ₁ to 2 ₃ fetches the DAT at the rising edge of CLK. At the time of read access, the slave modules 2 ₁ to 2 ₃ output the data signal DAT in synchronization with the fall of CLK, and the master module 1 captures DAT at the rise of CLK.

In such a serial transfer system, since the bus connection between the master module and a large number of slave modules is one system, all slave modules have to have a single transfer rate. As a countermeasure, if you want to transfer only a slave module capable of high-speed transfer at high speed, when transferring to a slave module capable of high-speed transfer, transfer the address of the slave module at low speed, then transfer data at a high speed, and transfer at low speed. In some cases, the clock CLK is controlled so that addresses and data are transmitted at a low speed (for example, see Patent Document 1).
JP 2001-320390 A

  There are three problems with the configuration of FIG. One is that, as shown in FIG. 4, DAT is taken in at the rising edge of CLK both at the time of reading and at the time of writing. When the delay difference tSKW between the two signals becomes large, these cannot be satisfied. This factor includes a difference in load capacity between CLK and DAT. In the CLK and DAT inputs of the slave module, CLK is generally connected to the input side of the unidirectional IC, and DAT is generally connected to the bidirectional IC. A difference in capacitance occurs due to the difference in the input IC. As the number of slave modules increases, the capacity difference increases and the delay difference also increases.

  Therefore, as the number of slave modules increases, the margin of the setup time tS and the hold time tH decreases. Therefore, the CLK frequency is lowered to increase the period, and the setup time tS and the hold time tH are secured. This slows down the transfer rate.

  The second problem is that when a plurality of slave modules are connected, CLK and DAT are multi-drop as seen from the master module, and the load form differs for each slave module, so the delay difference between CLK and DAT differs. This analysis requires analysis with distributed constants, and is complicated.

  The third problem is that the clock CLK and the data signal DAT need only be one system, but when the master module is transferring data to one slave module, data transfer with other slave modules is not possible, and transfer requests occur simultaneously. Is inefficient because it requires waiting time.

  An object of the present invention is to provide a serial transfer system that facilitates high-speed transfer even for transfer delay differences between a clock signal line and a data signal line, and that enables efficient transfer when transfer requests occur simultaneously.

  In order to solve the above problems, the present invention has a serial bus configuration in which a master module and each slave module are connected in a one-to-one connection, and a parallel-serial converter for write access data and a read access in the master module. A serial-parallel converter for data is provided to perform data transfer through each data line for each slave module, to perform data transfer using a clock signal having a different frequency for each slave module, and to select a register in the master module And a variable setting by a multiplexer or a semi-fixed setting by a digital switch and a multiplexer.

(1) A serial transfer method in which a master module and a plurality of slave modules are coupled by a clock synchronous serial bus to transfer data,
A serial bus configuration in which the master module and each slave module are connected one-to-one is used.

  (2) The master module includes a parallel-serial converter for write access data and a serial-parallel converter for read access data, and performs data transfer through each data line for each slave module.

  (3) The master module performs data transfer in accordance with individual transfer rates of the slave modules by selecting clock signals having different frequencies for each slave module with a multiplexer.

  (4) The master module is characterized in that the clock is selected by a variable setting by a register in the master module or a semi-fixed setting by a digital switch.

  As described above, according to the present invention, the transfer delay difference between the clock signal line and the data signal line can be easily transferred at high speed, and the transfer can be efficiently performed when transfer requests occur simultaneously. Specifically, the following effects are obtained.

  -The signal lines of the clock signal CLK and the data signal DAT are prepared for the slave modules, and the master module and the slave modules have a one-to-one serial bus configuration, so that the difference in the load capacity between the CLK and DAT is the number of slave modules. The setup time and hold time can be made constant without depending on. Therefore, the transfer rate can be improved over the conventional method.

  -The signal lines of the clock signal CLK and the data signal DAT are prepared for the slave module, and the master module and the slave module have a one-to-one connection serial bus configuration, so that the transmission end and reception end of the CLK and DAT can be fixed, The delay difference between CLK and DAT can be made uniform in all slave modules.

  -By preparing the parallel-serial converter P / S for write access data and the serial-parallel converter S / P for read access data for the slave modules, transfer between the master module and a plurality of slave modules is almost simultaneously performed. It becomes possible to do.

  By selecting a clock signal CLK having a different frequency for each slave module, the frequency of CLK can be selected for each slave module, and an optimum transfer rate can be selected.

  -The clock signal can be easily changed with a different frequency for each slave module by variable setting with a register.

  -The semi-fixed setting of the clock signal by the digital switch can easily change the transferable speed while reducing the load on the CPU in the master module.

(Embodiment 1)
FIG. 1 is a system configuration diagram showing an embodiment of the present invention. As shown in the figure, for the serial bus, the clock signal CLK line and the data signal DAT line are prepared for the number of slave modules, and the master module 1 and the slave modules 2 ₁ to 2 ₃ are connected one-to-one. Make the configuration.

  With this serial bus configuration, the difference in load capacity between the CLK signal line and the DAT signal line does not depend on the number of installed slave modules. Thereby, the setup time and the hold time can be made constant. Therefore, the transfer rate can be improved over the conventional method.

  Further, it is possible to avoid the occurrence of a delay difference between the clock signal CLK and the data signal DAT for each module. That is, the transmission end and the reception end of the clock signal CLK and the data signal DAT can be fixed, and the delay difference between CLK and DAT can be made uniform in all slave modules.

Next, in the master module 1, parallel-serial converters P / S for write access data and serial-parallel converters S / P for read access data are prepared for the number of slave modules. Almost simultaneous data transfer between the plurality of slave modules 2 _{1 to} 2 ₃ is enabled. In the master module 1, data is exchanged between the CPU and the converter P / S or the converter S / P by a parallel bus, and the master module 1 and the plurality of slave modules 2 ₁ to 2 ₃ are almost simultaneously. High-speed processing of transfer data.

  Next, a multiplexer MUX is provided in the master module 1 so that the clock CLK for each slave module can be selected. Clocks φ1 to φ3 having different frequencies are prepared for each slave module, and these clocks φ1 to φ3 can be selected by a multiplexer MUX so that a transferable speed can be selected. As a result, even when there is a difference between the high and low transfer rates of the slave modules, data transfer can be performed at a transfer rate optimum for them. In this clock selection, the conversion speeds of the parallel-serial converter P / S for write access data and the serial-parallel converter S / P for read access data are also synchronized.

  Next, the clock selection of the multiplexer MUX that selects the clock signal CLK in the master module 1 is performed by the register REG. In the software setting, clocks φ1 to φ3 having different frequencies can be selected for each slave module, and the transferable speed can be selected. As a result, only the clock needs to be selected when speeding up the system, such as when the slave module is switched from a low transfer rate to a high transfer rate.

(Embodiment 2)
A system configuration according to this embodiment is shown in FIG. 1 is different from FIG. 1 in that a clock of a multiplexer MUX that selects CLK in the master module 1 is selected by a digital switch DSW.

  By selecting the clock by this switch setting, it is possible to select semi-fixed clocks φ1 to φ3 having different frequencies for each slave module, and it is possible to easily change the transferable speed while reducing the CPU load compared to the first embodiment. To do.

1 is a system configuration diagram showing Embodiment 1 of the present invention. The system block diagram which shows Embodiment 2 of this invention. Clock synchronous serial bus connection diagram. Operation timing of the clock signal CLK and the data signal DAT.

Explanation of symbols

1 Master module 2 _{1 to} 2 ₃ Slave module P / S Parallel-serial converter S / P Serial-parallel converter MUX Multiplexer REG Register DSW Digital switch

Claims (4)

A serial transfer system that transfers data by connecting a master module and multiple slave modules via a clock synchronous serial bus.
A serial transfer system characterized in that the master module and each slave module are connected in a one-to-one connection.   The master module includes a parallel-serial converter for write access data and a serial-parallel converter for read access data, and performs data transfer through each data line for each slave module. The serial transfer method described.   3. The serial transfer according to claim 1, wherein the master module performs data transfer in accordance with an individual transfer speed of the slave module by selecting a clock signal having a different frequency for each slave module with a multiplexer. 4. method.   The serial transfer system according to any one of claims 1 to 3, wherein the master module uses a variable setting by a register in the master module or a semi-fixed setting by a digital switch for clock selection.

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