JP2004295915A5 - - Google Patents

Claims (4)

  In a memory subsystem comprising a memory controller and a memory array, a data transfer path connection means is provided between the memory controller and the memory array, and the memory controller and the data transfer path connection means are connected by a first data transfer path, A data transfer path connecting means and a memory array are connected by a second data transfer path, and the first data transfer path and the second data transfer path have data fetching clock information together with data. system.   The first data transfer path and the second data transfer path are characterized in that the first data transfer path has a smaller data transfer path width and a higher transfer frequency than the second data transfer path. Item 1. The memory subsystem according to item 1.   The data transfer path connecting means has control means for transferring data transferred from clock information for data fetching at different frequencies between the first data transfer path and the second data transfer path. The memory subsystem according to claim 1. 2. The memory subsystem according to claim 1, wherein the first data transfer path and the second data transfer path form a bus configuration, and have a dedicated line as data fetch clock information.